Tuning capacitance to enhance FET stack voltage withstand

Information

  • Patent Grant
  • 10951210
  • Patent Number
    10,951,210
  • Date Filed
    Monday, March 9, 2020
    4 years ago
  • Date Issued
    Tuesday, March 16, 2021
    3 years ago
Abstract
An RF switch to controllably withstand an applied RF voltage VSW, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of VSW appearing across it may be controlled to approximately zero.
Description
BACKGROUND
1. Field

The present disclosure relates to electronic integrated circuits (“ICs”), and more specifically to circuits comprised of stacked transistor devices for switching high frequency signals.


2. Related Art

Most radios, cell phones, TVs, and related equipment today require an “RF switch” to control connections between various transmitter and receiver circuits (“RF” is used generically herein to mean any reasonably high frequency ac signal). FIG. 1 is a simplified schematic diagram of a typical, simple two throw switch that may by used to switch, for example, a single antenna 102 between a transmit signal source 104 and a receive circuit 106. Switches S1 108, S2 110, S3 112 and S4 114 are represented by a mechanical single pole single throw switch symbol. Typically, the switches are controlled such that when S1 is “closed” or conducting at low impedance, S2 is “open” or high impedance. Because no switch is perfect, the node of a transmit/receive switch (such as S1 108 or S2 110) farthest from the antenna is typically shunted to circuit common to reduce the effects of signal leakage through such switch when it is open. Thus, as S2 110 is illustrated in the “open” state, the corresponding shunt switch S4 114 is “closed” to terminate the Receive SRF signal on node 106 to ground 116. Conversely, the shunt switch S3 112 is “open” condition because its corresponding signal switch S1 108 is “closed” to conduct the Transmit SRF signal on node 104 to the antenna 102. To couple the antenna 102 to the receive circuit, the condition of all four switches would typically be inverted to that shown in FIG. 1.


In modern circuits, RF switches such as represented in FIG. 1 are most often implemented using semiconductor devices, typically some form of field effect transistor (FET). Semiconductor RF switches are commonly fabricated using insulated gate FETs, often generically called MOSFETs despite the fact that many do not employ the original metal/oxide/semiconductor construction that gave rise to that acronym. Non-insulating gate FETs, such as junction FETs (JFETs), are also commonly used, particularly with certain semiconductor materials such as GaAs. Each switch may be implemented using a single FET, or, as described herein, a multiplicity of FETs stacked in series.


The impedance of ON (conducting) switches is generally sufficiently low that the voltage developed across it in this condition is negligible. However, switches that are OFF (nonconducting, or high impedance) must typically support the full voltage of the RF signal they control. Thus, the RF power that can be controlled by a semiconductor RF switch depends on its voltage withstand capacity, which in turn depends on the drain-to-source breakdown voltage (BVds) of its constituent transistor(s). In FIG. 1, both S2 110 and S3 112 must withstand the transmit signal voltage SRF with respect to ground.


Integrated circuit fabrication requires many compromises. In particular, many IC transistors that are otherwise highly effective for switching RF signals have a modest BVds, and thus may be inadequate to control signals of substantial amplitude. One solution may be to employ alternative transistor designs yielding higher BVds. However, the tradeoffs necessary to fabricate transistors with higher BVds in an integrated circuit may be burdensome. For example, such design may be incompatible with other circuitry desired for the integrated circuit, or it may otherwise be uneconomical.


Therefore, many semiconductor RF switches today stack a multiplicity of low BVds transistors in series to improve the breakdown performance of the overall switch. FIG. 2 represents an example of such a stacked-transistor semiconductor switch. The switch is disposed between a first node N1 202 and a second node N2 204, and is controlled by a voltage VControl 206. To form the overall switch, a multiplicity j of FETs are “stacked” in series connection, from drain to adjacent source. Thus, a first transistor M1 has a source coupled to N1 202, and a drain coupled directly to the source of a second FET M2 210. Additional FETs, represented by a series of dots, may be similarly connected above M2 210, the drain of the last such intervening FET being coupled to the source of the top or jth FET of the stack, FET Mj 212. Each FET of the stack is controlled by VControl as coupled to the FET's gate via a corresponding gate impedance, such as the base resistances RB1 214, RB1 216, . . . , RBj 218 that are illustrated.


Though the FET channel terminal closer to N1 is referred to as the “source,” and the opposite terminal as the “drain,” this is not a requirement. FETs may be implemented in a wide variety of designs and polarities (e.g., N channel FETs and P channel FETs; enhancement and depletion modes, and various threshold voltages, etc.). Moreover, the circuits in which transistors are employed may be illustrated using different conventions than are followed herein. Transistor polarity and drain-source orientation may often be interchanged without significantly altering the principle of operation of a circuit. Rather than illustrate the numerous possible permutations of drawing conventions, transistor polarities, and transistor designs, it should be well understood by those skilled in the electronics arts that the exemplary description and figures illustrated herein equally represent all such alternative circuit descriptions and equivalent device designs.


For most RF switch purposes, base impedances (represented in FIG. 2 as resistors RBx 214, 216, 218) should combine with the effective corresponding gate capacitance of the FET to form a low-pass filter whose transfer function has at least a single pole roll-off at a frequency that is less than 1/6 the lowest (expected) design frequency for the signal that will exist between N1 and N2. Indeed, the at least one pole frequency is preferably 1/10 such lowest design signal frequency, or even lower. Such low frequency base control permits the gate voltage of each FET to follow the voltage on the channel of the FET, thus assuring the correct “on” or “off” gate/source voltage (Vgs), and also limiting both Vgs and the drain/gate voltage (Vdg) to prevent breakdown of the gate insulation.


Ideally, stacked device switches such as shown in FIG. 2 have a net voltage withstand capacity equal to BVds of the individual FETs, multiplied by the number (j) of FETs in the stack. Thus, a stack of 10 transistors each having BVds of 1.8 V would ideally be capable of switching a signal having a peak amplitude of 18 V. In practice, unfortunately, such stacks may be unable to support such ideal voltage. The voltage withstand capacity can be increased by increasing the number of devices in the stack, but this may cause large increases in the corresponding required integrated circuit area.


For example, assume that BVds for a given fabrication process is 2V (i.e., each single transistor can handle 2V), but that a 16V signal must be controlled. A stack of eight transistors should ideally be able to control a signal of peak amplitude 16V. If eight transistors prove insufficient for this task in practice, then more transistors must be added to support the required voltage. Unfortunately, the series resistance of the stack is the sum of the individual device resistances. Consequently, as the number of stacked devices increases by a factor S, so does the ON resistance of the switch. Therefore, to maintain the required overall ON resistance (or insertion loss), the impedance of each device must be reduced by the factor S. This, in turn, requires that the area of each such device is increased by the factor S. Given S additional FETs, each with an area increased by S, it is clear that the total area of the FETs in the stack will increase as S2. At some point, the switch area can be immense. Moreover, the parasitic capacitances of these transistors typically increase with the area, and this can lead to numerous additional problems.


Thus, there is clearly a need to identify and solve the problem that prevents some stacked FETs from controlling the ideal voltage, i.e., the number of FETs times the BVds of the individual FETs. Embodiments of devices and methods of manufacturing such devices are described herein that can mitigate or eliminate the noted problem, thus enabling stacked transistors to withstand voltages that approach, or even equal, the theoretical maximum for a given BVds of the constituent transistors.


SUMMARY

Research into observed failures of some stacked transistor RF switches at lower than expected applied switch voltages (Vsw) led to a conclusion that small parasitic capacitances (Cpd), previously thought negligible, were unexpectedly causing significant imbalances in the distribution of Vsw across the individual transistors of the stack. To reduce the distribution imbalances, capacitance to internal stack nodes is added or intentionally modified, in contrast to the previous practice of merely making drain-source capacitances (Cds) uniform for the series-connected (stacked) transistors.


One embodiment is a stacked transistor RF switch comprising a multiplicity of constituent transistors (e.g., FETs) of the stack all coupled in series connection drain to source to form a series string for which internal nodes are those between adjacent transistors. This embodiment includes effective drain-source capacitance Cds that is significantly different for one transistor than for another transistor of the stack. Their relative Cds values may differ by an amount of at least 2%, 5%, or 10%, or by at least 0.5% between each of a majority of pairs of constituent transistors, and/or so as to effectively tune capacitances of the stack. Tuning is effective if a variance of the magnitude of Vds-off as distributed across all constituent transistors increases when the Cds values are made substantially more equal. An embodiment may include a discrete capacitive element coupled to an internal node of the series string, and/or may include transistors having different Cds values due to design differences, and may have different Cds between a majority of pairs of transistors of the stack.


Another embodiment is also a stacked transistor RF switch comprising a multiplicity of constituent transistors (e.g., FETs) of the stack all coupled in series connection drain to source to form a series string for which internal nodes are those between adjacent transistors. This embodiment includes a discrete physical capacitor element Ccomp that effectively tunes capacitances of the transistor stack by being coupled to an internal node of the series string. Tuning is effective if a variance of the magnitude of Vds-off as distributed across all constituent transistors increases when all Ccomp capacitor elements are removed. Ccomp capacitors may be fabricated as metal-insulator-metal (MIM) capacitors, or may be any other distinct physical feature having an impedance that is predominantly capacitive at the frequency (a primary frequency) of a signal ordinarily switched by the RF switch.


A further embodiment is a method of fabricating an RF switch comprising a multiplicity of series connected constituent transistors in a series string for which internal nodes are those between each pair of adjacent transistors, and includes a step of establishing significantly different values for total effective drain-source capacitance Cds of different transistors in the stack. Significantly different values may be those varying by at least 2%, 5%, or 10%, or by at least 0.5% between each of a majority of pairs of constituent transistors, and/or may be such as to effectively tune capacitances of the stack. Tuning is effective if a variance of Vds-off as distributed across all constituent transistors due to a voltage Vsw applied across the RF switch would increase if the effective drain-source capacitances were substantially more equal. The method may include an additional step of determining parasitic drain capacitances, other than drain-source capacitances, coupled to internal nodes in the series string, and may include a further step of determining voltages of nodes to which the parasitic drain capacitances are coupled as compared to voltages on endnodes of the RF switch. The method may include a further capacitance balancing step of establishing values of the capacitances coupled to a particular internal node of the series string of stacked transistors and multiplying each such capacitance value by a number reflecting a proportion of Vsw appearing across the capacitance in operation to voltage-weight the capacitance, such that a sum of such voltage-weighted capacitances is approximately zero for the particular node. The method may further include thus balancing a node between each of a majority of adjacent transistor pairs, or even thus balancing a node between each adjacent transistor pair of the stack.


A yet further embodiment is a method of fabricating an RF switch comprising a multiplicity of series connected constituent transistors in a series string for which internal nodes are those between each pair of adjacent transistors, and includes a step of coupling a discrete capacitive feature, or alternatively at least two discrete capacitive features, to one or more internal nodes of the stack. A discrete capacitive feature is a distinct element having an impedance that is predominantly capacitive at the frequency of a signal that is ordinarily switched by the RF switch, and the added capacitive feature(s) may be required to effectively tune capacitances of the stack, such that a variance of magnitude in Vds-off as distributed across all constituent transistors due to an RF switch voltage Vsw applied across the RF switch increases when all such discrete capacitive features are omitted. The method may include an additional step of determining parasitic drain capacitances Cpd that are coupled to an internal node in the series string, and also may include determining voltages of nodes to which the parasitic drain capacitances are coupled as compared to voltages on endnodes of the RF switch. The step of determining parasitic drain capacitances may include analyzing semiconductor device layout geometric parameters including parameters descriptive of interconnection traces. The method may include a capacitance balancing step of weighting each value of the capacitances coupled to a particular internal node of the series string of stacked transistors according to a number reflecting a proportion of Vsw appearing across the capacitance in operation, such that a sum of such weighted capacitance values is approximately zero for the particular node. The method may further include performing the balancing step for each of a majority of the internal nodes of the series string, or for all of the internal nodes of the series string.





BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will be more readily understood by reference to the following figures, in which like reference numbers and designations indicate like elements.



FIG. 1 is a simplified schematic diagram of a simple transmit/receive RF switch.



FIG. 2 illustrates a basic FET stack designed to function as an RF switch device.



FIG. 3 illustrates voltage division across j stacked FETs in an RF switch that is “off.”



FIG. 4 illustrates effective parasitic drain capacitances Cpd for FETs in a stack such as illustrated in FIG. 2.



FIG. 5 is an equivalent circuit illustrating effects of a parasitic drain capacitance Cpd.



FIG. 6 is an equivalent circuit illustrating an addition of tuning capacitance between stack nodes to compensate Cpd in a circuit such as represented by FIG. 5.



FIG. 7 is a graph illustrating the relative Vds of each of the transistors in a stack of 16 transistors as a function of a ratio of Cpd to Cds values.



FIG. 8 is a graph illustrating the effective number of transistors in transistor stacks having 2 to 16 transistors, as a function of a ratio of Cpd to Cds values.



FIG. 9 schematically illustrates further capacitance details of circuits such as illustrated in FIG. 4.





DETAILED DESCRIPTION

The background set forth above describes a typical stacked RF switch, as illustrated in FIG. 2. FIG. 3 illustrates how a switch such as shown in FIG. 2 should divide an applied RF voltage, such as (Vs 302-VRef 304) such that equal voltages are imposed on each of the j FETs in the stack. When the switch is off (and presuming VRef is zero), VS 302 is applied to the endnodes 302-304 of the stack. Though each FET is in a high impedance state, the switch conducts somewhat due to the effective drain-source capacitances Cdsx corresponding to each FETx. Because the “off” conduction is almost entirely due to these capacitances, the FET structure itself is not shown, but only the j corresponding effective drain-source capacitances Cds1 306, Cds2 308, Cds3 310, . . ., Cds(j−1) 312 and Cdsj 314. This capacitive divider distributes the impressed voltage VS across each corresponding drain node to produce Vd1 316, Vd2 318, Vd3 320, . . ., Vd(j−2) 322 and Vd(j−1) 324.


If each Cds has the same value, it appears that VS should divide uniformly across the FETs such that Vd1 (all voltages with respect to VRef) is Vs/j, Vd2 is 2*Vs/j, and so on, with Vd(j−1)=(j−1)Vs/j. Because of this expected result, stacked FET devices have previously been fabricated to establish Cds for each FET at substantially the same value. Other parasitic capacitances in such FET stacks are generally quite small relative to Cds, and moreover typically do not directly divide the impressed voltage. Accordingly, the effects of such other parasitic capacitances have been largely ignored in regard to voltage division across the FETs in stacked-FET RF switches.


The series coupling of transistors to form a stacked switch as represented, for example, in FIG. 2 forms a path for conduction when the switch is “on.” In that “on” condition, the conduction path couples together the endnodes (N1 202 on the “bottom” and N2 204 on the “top”) via the channels of all of the constituent FETs M1 208 to Mj 212. Only nodes along such conduction path will be referred to herein as “series nodes” or “nodes of the series string” of a transistor stack or stacked switch. Typically, most of the series string nodes are either a drain or a source of a constituent FET, which are so closely coupled that all such nodes may be called “drain nodes.” However, other elements may be disposed in the series string of a transistor stack, and if so may have nodes that are on the conduction path, and that are therefore also “series nodes” or “nodes of the series string.”


Voltage Distribution Inequality Due to Parasitic Drain Capacitances


After examination of a problem of unexpectedly low voltage breakdown for stacked-FET RF switches, the Applicant determined that voltage distribution across the FETs in such stack was not uniform. Therefore one FET generally experienced a larger proportion of the total applied switch voltage than any other FET in the stack. That most heavily stressed FET failed first, leading to failure of the other


FETs in a domino-like effect. Upon further investigation, the Applicant determined that the voltage distribution inequalities are often caused by parasitic capacitances that are small compared to the drain-source capacitances, and hence have been previously overlooked.


As noted above, drain parasitic capacitance (Cpd) values are generally not more than a few percent of the corresponding drain-source capacitance Cds. As such, Cpd has often been ignored when calculating the expected voltage distribution. Even small values of Cpd, however, may have large effects on the voltage distribution, depending upon the node to which such Cpd is coupled. A Cpd coupling a drain to a node Np that experiences some combination of the signals at the RF switch endnodes may inject such signals into the drain, changing the distribution of voltages across the FETs of the stack from the ideal equality to something less desirable. That is, if the node Np experiences a signal that comprises (A*V1+B*V2), where A and B are possibly complex or even time-varying multipliers, V1 is the voltage at one end of the “open” RF switch, and V2 is the voltage at the other end of the open RF switch, then a signal will be injected into the corresponding drain that distorts the distribution of (V2−V1) across the FETs. Any Cpd that couples to such an Np (a node having a significant component of (A*V+B*V2)) may be relevant to net voltage distribution. When the signal on such Np differs greatly from the “ideal” drain voltage, the signal injection and resulting voltage distribution inequality can be quite substantial, even if Cpd is small, due to the large voltage across it. This effect is described in more detail below with reference to FIG. 4.


Not all integrated circuit technologies have been equally successful in enhancing RF switch breakdown voltage by stacking devices in series. In some technologies, Cpd may be quite obviously significant in comparison with a corresponding Cds, and hence would not be overlooked. However, the problem has also not been recognized or resolved with these technologies, possibly because the performance has been so bad that the issue has not been pursued. Indeed, the very large parasitic components might possibly be an important reason that stacked switch designs have not been pursued using some integrated circuit technologies.


Special case: parasitic drain capacitances Cpd are predominantly disposed between a corresponding drain and ground. In a special case, each significant Cpdn, for 1<=n<=(j−1), is coupled to a common voltage VCOM (e.g., ground) to which one end of the corresponding RF switch is connected. Stated differently, each Npn experiences essentially the same signal as does one end of the RF switch, typically VCOM or ground. This special case is addressed first for two reasons: first, it approximates many practical switches; and second, it is conceptually simple.


An RF switch is often disposed between an RF signal node and a ground or circuit common node. This is the situation, for example, for RF switch S3 112 of the transmit/receive antenna switch circuit illustrated in FIG. 1. As shown in FIG. 1, the transmit RF signal Transmit SRF 104 is imposed on one side of S3 112, while the other side of the switch S3 is connected to ground 116. It is also not unusual for parasitic drain capacitances Cpd to be predominantly coupled to a ground plane. For example, Cpd may predominantly consist of parasitic capacitances to a substrate, and such substrate may be held at ground potential (at least for RF purposes). At least when both of these conditions exist, the special case arises in which each relevant Cpd is coupled to the signal at one end of the RF switch. In such special case, the Cpd of each FET will have an effect on the (off) RF switch voltage distribution that is roughly proportional to the value of such Cpd multiplied by the number n of the FET, where n=1 for the FET whose source is coupled to VCOM or ground, such that n indicates how many FETs are connected in series between the drain of FETn and VCOM or ground.



FIG. 4 illustrates three FETs 402, 404 and 406 within a stack of j FETs that are disposed between a first node N1 202 and a second node N2 204. For purposes of understanding the special case, it is temporarily assumed that N1 202 is ground, and that Npn 410 and Np(n−1) 414 are also coupled to ground for at least RF signals. It is also presumed that the ideal voltage on Dn (the drain of the center FET Mn 402) is (n/j)VN2. Such ideal voltage distribution obtains in the RF switch reflected by FIG. 4 if, for example, all values Cds are equal, and all values of Cpd are truly negligible. It is also momentarily assumed that all values of Cds are indeed equal, and further that all values of Cpdx, for x unequal to n, are truly negligible.


The effect of Cpdn 408 on the signal present on the drain Dn 502 of FETn may then be analyzed with reference to FIG. 5, which is an equivalent circuit for FIG. 4 that reflects the conditions and assumptions noted above. The equal-valued Cds capacitances for the (j−n) FETs above FET Mn are equivalent to a capacitor 504 having a value of Cds/(j−n). Similarly, the Cds for the lowest n FETs are equivalent to a capacitor 506 having a value Cds/n. As noted above, Cpd values have conventionally been ignored because they are generally not more than about 2% of the values of Cds. Consideration of FIG. 5 reveals, however, that the effect of Cpdn is much greater than suggested by its size in proportion to Cds, at least when n approaches j for large stacks. For example, let j=16, n=15, and Cpdn =2% of Cds. Though Cpdn is only 2% as large as Cds, it is 30% as large as the equivalent capacitor (capacitor 506) that is parallel to Cpdn; as such, Cpdn is clearly not negligible. In fact, the resulting voltage at Dn 502 becomes (0.9202)N2, rather than the ideal value (were Cpdn not present) of (15/16)N2 or (0.9375)N2. Just a single Cpd15, having a value only 2% that of Cds, thus causes the drain-source voltage across M16 to be (1.276/16)N2 rather than (1/16)N2, which is a 27.6% increase in Vds16. Moreover, the effect is greatly increased when each Dn has a corresponding Cpdn to ground, as illustrated in FIG. 7.



FIG. 7 is a graph showing the relative distribution of the drain-source voltage Vdsn for each of the FETs (n=1 to 16) in a stacked RF switch, as a function of the size of Cpd with respect to Cds. Relative Vds is the Vds for each FETn, compared to the voltage of N2/j. Because j is 16 in this example, Relative Vds is the Vds of the particular FET compared to 1/16 of the RF switch voltage. A curve is provided for each of the 16 FETs in the stack, which are labeled on the right side of the graph as space permits.


As expected from consideration of FIG. 5, FIG. 7 shows that the disparity between the ideal expected voltage across each FETn is most pronounced at the ends of the stack, i.e., for n=1 and for n=16; and the magnitude of the Vdsn increases for higher values of n. Indeed, FET16 experiences a relative voltage 200% larger than the ideal value (Relative Vds=2) when each Cpd is just 1.6% as large as Cds. The assumptions for this figure are that each Cds has the same value, each Cpd has the same proportional value of Cds, and each Cpd is coupled to a node that is the RF signal equivalent to the voltage at the source connection of FET M1, e.g., ground.



FIG. 8 also reflects the effect of uncompensated Cpd capacitances as a function of the ratio of Cpd to Cds. The Effective Stack Height is the actual withstand voltage of the RF switch in units of BVds, which is assumed the same for each stack transistor. The Effective Stack Height for stacks of j FETs are shown for actual stack heights j=1 (no stack at all) to 16 transistors. When the drain parasitic capacitances Cpd are very small (0.0001, or 0.01% as large) compared to the drain-source capacitances Cds, the stack operates nearly ideally, with a withstand voltage of j multiplied by the BVds of each FET. Thus, when the Cpd/Cds ratio=0.0001, a stack of 13 FETs (j=13) behaves essentially like an ideal stack of 13 devices, and hence it begins at an effective stack height of 13. Each other trace similarly begins at an Effective Stack Height value equal to the actual stack height of the switch, so the traces need no labeling. As the ratio of Cpd/Cds increases, the effective stack height decreases, because uncompensated Cpd values cause unequal distribution of voltage over the FETs of the stack, decreasing most rapidly for the largest stack (j=16). As the ratio of Cpd to Cds increases, the transistors no longer equally share the source voltage, and the top transistor in the stack, Mj, typically experiences significantly more voltage than any other transistor. When Mj breaks down, the remaining transistors follow suit in a domino effect, so the effectiveness is limited by the voltage across Mj. For a stack of 16, the ideal breakdown voltage of the stack would be 16×BVds, but at a Cpd/Cds ratio of only 1.6% (0.016), it will fail at 8×BVds, thus having an effective stack height of 8.


For the special case, at least, it is thus clear that if Cpd values are not taken into account the stack is likely to fail at a much lower voltage than expected. The FET that is positioned furthest from the ground connection of an RF switch will most likely fail first, at a total RF switch voltage that may be a fraction of the ideal or expected peak voltage. Some solutions to this problem are set forth below for the special case, followed by a generalization of the problem and corresponding general solutions.


Solutions for the Special Case



FIG. 6 is an equivalent circuit similar to that of FIG. 5, and illustrates a set of solutions that differ from each other according to a value of k. To compensate or tune a node Dn 502, a node D(n+k) 602 is selected based on factors such as ease of layout and effectiveness of the node 602. Nodes of higher k may be more effective, as described below. As an example, if j=16 and n=10, k may be set to any value from 1 to 6 (i.e., j−n). Selection of the node 602 results in a capacitor 604 composed of the series combination of those Cds that are above D(n+k) 602. Capacitor 604 therefore has a value of Cds/(j−n−k), for k<(j−n). When k=(j−n), of course, there is no capacitor 604 because D(n+k) 602 is tied directly to N2 204. As in FIG. 5, a capacitor 506 represents the series combination of the Cds of all FETs up to FET Mn and hence has a value of Cds/n. The capacitor 506 is coupled, together with Cpdn 408, to ground 116. Tuning is achieved by adding a compensation capacitor Ccompn 608 to compensate for the disruptive effects of Cpdn 408.


In one conceptually simple solution, k=(j−n) so that D(n+k) 602 is tied directly to N2 204. Perfect tuning of Dn 502 is then readily achieved by making Ccompn 608 equal to Cpdn*(n/k). This turns out to be the solution for any value of k. Such tuning is an iterative process, because the node D(n+k) 602 will need to be subsequently compensated due to the effect of Ccompn 608. In this special case (Cpd components all effectively coupled to the source of M1), solutions of the form illustrated in FIG. 6 are most readily implemented by first compensating the node D1 (Cdp1), and then proceeding to compensate each successive drain node.


It may be useful in some embodiments to let k=1, such that Ccompn is simply disposed parallel to the channel of M(n+1). One advantage may be the relative simplicity of disposing Ccompn between two nearby nodes. Another advantage may follow if the design of M(n+1) can be altered such that the inherent capacitance Cds(n+1) is significantly increased. Changes to the layout and design of the transistors M1 to Mj may reduce the size of the needed Ccomp capacitances, and may even obviate a need for some discrete Ccomp capacitances.


On the other hand, if k>1 (i.e., if Ccomp is coupled to a drain of a transistor higher in the stack), then the actual capacitance required for such Ccomp will generally be proportionally reduced as k increases. Note, however, that the breakdown voltage of such Ccomp must correspondingly increase. To implement the special case solution when k>1 requires discrete Ccomp capacitors to bridge a plurality of FETs. In the special case (i.e., when the various effective Cpd are predominantly coupled to a node equivalent to the end of the RF switch that is coupled to the lowest transistor M1), a k>=1 solution may be implemented by disposing Ccomp capacitors between drain nodes Dn and a drain D(m>n). Drain D(m>n) may, for example, be a node equivalent to the end of the RF switch to which Mj is coupled.


The desirability of such coupling to drains of FETs that are more remote in the stack depends on the fabrication parameters and layout of the target RF switch. Factors tending to make such remote-node coupling desirable include: a) a layout that lends itself to such connection, especially if the Ccomp layout create no further undesirable parasitic capacitances; b) availability of a capacitor suitable for voltages greater than BVds; and c) a dearth of space available for such capacitors. Indeed, if the breakdown voltage BVc of a compensating capacitor is sufficiently high, it may be useful to couple the compensating capacitor to that endnode of the RF switch that is opposite the node to which the Cpd to be compensated is most closely coupled. The capacitance required for a compensation capacitor is proportional to 1/m, where m is the number of series FETs across which such compensation capacitor is coupled. This effect may permit compensation capacitors disposed across a plurality of FETs to occupy less die area, which is almost always beneficial.


The best tuning embodiment thus depends, among other things, on the accessibility of the various drain nodes, as well as on the suitability of capacitors that are compatible with the fabrication parameters, as well as on the space available for such capacitors and whether or not they can be fabricated atop other structures without adding die area. If tuning creates difficulties in layout, it may be desirable to compensate less than perfectly, permitting j to increase slightly.


A further tuning solution applies to the special case (in which each Cpd is coupled to ground or N1), and in a basic form uses compensation capacitance only across single transistors (i.e., k=1). Conceptually, this further solution first compensates for Cpd1 by increasing the effective Cds2 by an amount equal to Cpd1. Next it compensates for Cpd2 by increasing the effective Cds3 by an amount equal to Cpd2, but increased by a factor of 2 (i.e., 2Cpd2) because Cpd2 is coupled across two transistors, M1 and M2. Furthermore, Cds3 must be increased over Cds2, which has already been increased by the value of Cpd1. All Cpd being equal, and all original Cds being equal, and for n>1, each effective Cds should be increased by an amount Ccompn determined according to the following geometric progression:










Ccomp
n

=




i
=
1


n
-
1




i
×

Cpd
i







(

Eqn
.




0

)








Though conceptually described as beginning with compensation of Cpd1, note that the equation may be evaluated in any order. All compensations must be present at the time of fabrication, of course, and thus there can really be no “order” of compensation.


Compensation or tuning can rarely be absolutely precise, and the value of further precision certainly approaches zero for uncompensated Cpd values that are 0.01% of Cds or less. Smaller stacks tolerate greater imprecision. In the case illustrated in FIG. 5, the single Cpd15 that was presumed present resulted in a Vds16 increased over the ideal value by only a factor of 1.28. Yet FIG. 7 suggests that the result for the same transistor, M16, when each drain has a corresponding Cpd, would be that Vds16 have approximately a factor of 2.2 greater than the ideal. Thus, while a single parasitic capacitance may not be negligible, it is unlikely to cause severe voltage distribution imbalances by itself. Therefore, errors in tuning any one particular node may be unimportant if most of the nodes are reasonably well tuned.


Moreover, even imprecise tuning may substantially raise the voltage withstand capacity of a stacked-transistor RF switch. For example, when the Cpd capacitances of a stacked-transistor RF switch design are predominantly coupled to a first endnode of an RF switch, improvements in switch voltage withstand may be realized by progressively increasing the net effective Cds for transistors that are progressively farther from the first endnode. Such general, progressive increase may be achieved, for example, by modifying transistor designs, and/or by adding discrete compensating capacitances. Such a general, imprecise solution may be as described in regard to FIG. 6, with k=1.


General Case Circuits and Solutions


In practice, parasitic capacitances from internal nodes can couple to any number of places. In a standard CMOS IC they may couple to the substrate. In SOI or GaAs devices they may couple to the package or metal on the back of the part. In all types of devices, the parasitic capacitances can also couple to nearby metal lines. Constituent Cpd capacitances coupled to any node having a signal comprising X*VN1−Y*VN2 may limit the RF handling capability of large stacks to less than j×BVds.


Not only the effective Cpd of a drain node, but also the effective Cds and/or the effective Ccomp may be comprised of a plurality of distinct constituent capacitances. The constituents of an effective Cpd capacitance may well be coupled to a multiplicity of different circuit nodes, as may constituents of Ccomp. Cds are coupled between particular nodes, but may still comprise a plurality of constituent capacitances. Consequently, the general case is far more complicated than the special case described above.



FIG. 9 expands upon a portion of FIG. 4 to illustrate such greater complexity. FIG. 9 illustrates Mn 402 of FIG. 4, together with Cpd(n−1) 412, which is coupled to the source node Sn and to the corresponding terminal node Np(n−1) 414, and the two endnodes N1 202 and N2 204 of the RF switch. FIG. 9 illustrates an expansion of the effective Cpdn 408 of FIG. 4, or an expansion of an effective compensation capacitance Ccomp, or both. In the first case, CnA 902, CnB 904 and CnC 906, which are terminated at nodes 908, 910 and 912 respectively, represent constituent capacitances of Cpdn 408. Node 908 is the RF equivalent of the second end of the RF switch, N2 204, while Node 912 is the RF equivalent of the first end of the RF switch, N1 202. Finally, node 910 is the RF equivalent of a different drain, Dq. Cpdn 408 represents the parallel combination of such constituent capacitances, so the total capacitance of Cpdn 408 will be the sum of the three values of CnA, CnB and CnC, presuming there are no other significant Cpd constituents.


In this general case, the equivalent node Npn 410 of FIG. 4 may well not be an actual node. However, in any event, it is a mathematical equivalent node having an equivalent signal content based on the signal voltages of N2, N1, and on the relative magnitudes of CnA 902, CnB 904 and CnC 906. It may be useful to determine whether the effective signal on the equivalent node Npn 410 is closer to the signal on N2 or the signal on N1. The relevant signal components of the (net effective) Cpdn will most often cause the signal to fall somewhere between the ideal voltage of Dn and the voltage of N2, or else between the ideal voltage of Dn and the voltage of N1. In the former case, Dn is properly said to be more closely coupled to N2 than to N1, while in the latter case Dn is properly said to be more closely coupled to N1. With M1 coupled to N1 (as shown in FIG. 4), compensation of effective Cpdn that is more closely coupled to N1 requires an increase in capacitance between Dn and one or more nodes that are more closely coupled to N2. The converse is also true: compensation of effective Cpdn that is more closely coupled to N2 requires an increase in capacitance between Dn and one or more nodes that are more closely coupled to N1. For each drain node n, the effect of each constituent of Cpd may be calculated as described with respect to FIG. 6, and the effects of all such constituents combined to determine the effective Cpdn.


In an alternative view of FIG. 9, the capacitances CnA 902, CnB 904 and CnC 906, instead of exclusively representing constituents of a Cpd, represent constituents of both a Cpd and of a Ccomp. According to one example of this view, node 912 is N1, and capacitor CnC 906 comprises substantially all of Cpdn. Node 910 (Dq) is the next higher drain, D(n+1) (i.e., q=n+1), and consequently the CnB 904 represents an increase in effective drain-source capacitance Cds(n+1). CnB 904 may, for example, be a discrete capacitor, or it may reflect an increase in Cds resulting from design modification of M(n+1). Further, it may reflect a combination of both means. Node 908 is an RF equivalent to N2, so CnA 902 may be a small discrete capacitor coupled between Dn and N2. Capacitances 902 and 904 are constituents of Ccompn. Values of the capacitances 902, 904 and 906, together with any disparity between Cdsn and Cds(n+1) not encompassed by CnB 904, should be established to satisfy Eqn. 1, as described below. Of course, Ccomp may have any number of constituent capacitances; and, as described above for determining the effective Cpd, the effect of each Ccomp constituent may be individually determined and then combined as the effective Ccompn.


A general rule for tuning or compensation of a node m, which is the drain of a stacked transistor, is set forth below. Each capacitance Cim is disposed between the node m and a different node i. Node m (in operation, with the RF switch in high impedance or off state) will have a voltage Vm, and under the same conditions each other node i will have a voltage Vi. P is the total number of distinct capacitors tied to node m. Based on calculation of charge injection to the node m, then, balance (and thus uniform voltage distribution) may be achieved by establishing that:









0
=




i
=
0


P
-
1





(

Vi
-
Vm

)

×

Cim
.







(

Eqn
.




1

)







To the extent that Cds for the transistor immediately above node m and Cds for the transistor immediately below node m are equal, they may be ignored if the voltage is uniform on those two transistors, i.e., if [V(m+1)−V(m−1)]/2=Vm. However, if the Vds above and below node m are not going to be established to be equal in magnitude (and opposite in sign), then each Cds must be included in the calculation. Even if the Vds are equal, the Cds values should be included in the summation at least to the extent that they are significantly unequal.


Precision is helpful up to a point, but as noted above, precision is not always necessary to substantially improve voltage distribution imbalances across the transistors in a stacked RF switch. For some embodiments, it will suffice to observe that the Cpd are, on average, more closely coupled to N1 than to N2, and accordingly to establish values for Cds that are significantly increasing (e.g., increasing by more than 0.03%) for a majority of the FETs, rather than being substantially equal or varying randomly. Many embodiments of the devices and methods described herein achieve compensation for undesirable parasitic capacitances in a stacked FET RF switch by adding compensating capacitances coupled between nodes of transistors in the stack, particularly between drain nodes (or source nodes, which are equivalent). Such compensating capacitances may cause adjacent FETs in a stack to have significantly different net values of Cds, or may establish a compensating network of capacitance that is parallel to the series Cds string of the FET stack.


Adding Compensation Capacitance:


Cds is described as an effective drain-source capacitance, and herein means the total effective drain-source capacitance, net of intentional and unintentional capacitances and effects, unless a different meaning is made clear. Net effective Cds may be changed, for example, by simply coupling a predominantly capacitive feature between the drain and source nodes of a transistor in an RF switch stack. A predominantly capacitive feature is a passive element having an impedance at the frequency of a switched signal that is more capacitive than inductive or resistive. As circuit designers will understand, many structures may be fabricated that function as capacitors, and any such capacitor or predominantly capacitive feature or element may constitute a compensation capacitor or capacitance.


A compensation capacitance may include a difference between the intrinsic Cds of different constituent transistors of a stack, at least to the extent that such difference is an intentional result of specific design variations between such transistors. A particular constituent FET of a stack may have a different layout, or otherwise be designed or fabricated differently, from another constituent FET to achieve a desired difference in Cds values between such FETs. The manner in which Cds is achieved is not important to the devices and methods described herein; instead, any technique may be employed to establish satisfactory effective Cds values. Thus, any significant or intentional difference between the effective Cds of different transistors in a stack may fairly be considered to represent compensation capacitance.


When modifying individual transistor designs to vary their effective Cds is feasible, such modification may at least partly tune the capacitance of a transistor stack. Such modification may be very elegant. However, the required differences in design may be tedious to implement, and also may be relatively difficult to reestablish when a circuit must be modified for unrelated reasons. Nonetheless, such modification may provide some or even all of the compensation capacitance needed to satisfactorily tune the capacitances of a stacked transistor RF switch.


The simplest design modification for varying effective Cds is a simple change in device size. A larger device intrinsically has a larger value of Cds, so physically larger transistors may be used when larger Cds is required. Indeed, intrinsic Cds may well be substantially proportional to device size. In the special case in which Cpd capacitances are predominantly coupled to one endnode (the “bottom”) of the RF switch, the transistors at the top of the stack require more compensation capacitance. In that case, the higher n transistors may be made progressively larger, either in lieu of, or in addition to, adding discrete capacitance between nodes of the series string of the stack.


The general idea of varying transistor size to at least partially supplant a need for discrete compensation capacitors applies to the general case of tuning stacked transistor switches. However, the following analysis particularly applies to the special case of a stack as described above and represented by FIG. 4, with the assumption made above for FIGS. 5 and 6 that each Cpd is coupled to a node equivalent to the lowest endnode (N1, to which M1 is coupled) of the RF switch. The width Wn of each transistor Mn, n>1, may be determined as follows for the special case, with W1 selected to establish overall switch resistance to satisfy performance requirements:










W
n

=


W
1






i
=
1


j
-
1






Cds
i

+

i
×

Cpd
i




Cds
i








(

Eqn
.




2

)








Because Cds is generally a linear function with transistor width, while Cpd will typically be non-linear, eqn. 2 cannot readily be further simplified, nor made precise. Ideally, a stack tuned in accordance with Eqn. 2 will also satisfy the requirements of Eqn. 1, as set forth above.


Capacitances fabricated using gate insulation may be employed for tuning, though they may, for example, have a relatively low breakdown voltage, or be nonlinear. Moreover, because parasitic capacitance is often proportional to layout area, adding such compensating capacitors to the side of a transistor may create further parasitic capacitance. This may make tuning an iterative process, because the solution to the problem changes with each addition of compensation.


Metal-Metal (MIM) capacitance disposed on top of the switch transistor itself may be the best solution in some cases. Thus located, MIM capacitors may not require extra die area, and typically add no extra parasitic capacitance to ground, at least. Moreover, establishing a desired capacitance with a MIM capacitor is relatively simple, and consequently is likely to be easier to revise for subsequent design iterations, as compared to solutions based on modifying the transistor design. MIM capacitors may also have higher breakdown voltages, and thus may be amenable to being coupled between nodes m and i that are separated by a plurality of transistors (i.e., k>1 with respect to FIG. 6).


Identifying and Quantifying Effective Tuning


A voltage Vsw applied to an RF switch comprised of j constituent stacked transistors is distributed across the constituent transistors of the stack. Deviation from uniformity in the distribution may be quantified as the variance V of the portion of Vsw appearing on each transistor, where Vdsi for each transistor Mi resulting from Vsw is Vi, and







V
2

=


(




i
=
1

j




(

Vi
-

Vsw
/
j


)

2


)

/

j
.






Useful tuning of a stacked transistor RF switch will result in a smaller variance V for the distributed voltages across the constituent transistors of the stack. Random process variation will inevitably cause small differences between the Cds of different transistors in a stack. However, because a design with no variation will be as perfect as possible, such random variations should generally act to increase the variance of the distributed transistor voltages. Accordingly, intentional tuning through control of Cds, on the one hand, and random, unintentional variations in the values of Cds on the other hand, may be distinguished by a showing of whether reducing the variation in Cds in a device or method (making the Cds of constituent transistors more uniform) would decrease or increase the variance in voltage distribution across the stack. The variance will increase as a result of reducing the Cds variations that serve to effectively tune a stacked switch.


Variance in voltage distribution across constituent transistors can similarly distinguish distribution tuning capacitance that is coupled to an internal node of the series string of a stacked-transistor switch. Upon omission of the predominantly capacitive elements coupled to internal nodes of the switch in an RF switch embodiment as described herein, the variance of the voltage distribution will increase if they are distribution tuning capacitances. Conversely, if capacitance has been coupled to internal string nodes for purposes other than tuning to increase voltage withstand capacity, then removing such capacitance will decrease the variance of voltage distribution.


Random process variation in Cds values can be distinguished from variations implemented intentionally to increase voltage withstand tuning by the magnitude of the maximum Cds variations. Thus, for the constituent transistors of a stack on a particular device, the largest Cds will be very close to the smallest Cds if the deviation is merely due to random process variations. For tuning a stack of j transistors, a size comparison (Cds(max)/Cds(min)−1) may be required to be at least j/200, or at least j/100, or at least j/50. Irrespective of j, a tuned stack of transistors may be required to have a Cds(max) that exceeds Cds(min) by at least 2%, at least 5%, or at least 10%, or at least 20%. Any of these limitations may be explicitly added to any claim of method, process or apparatus in order to distinguish incidental designs that are not intended to be encompassed by such claim.


Differences in net effective Cds values between adjacent pairs of transistors in a series stack may be required to be at least 0.5% for each of a majority of such adjacent pairs. Alternatively, differences in such net effective Cds values between adjacent pairs of transistors may be compared to a total Cpd (not including Cds constituents) for the internal node of the string that is between the transistors of such pair. The Cds differences may then be required to exceed the total Cpd for the node between them, for at least half, or for a majority, of such adjacent pairs. The calculation may also be made by averaging, such that a sum of Cds differences between all adjacent transistor pairs is required to exceed a sum of the total Cpd for the node(s) between such pairs.


Determining Cpd Values


The integrated circuit designer is often faced with a need to evaluate circuit parasitic elements, and any such technique may be employed to establish the parasitic drain capacitances Cpd to nodes other than the corresponding source, as well as the parasitic drain-source capacitance Cds. Complete circuit simulation based on the detailed parameters of the selected fabrication process and layout is ideal, if the simulation program is accurate and sufficient processing power is available to complete the task in a reasonable length of time. It is also possible to build a circuit, probe (measure) the distribution of the RF switch voltage across the individual transistors of the stack, and to deduce the effective Cpd values from such measurements. However, as noted above, a substantial improvement in RF switch voltage withstand capacity may be achieved even without perfect compensation. Accordingly, less demanding techniques may be employed to estimate Cpd values.


One example of such a technique to estimate parasitic capacitance from a node to substrate is as follows:










C
=

L





ɛ


{


w
h

+


0
.
7


7

+


1
.
0


6
×

[



(

w
h

)

0.25

+


(

t
h

)

0.5


]



}



,




(

Eqn
.




3

)








where w and L are the width and length of the node, t is the thickness of the node, h is the height of the node above the ground plane, ε=εo×8.854e-12F/m, and εo is the relative permittivity of the substrate material.


Numerous computer programs exist to aid the designer in estimating parasitic circuit elements. Programs such as Medici, ADS/Momentum, FastCap, HFSS, and others are capable of 2D and 3D parasitic capacitance estimation. These tools enable more accurate estimation of capacitance to all other nodes in the vicinity of the node(s) being analyzed.


Conclusion


The foregoing description illustrates exemplary implementations, and novel features, of related methods of tuning or compensating the capacitances of stacked-transistor RF switches to alleviate low breakdown voltages for such switch that would otherwise result from imbalances in the distribution of the overall RF switch voltage across the transistors of the stack. It also describes implementations and novel features of integrated circuit stacked-transistor RF switches, apparatus that employ capacitive tuning or compensation features to improve net breakdown voltage compared to the absence of such features. The skilled person will understand that various omissions, substitutions, and changes in the form and details of the methods and apparatus illustrated may be made without departing from the scope of the invention. Because it is impractical to list all embodiments explicitly, it should be understood that each practical combination of the features set forth above (or conveyed by the figures) as suitable for embodiments of the apparatus or methods constitutes a distinct alternative embodiment of an apparatus or method. Moreover, each practical combination of equivalents of such apparatus or method alternatives also constitutes a distinct alternative embodiment of the subject apparatus or methods. Therefore, the scope of the presented invention should be determined only by reference to the appended claims, as they may be amended during pendency of the application, and is not to be limited by features illustrated in the foregoing description except insofar as such limitation is recited, or intentionally implicated, in an appended claim.


The transistors in stacked-transistor RF switches as described herein are preferably of an insulated-gate type, or are biased so as to conduct no DC gate current. Even more preferably, the transistors are FETs, particularly those referred to as MOSFETs, though that includes many FETs that are not fabricated with traditional Metal/Oxide/Semiconductor layers, as was once implied by the name. The FETs have been described as if they are of N polarity (NMOS), but they could equally well be PMOS. Embodiments may employ non-preferred transistors, though they may require circuit adjustments to deal with control-node DC current.


The circuits illustrated and described herein are only exemplary, and should be interpreted as equally describing such alternatives as may be readily seen to be analogous by a person of skill in the art, whether by present knowledge common to such skilled persons, or in the future in view of unforeseen but readily-applied alternatives then known to such skilled persons.


All variations coming within the meaning and range of equivalency of the various claim elements are embraced within the scope of the corresponding claim. Each claim set forth below is intended to encompass any system or method that differs only insubstantially from the literal language of such claim, but only if such system or method is not an embodiment of the prior art. To this end, each element described in each claim should be construed as broadly as possible, and should be understood to encompass any equivalent to such element insofar as possible without also encompassing the prior art.

Claims
  • 1. A voltage distribution-balanced stack of series coupled transistors, comprising: a stack of series coupled transistors;a plurality of internal nodes between pairs of adjacent transistors of the stack of series coupled transistors;at least one compensation capacitor coupled across at least one node of the plurality of internal nodes and ground to voltage balance the stack of series coupled transistors;a plurality of gate resistive impedances of the stack of series coupled transistors; anda plurality of gate capacitive impedances of the stack of series coupled transistors, wherein at least one gate resistive impedance of the plurality of gate resistive impedances and at least one gate capacitive impedance of the plurality of gate capacitive impedances combine to form a low pass filter.
  • 2. A voltage distribution-balanced stack of series coupled transistors, comprising: a stack of series coupled transistors, wherein a first transistor of the series coupled stacked transistors has a first intrinsic drain-source capacitance Cds;internal nodes between adjacent transistors of the stack of series coupled transistors, at least one internal node of the internal nodes having a capacitance Cpd between the at least one internal node and a coupled node, wherein a ratio of the capacitance Cpd to the first intrinsic drain-source capacitance Cds is set at less than a predetermined value.
  • 3. The voltage-distribution balanced stack of claim 2, wherein the capacitance Cpd is coupled to ground.
  • 4. The voltage-distribution balanced stack of claim 2, further comprising at least one compensation capacitor coupled across at least two internal nodes of the plurality of internal nodes to voltage balance the stack of series coupled transistors.
  • 5. The voltage distribution-balanced stack of claim 4, wherein the at least one compensation capacitor is coupled to ground.
  • 6. The voltage-distribution balanced stack of claim 2, wherein a second transistor of the series of coupled stacked transistors has a second intrinsic drain-source capacitance Cds, wherein a difference between the first intrinsic drain-source capacitance Cds and the second intrinsic drain-source capacitance Cds is set at a predetermined amount.
  • 7. The voltage distribution-balanced stack of claim 6, wherein the first transistor has a first transistor size and the second transistor has a second transistor size different from the first transistor size.
  • 8. The voltage distribution-balanced stack of claim 7, wherein the first transistor size is smaller than the second transistor size.
  • 9. The voltage distribution-balanced stack of claim 6, wherein the first intrinsic drain-source capacitance Cds is lower than the second intrinsic drain-source capacitance Cds.
CROSS-REFERENCE TO RELATED APPLICATIONS—CLAIMS OF PRIORITY

This application is a continuation application of co-pending and commonly assigned U.S. application Ser. No. 15/829,773, “Tuning Capacitance to Enhance FET Stack Voltage Withstand”, filed Dec. 1, 2017; application Ser. No. 15/829,773 is a continuation application of commonly assigned U.S. application Ser. No. 15/061,909, “Tuning Capacitance to Enhance FET Stack Voltage Withstand”, filed Mar. 4, 2016, now U.S. Pat. No. 9,866,212, issued Jan. 9, 2018; application Ser. No. 15/061,909 is a continuation application of commonly assigned U.S. application Ser. No. 14/883,122, “Tuning Capacitance to Enhance FET Stack Voltage Withstand”, filed Oct. 14, 2015, now U.S. Pat. No. 9,595,956 issued Mar. 14, 2017; application Ser. No. 14/883,122 is a continuation application of commonly assigned U.S. application Ser. No. 14/028,357, “Tuning Capacitance to Enhance FET Stack Voltage Withstand”, filed Sep. 16, 2013, now U.S. Pat. No. 9,177,737 issued Nov. 3, 2015, which is a continuation application of commonly assigned U.S. application Ser. No. 13/046,560, “Tuning Capacitance to Enhance FET Stack Voltage Withstand”, filed Mar. 11, 2011, Issued as U.S. Pat. No. 8,536,636 on Sep. 17, 2013, which is a divisional application of issued and commonly owned U.S. application Ser. No. 11/796,522, filed Apr. 26, 2007, issued Jun. 14, 2011 as U.S. Pat. No. 7,960,772 and entitled “Tuning Capacitance to Enhance FET Stack Voltage Withstand”, and the contents of the above cited pending application and issued patents are hereby incorporated by reference herein in their entirety.

US Referenced Citations (420)
Number Name Date Kind
3470443 Berry et al. Sep 1969 A
3646361 Pfiffner Feb 1972 A
3699359 Shelby Oct 1972 A
3731112 Smith May 1973 A
3878450 Greatbatch Apr 1975 A
3942047 Buchanan Mar 1976 A
3943428 Whidden Mar 1976 A
3955353 Astle May 1976 A
3975671 Stoll Aug 1976 A
3988727 Scott Oct 1976 A
4047091 Hutchines et al. Sep 1977 A
4061929 Asano Dec 1977 A
4068295 Portmann Jan 1978 A
4079336 Gross Mar 1978 A
4106086 Holbrook et al. Aug 1978 A
4186436 Ishiwatari Jan 1980 A
4241316 Knapp Dec 1980 A
4244000 Ueda et al. Jan 1981 A
4256977 Hendrickson Mar 1981 A
4306203 Sasaki et al. Dec 1981 A
4316101 Minner Feb 1982 A
4317055 Yoshida et al. Feb 1982 A
4321661 Sano Mar 1982 A
4367421 Baker Jan 1983 A
4390798 Kurafuji Jun 1983 A
4460952 Risinger Jul 1984 A
RE31749 Yamashiro Nov 1984 E
4485433 Topich Nov 1984 A
4564843 Cooper Jan 1986 A
4621315 Vaughn et al. Nov 1986 A
4633106 Backes et al. Dec 1986 A
4638184 Kimura Jan 1987 A
4679134 Bingham Jul 1987 A
4701732 Nestlerode Oct 1987 A
4703196 Arakawa Oct 1987 A
4736169 Weaver et al. Apr 1988 A
4739191 Puar Apr 1988 A
4746960 Valeri et al. May 1988 A
4752699 Cranford et al. Jun 1988 A
4769784 Doluca et al. Sep 1988 A
4777577 Bingham et al. Oct 1988 A
4810911 Noguchi Mar 1989 A
4825145 Tanaka et al. Apr 1989 A
4839787 Kojima et al. Jun 1989 A
4847519 Wahl et al. Jul 1989 A
4849651 Estes, Jr. Jul 1989 A
4890077 Sun Dec 1989 A
4891609 Eilley Jan 1990 A
4893070 Milberger et al. Jan 1990 A
4897774 Bingham et al. Jan 1990 A
4924238 Ploussios May 1990 A
4929855 Ezzeddine May 1990 A
4939485 Eisenberg Jul 1990 A
4984040 Yap Jan 1991 A
4985647 Kawada Jan 1991 A
4999585 Burt et al. Mar 1991 A
5012123 Ayasli et al. Apr 1991 A
5023494 Tsukii et al. Jun 1991 A
5029282 Ito Jul 1991 A
5032799 Milberger et al. Jul 1991 A
5038325 Douglas et al. Aug 1991 A
5041797 Belcher et al. Aug 1991 A
5061907 Rasmussen Oct 1991 A
5061911 Weidman et al. Oct 1991 A
5068626 Takagi et al. Nov 1991 A
5081371 Wong Jan 1992 A
5081706 Kim Jan 1992 A
5111375 Marshall Mar 1992 A
5124762 Childs et al. Jun 1992 A
5126590 Chern Jun 1992 A
5138190 Yamazaki et al. Aug 1992 A
5146178 Nojima et al. Sep 1992 A
5182529 Chern Jan 1993 A
5193198 Yokouchi Mar 1993 A
5208557 Kersh, III May 1993 A
5212456 Kovalcik et al. May 1993 A
5272457 Heckaman et al. Dec 1993 A
5274343 Russell et al. Dec 1993 A
5285367 Keller Feb 1994 A
5306954 Chan et al. Apr 1994 A
5313083 Schindler May 1994 A
5317181 Tyson May 1994 A
5332997 Dingwall et al. Jul 1994 A
5345422 Redwine Sep 1994 A
5350957 Cooper et al. Sep 1994 A
5375256 Yokoyama et al. Dec 1994 A
5375257 Lampen Dec 1994 A
5392186 Alexander et al. Feb 1995 A
5392205 Zavaleta Feb 1995 A
5416043 Burgener et al. May 1995 A
5422586 Tedrow et al. Jun 1995 A
5442327 Longbrake et al. Aug 1995 A
5446418 Hara et al. Aug 1995 A
5448207 Kohama Sep 1995 A
5455794 Javanifard et al. Oct 1995 A
5465061 Dufour Nov 1995 A
5477184 Uda et al. Dec 1995 A
5488243 Tsuruta et al. Jan 1996 A
5492857 Reedy et al. Feb 1996 A
5493249 Manning Feb 1996 A
5519360 Keeth May 1996 A
5535160 Yamaguchi Jul 1996 A
5548239 Kohama Aug 1996 A
5553021 Kubono et al. Sep 1996 A
5553295 Pantelakis et al. Sep 1996 A
5554892 Norimatsu Sep 1996 A
5572040 Reedy et al. Nov 1996 A
5576647 Sutardja Nov 1996 A
5589793 Kassapian Dec 1996 A
5596205 Reedy et al. Jan 1997 A
5597739 Sumi et al. Jan 1997 A
5600169 Burgener et al. Feb 1997 A
5629655 Dent May 1997 A
5663570 Reedy et al. Sep 1997 A
5670907 Gorecki et al. Sep 1997 A
5672992 Nadd Sep 1997 A
5677649 Martin Oct 1997 A
5681761 Kim Oct 1997 A
5694308 Cave Dec 1997 A
5698877 Gonzalez Dec 1997 A
5699018 Yamamoto et al. Dec 1997 A
5717356 Kohama Feb 1998 A
5729039 Beyer et al. Mar 1998 A
5731607 Kohama Mar 1998 A
5734291 Tasdighi et al. Mar 1998 A
5748053 Kameyama et al. May 1998 A
5757170 Pinney May 1998 A
5760652 Yamamoto et al. Jun 1998 A
5774792 Tanaka et al. Jun 1998 A
5784687 Itoh et al. Jun 1998 A
5777530 Nakatuka Jul 1998 A
5786617 Merrill et al. Jul 1998 A
5793246 Costello et al. Aug 1998 A
5801577 Tailliet Sep 1998 A
5807772 Takemura Sep 1998 A
5808505 Tsukada Sep 1998 A
5812066 Terk et al. Sep 1998 A
5812939 Kohama Sep 1998 A
5818099 Burghartz Oct 1998 A
5818278 Yamamoto et al. Oct 1998 A
5818283 Tonami et al. Oct 1998 A
5818289 Chevallier et al. Oct 1998 A
5818766 Song Oct 1998 A
5821800 Le et al. Oct 1998 A
5825227 Kohama et al. Oct 1998 A
5861336 Reedy et al. Jan 1999 A
5863823 Burgener Jan 1999 A
5864328 Kajimoto Jan 1999 A
5872489 Chang et al. Feb 1999 A
5874836 Nowak et al. Feb 1999 A
5874849 Marotta et al. Feb 1999 A
5878331 Yamamoto et al. Mar 1999 A
5880921 Tham et al. Mar 1999 A
5883396 Reedy et al. Mar 1999 A
5883541 Tahara et al. Mar 1999 A
5889428 Young Mar 1999 A
5892400 van Saders et al. Apr 1999 A
5895957 Reedy et al. Apr 1999 A
5903178 Miyatsuji et al. May 1999 A
5912560 Pastemak Jun 1999 A
5917362 Kohama Jun 1999 A
5920233 Denny Jul 1999 A
5926466 Ishida et al. Jul 1999 A
5930638 Reedy et al. Jul 1999 A
5945867 Uda et al. Aug 1999 A
5959335 Bryant et al. Sep 1999 A
5969560 Kohama et al. Oct 1999 A
5973363 Staab et al. Oct 1999 A
5973382 Burgener et al. Oct 1999 A
5973636 Okubo et al. Oct 1999 A
5986518 Dougherty Nov 1999 A
5990580 Weigand Nov 1999 A
6020781 Fujioka Feb 2000 A
6057555 Reedy et al. May 2000 A
6057723 Yamaji et al. May 2000 A
6064275 Yamauchi May 2000 A
6064872 Vice May 2000 A
6066993 Yamamoto et al. May 2000 A
6081165 Goldman Jun 2000 A
6081694 Matsuura et al. Jun 2000 A
6094088 Yano Jul 2000 A
6107885 Miguelez et al. Aug 2000 A
6114923 Mizutani Sep 2000 A
6118343 Winslow Sep 2000 A
6122185 Utsunomiya et al. Sep 2000 A
6130572 Ghilardelli et al. Oct 2000 A
6133752 Kawagoe Oct 2000 A
6163238 Nesterode Dec 2000 A
6169444 Thurber, Jr. Jan 2001 B1
6177826 Mashiko et al. Jan 2001 B1
6188247 Storino et al. Feb 2001 B1
6188590 Chang et al. Feb 2001 B1
6191653 Camp, Jr. et al. Feb 2001 B1
6195307 Umezawa et al. Feb 2001 B1
RE37124 Monk et al. Apr 2001 E
6215360 Callaway, Jr. Apr 2001 B1
6218890 Yamaguchi et al. Apr 2001 B1
6225866 Kubota et al. May 2001 B1
6239657 Bauer May 2001 B1
6249446 Shearon et al. Jun 2001 B1
6265925 Wong Jul 2001 B1
6288458 Berndt Sep 2001 B1
6297687 Sugimura Oct 2001 B1
6297696 Abdollahian et al. Oct 2001 B1
6300796 Troutman et al. Oct 2001 B1
6308047 Yamamoto et al. Oct 2001 B1
6310508 Westerman Oct 2001 B1
6316983 Kitamura Nov 2001 B1
6337594 Hwang Jan 2002 B1
6356135 Rastegar Mar 2002 B1
6356536 Repke Mar 2002 B1
6365488 Liao Apr 2002 B1
6380793 Bancal et al. Apr 2002 B1
6380796 Sakai et al. Apr 2002 B2
6380802 Pehike et al. Apr 2002 B1
6392440 Nebel May 2002 B2
6396352 Muza May 2002 B1
6400211 Yokomizo et al. Jun 2002 B1
6407614 Takahashi Jun 2002 B1
6411531 Nork et al. Jun 2002 B1
6414863 Bayer et al. Jul 2002 B1
6429632 Forbes et al. Aug 2002 B1
6429723 Hastings Aug 2002 B1
6449465 Gallus et al. Sep 2002 B1
6452232 Adan Sep 2002 B1
6461902 Xu et al. Oct 2002 B1
6486511 Nathanson et al. Nov 2002 B1
6486729 Imamiya Nov 2002 B2
6496074 Sowlati Dec 2002 B1
6504213 Ebina Jan 2003 B1
6509799 Franca-Neto Jan 2003 B1
6512269 Bryant et al. Jan 2003 B1
6518829 Butler Feb 2003 B2
6537861 Kroell et al. Mar 2003 B1
6559689 Clark May 2003 B1
6563366 Kohama May 2003 B1
6611164 Uno Aug 2003 B2
6617933 Ito et al. Sep 2003 B2
6642578 Arnold et al. Nov 2003 B1
6653697 Hidaka et al. Nov 2003 B2
6677641 Kocon Jan 2004 B2
6683499 Lautzenhiser et al. Jan 2004 B2
6684065 Bult Jan 2004 B2
6693498 Sasabata et al. Feb 2004 B1
6698082 Crenshaw et al. Mar 2004 B2
6698498 Crenshaw et al. Mar 2004 B1
6704550 Kohama et al. Mar 2004 B1
6711397 Petrov et al. Mar 2004 B1
6714065 Komiya et al. Mar 2004 B2
6717458 Potanin Apr 2004 B1
6747522 Peitruszynski et al. Jun 2004 B2
6753738 Baird Jun 2004 B1
6774701 Heston et al. Aug 2004 B1
6781805 Urakawa Aug 2004 B1
6788130 Pauletti et al. Sep 2004 B2
6801076 Merritt Oct 2004 B1
6803680 Brindle et al. Oct 2004 B2
6804502 Burgener et al. Oct 2004 B2
6816000 Miyamitsu Nov 2004 B2
6816001 Khouri et al. Nov 2004 B2
6816016 Sander et al. Nov 2004 B2
6819938 Sahota Nov 2004 B2
6825730 Sun Nov 2004 B1
6831847 Perry Dec 2004 B2
6833745 Hausman et al. Dec 2004 B2
6836172 Okashita Dec 2004 B2
6870404 Maangat Mar 2005 B1
6871059 Piro et al. Mar 2005 B1
6879502 Yoshida et al. Apr 2005 B2
6882210 Asano et al. Apr 2005 B2
6889036 Ballweber et al. May 2005 B2
6891234 Connelly et al. May 2005 B1
6903596 Geller et al. Jun 2005 B2
6906653 Uno Jun 2005 B2
6917258 Kushitani et al. Jul 2005 B2
6927722 Hong Aug 2005 B2
6934520 Rozsypal Aug 2005 B2
6947720 Razavi et al. Sep 2005 B2
6968167 Wu Nov 2005 B1
6975271 Adachi et al. Dec 2005 B2
6978122 Kawakyu et al. Dec 2005 B2
6992543 Luetzelschwab et al. Jan 2006 B2
7023260 Thorp et al. Apr 2006 B2
7042245 Hidaka May 2006 B2
7057472 Fukamachi et al. Jun 2006 B2
7082293 Rofougaran et al. Jul 2006 B1
7088971 Burgener et al. Aug 2006 B2
7092677 Zhang et al. Aug 2006 B1
7109532 Lee et al. Sep 2006 B1
7123898 Burgener et al. Oct 2006 B2
7129545 Cain Oct 2006 B2
7132873 Hollmer Nov 2006 B2
7138846 Suwa et al. Nov 2006 B2
7161197 Nakatsuka et al. Jan 2007 B2
7173471 Nakatsuka et al. Feb 2007 B2
7190933 De Ruijter Mar 2007 B2
7199635 Nakatsuka et al. Apr 2007 B2
7212788 Weber et al. May 2007 B2
7248120 Burgener et al. Jul 2007 B2
7269392 Nakajima et al. Sep 2007 B2
7299018 Van Rumpt Nov 2007 B2
7307490 Kizuki Dec 2007 B2
7310215 Pasternak Dec 2007 B2
7345342 Challa Mar 2008 B2
7345521 Takahashi et al. Mar 2008 B2
7355455 Hidaka Apr 2008 B2
7391282 Nakatsuka et al. Jun 2008 B2
7432552 Park Oct 2008 B2
7460852 Burgener et al. Dec 2008 B2
7463085 Kim et al. Dec 2008 B2
7515882 Kelcourse et al. Apr 2009 B2
7546089 Bellantoni Jun 2009 B2
7551036 Berroth et al. Jun 2009 B2
7561853 Miyazawa Jul 2009 B2
7659152 Gonzalez et al. Feb 2010 B2
7714676 McKinzie May 2010 B2
7719343 Burgener et al. May 2010 B2
7733156 Brederlow et al. Jun 2010 B2
7733157 Brederlow et al. Jun 2010 B2
7741869 Hidaka Jun 2010 B2
7764140 Nagarkatti et al. Jul 2010 B2
7772648 Ivanov et al. Aug 2010 B1
7796969 Kelly et al. Sep 2010 B2
7825715 Greenberg Nov 2010 B1
7847642 Pretl Dec 2010 B2
7860499 Burgener et al. Dec 2010 B2
7910993 Brindle et al. Mar 2011 B2
7928759 Hidaka Apr 2011 B2
7960772 Englekirk Jun 2011 B2
7982265 Challa et al. Jul 2011 B2
8138816 Freeston et al. Mar 2012 B2
8536636 Englekirk Sep 2013 B2
8583065 Ben-Bassat Nov 2013 B2
8583111 Burgener et al. Nov 2013 B2
8604864 Ranta et al. Dec 2013 B2
8638159 Ranta et al. Jan 2014 B2
8669804 Ranta et al. Mar 2014 B2
8803631 Manssen et al. Aug 2014 B2
8847666 Chih-Sheng Sep 2014 B2
9024700 Ranta May 2015 B2
9087899 Brindle et al. Jul 2015 B2
9106227 Ranta et al. Aug 2015 B2
9177737 Englekirk Nov 2015 B2
9197194 Reedy et al. Nov 2015 B2
9225378 Burgener et al. Dec 2015 B2
9293262 Bawell et al. Mar 2016 B2
9496849 Ranta et al. Nov 2016 B2
9595956 Englekirk Mar 2017 B2
9667227 Ranta May 2017 B2
9806694 Reedy et al. Oct 2017 B2
9866212 Englekirk Jan 2018 B2
10050616 Ranta et al. Aug 2018 B2
10158345 Reedy et al. Dec 2018 B2
10382031 Ranta Aug 2019 B2
10622992 Englekirk Apr 2020 B2
20010031518 Kim et al. Oct 2001 A1
20010040479 Zhang Nov 2001 A1
20020115244 Park et al. Aug 2002 A1
20020126767 Ding et al. Sep 2002 A1
20030002452 Sahota Jan 2003 A1
20030032396 Tsuchiya et al. Feb 2003 A1
20030141543 Bryant et al. Jul 2003 A1
20030160515 Yu et al. Aug 2003 A1
20030181167 Iida Sep 2003 A1
20030201494 Maeda et al. Oct 2003 A1
20030224743 Okada et al. Dec 2003 A1
20040061130 Morizuka Apr 2004 A1
20040080364 Sander et al. Apr 2004 A1
20040121745 Meck Jun 2004 A1
20040129975 Koh et al. Jul 2004 A1
20040204013 Ma et al. Oct 2004 A1
20040242182 Hikada et al. Dec 2004 A1
20050017789 Burgener et al. Jan 2005 A1
20050068103 Dupuis et al. Mar 2005 A1
20050077564 Forbes Apr 2005 A1
20050079829 Ogawa et al. Apr 2005 A1
20050121699 Chen et al. Jun 2005 A1
20050212595 Kusunoki et al. Sep 2005 A1
20050264341 Hikita et al. Dec 2005 A1
20050285684 Burgener et al. Dec 2005 A1
20050287976 Burgener et al. Dec 2005 A1
20060009164 Kataoka Jan 2006 A1
20060077082 Shanks et al. Apr 2006 A1
20060160520 Naoyuki Jul 2006 A1
20060194558 Kelly Aug 2006 A1
20060194567 Kelly et al. Aug 2006 A1
20060255852 O'Donnell Nov 2006 A1
20060270367 Burgener et al. Nov 2006 A1
20070018247 Brindle et al. Jan 2007 A1
20070045697 Cheng et al. Mar 2007 A1
20070076454 Burstein et al. Apr 2007 A1
20070279120 Brederlow et al. Dec 2007 A1
20070290744 Adachi et al. Dec 2007 A1
20080076371 Dribinsky et al. Mar 2008 A1
20080265978 Englekirk Oct 2008 A1
20090039970 Shen et al. Feb 2009 A1
20090134949 He May 2009 A1
20090224843 Radoias et al. Sep 2009 A1
20100219997 Le Guillou Sep 2010 A1
20110001542 Ranta Jan 2011 A1
20110001544 Ranta Jan 2011 A1
20110002080 Ranta Jan 2011 A1
20110043271 Ranta Feb 2011 A1
20110163779 Hidaka Jul 2011 A1
20110165759 Englekirk Jul 2011 A1
20110227666 Manssen Sep 2011 A1
20110316636 Zhao Dec 2011 A1
20130208396 Bawell et al. Aug 2013 A1
20130222075 Reedy et al. Aug 2013 A1
20140165385 Englekirk Jun 2014 A1
20140179374 Burgener et al. Jun 2014 A1
20160191019 Reedy et al. Jun 2016 A1
20160191050 Englekirk Jun 2016 A1
20170026035 Englekirk Jan 2017 A1
20180097509 Reedy et al. Apr 2018 A1
20180159530 Englekirk Jun 2018 A1
20190007042 Ranta et al. Jan 2019 A1
20190123735 Reedy et al. Apr 2019 A1
20200014382 Ranta Jan 2020 A1
20200295750 Ranta et al. Sep 2020 A1
Foreign Referenced Citations (107)
Number Date Country
19832565 Aug 1999 DE
385641 Sep 1990 EP
0622901 Nov 1994 EP
782267 Jul 1997 EP
913939 May 1999 EP
625831 Nov 1999 EP
1451890 Feb 2011 EP
2387094 Nov 2011 EP
2255443 Nov 2012 EP
2568608 Mar 2013 EP
2568608 May 2014 EP
2760136 Jul 2014 EP
2140494 Jun 2017 EP
2760136 May 2018 EP
3346611 Jul 2018 EP
2425401 Oct 2006 GB
55-75348 Jun 1980 JP
1254014 Oct 1989 JP
2161769 Jun 1990 JP
04-34980 Feb 1992 JP
4183008 Jun 1992 JP
5299995 Nov 1993 JP
6112795 Apr 1994 JP
06-314985 Nov 1994 JP
6334506 Dec 1994 JP
7046109 Feb 1995 JP
7-70245 Mar 1995 JP
07106937 Apr 1995 JP
8023270 Jan 1996 JP
8070245 Mar 1996 JP
8148949 Jun 1996 JP
11163704 Jun 1996 JP
08-307305 Nov 1996 JP
8330930 Dec 1996 JP
09-008621 Jan 1997 JP
9008627 Jan 1997 JP
9041275 Feb 1997 JP
9055682 Feb 1997 JP
9092785 Apr 1997 JP
9148587 Jun 1997 JP
09163721 Jun 1997 JP
9163721 Jun 1997 JP
9181641 Jul 1997 JP
9186501 Jul 1997 JP
09200021 Jul 1997 JP
9200074 Jul 1997 JP
9238059 Sep 1997 JP
9243738 Sep 1997 JP
9270659 Oct 1997 JP
9284114 Oct 1997 JP
9284170 Oct 1997 JP
9298493 Oct 1997 JP
9326642 Dec 1997 JP
10079467 Mar 1998 JP
10-93471 Apr 1998 JP
10-242477 Sep 1998 JP
10-242829 Sep 1998 JP
10242826 Sep 1998 JP
10-344247 Dec 1998 JP
10335901 Dec 1998 JP
11026776 Jan 1999 JP
11112316 Apr 1999 JP
11-13611 May 1999 JP
11163642 Jun 1999 JP
11205188 Jul 1999 JP
11274804 Oct 1999 JP
2000031167 Jan 2000 JP
2000183353 Jun 2000 JP
2000188501 Jul 2000 JP
2000208614 Jul 2000 JP
2000223713 Aug 2000 JP
2000243973 Sep 2000 JP
2000277703 Oct 2000 JP
2000294786 Oct 2000 JP
2000311986 Nov 2000 JP
2001089448 Mar 2001 JP
2001-119281 Apr 2001 JP
2001157487 May 2001 JP
2001156182 Jun 2001 JP
2001274265 Oct 2001 JP
2004515937 May 2002 JP
20002164441 Jun 2002 JP
2003060451 Feb 2003 JP
2003167615 Jun 2003 JP
2003-198248 Jul 2003 JP
2003189248 Jul 2003 JP
2002156602 Dec 2003 JP
2004-147175 May 2004 JP
2004166470 Jun 2004 JP
2004199950 Jul 2004 JP
2005-203643 Jul 2005 JP
2006332778 Dec 2006 JP
5185369 Jan 2013 JP
5417346 Nov 2013 JP
5591356 Aug 2014 JP
5860857 Dec 2015 JP
1994027615 Dec 1994 KR
WO9523460 Aug 1995 WO
WO9806174 Feb 1998 WO
WO9935695 Jul 1999 WO
WO0227920 Apr 2002 WO
2006038190 Apr 2006 WO
2007008044 Jan 2007 WO
WO2007033045 Mar 2007 WO
2007060210 May 2007 WO
WO2008133621 Jun 2008 WO
WO2009108391 Sep 2009 WO
Non-Patent Literature Citations (515)
Entry
Patel, Reema, Office Action received from the USPTO dated Mar. 14, 2017 for U.S. Appl. No. 15/061,909, 7 pgs.
Patel, Reema, Office Action received from the USPTO dated Jul. 3, 2017 for U.S. Appl. No. 15/061,909, 39 pgs.
Patel, Reema, Notice of Allowance received from the USPTO dated Sep. 20, 2017 for U.S. Appl. No. 15/061,909, 17 pgs.
Englekirk, Robert Mark, Response filed in the USPTO dated Mar. 24, 2017 for U.S. Appl. No. 15/061,909, 3 pgs.
Englekirk, Robert Mark, Response filed in the USPTO dated Aug. 7, 2017 for U.S. Appl. No. 15/061,909, 11 pgs.
Ranta, et al., Response filed in the USPTO dated Jan. 23, 2018 for U.S. Appl. No. 15/442,491, 8 pgs.
Puentes, Daniel Calrissian, Final Office Action received from the USPTO dated Feb. 8, 2018 for U.S. Appl. No. 15/442,491, 22 pgs.
Willoughby, Terrence Ronique, Office Action received from the USPTO dated Apr. 6, 2018 U.S. Appl. No. 15/688,658, 24 pgs.
Brosa, Anna-Maria, Extended Search Report received from the EPO dated Apr. 18, 2018 for appln. No. 18157696.8, 14 pgs.
Kelly, et al., “The State-of-the-Art of Silicon-on-Sapphire CMOS RF Switches” CSIC 2005 Digest, pp. 200-203 (4 pgs).
Puentes, Daniel Calrissian, Notice of Allowance received from the USPTO dated May 23, 2018 for U.S. Appl. No. 15/442,491, 9 pgs.
Patel, Reema, Office Action received from the USPTO dated Dec. 14, 2018 for U.S. Appl. No. 15/829,773, 5 pgs.
Patel, Reema, Office Action received from the USPTO dated May 1, 2019 for U.S. Appl. No. 15/829,773, 40 pgs.
Patel, Reema, Notice of Allowance received from the USPTO dated Aug. 14, 2019 for U.S. Appl. No. 15/829,773, 12 pgs.
Patel, Reema, Notice of Allowance received from the USPTO dated Nov. 29, 2019 for U.S. Appl. No. 15/829,773, 13 pgs.
Patel, Reema, Response to Rule 312 Communication received from the USPTO dated Feb. 13, 2020 for U.S. Appl. No. 15/829,773, 3 pgs.
Willoughby, Terrence Ronique, Notice of Allowance received from the USPTO dated Jul. 20, 2018 for U.S. Appl. No. 15/688,658, 11 pgs.
Itoh, et al., English translation of Office Action received from the JPO dated Aug. 28, 2018 for appln. No. 2017-102495, 2 pgs.
Rhaman, Hafizur, Office Action received from the USPTO dated Nov. 19, 2018 for U.S. Appl. No. 15/279,302, 82 pgs.
Puentes, Daniel Calrissian, Office Action received from the USPTO dated Dec. 18, 2018 for U.S. Appl. No. 16/025,922, 20 pgs.
Puentes, Danil Calrissian, Final Office Action received from the USPTO dated Apr. 10, 2019 for U.S. Appl. No. 16/025,922, 14 pgs.
Puentes, Danil Calrissian, Applicant-Initiated Interview Summary received from the USPTO dated Apr. 29 2019 for U.S. Appl. No. 16/025,922, 3 pgs.
Puentes, Danil Calrissian,Advisory Action received from the USPTO dated Jun. 24, 2019 for U.S. Appl. No. 16/025,922, 6 pgs.
Puentes, Danil Calrissian, Notice of Allowance received from the USPTO dated Aug. 19, 2019 for U.S. Appl. No. 16/025,922, 13 pgs.
Willoughby, Terrence Ronique, Office Action received from the USPTO dated Oct. 11, 2019 for U.S. Appl. No. 16/156,930, 33 pgs.
Brosa, Anna-Maria, Office Action received from the EPO dated Dec. 11, 2019 for appln. No. 18157696.8, 8 pgs.
Nguyen, Hai L., Notice of Allowance received from the USPTO dated Dec. 27, 2019 for U.S. Appl. No. 16/025,922, 12 pgs.
Englekirk, Robert Mark, Preliminary Amendment filed in the USPTO dated Feb. 23, 2018 for U.S. Appl. No. 15/829,773, 6 pgs.
PSEMI Corporation, Response filed in the USPTO dated Jan. 15, 2019 for U.S. Appl. No. 15/829,773, 6 pgs.
PSEMI Corporation, Response filed in the USPTO dated Aug. 1, 2019 for U.S. Appl. No. 15/829,773, 7 pgs.
PSEMI Corporation, Amendment After Allowance filed in the USPTO dated Jan. 9, 2020 for U.S. Appl. No. 15/829,773, 6 pgs.
Willoughby, Terrence Ronique, Final Office Action received from the USPTO dated Jun. 24, 2020 for U.S. Appl. No. 16/156,930, 30 pgs.
Newman, “Radiation Hardened Power Electronics”, Intersil Corporation, 1999, pp. 1-4.
Kelly, Response and Terminal Disclaimer filed in the USPTO dated Mar. 2010 relating to U.S. Appl. No. 11/347,014.
Burgener, et al., Response filed in the USPTO dated May 2006 relating to U.S. Appl. No. 10/922,135.
Kelly, Response to Office Action mailed to USPTO relating to U.S. Appl. No. 11/351,342 dated Jan. 30, 2009.
“RF & Microwave Device Overview 2003—Silicon and GaAs Semiconductors”, NEC, 2003.
“RF Amplifier Design Using HFA3046, HFA3096, HFA3127, HFA3128 Transistor Arrays”, Intersil Corporation, 1996, pp. 1-4.
“SA630 Single Pole Double Throw (SPDT) Switch”, Philips Semiconductors, 1997.
Narendra, et al., “Scaling of Stack Effects and its Application for Leakage Reduction”, ISLPED 2001, 2001, pp. 195-200.
Huang, “Schottky Clamped MOS Transistors for Wireless CMOS Radio Frequency Switch Application”, University of Florida, 2001, pp. 1-167.
Botto, et al., “Series Connected Soft Switched IGBTs for High Power, High Voltage Drives Applications: Experimental Results”, IEEE, 1997, pp. 3-7.
Baker, et al., “Series Operation of Power MOSFETs for High Speed Voltage Switching Applications”, American Institute of Physics, 1993, pp. 1655-1656.
Lovelace, et al., “Silicon MOSFET Technology for RF ICs”, IEEE, 1995, pp. 1238-1241.
Rodgers, et al., “Silicon UTSi CMOS RFIC for CDMA Wireless Communications System”, IEEE MTT-S Digest, 1999, pp. 485-488.
“Silicon Wave SiW1502 Radio Modem IC”, Silicon Wave, 2000, pp. 1-21.
Johnson, et al., “Silicon-On-Sapphire MOSFET Transmit/Receive Switch for L and S Band Transceiver Applications”, Electronic Letters, 1997, pp. 1324-1326.
Reedy, et al., “Single Chip Wireless Systems Using SOI”, IEEE International SOI Conference, 1999, pp. 8-11.
Stuber, et al., “SOI CMOS with High Performance Passive Components for Analog, RF and Mixed Signal Designs”, IEEE International SOI Conference, 1998, pp. 99-100.
Chung, et al., “SOI MOSFET Structure with a Junction Type Body Contact for Suppression of Pass Gate Leakage”, IEEE Transactions on Electron Devices, vol. 48, No. 7, Jul. 2001.
Rozeau, “SOI Technologies Overview for Low Power Low Voltage Radio Frequency Applications”, Analog Integrated Circuits and Signal Processing, Nov. 2000, pp. 93-114.
Fukuda, et al., “SOI CMOS Device Technology”, Special Edition on 21st Century Solutions, 2001, pp. 54-57.
Fukuda, et al., “SOI CMOS Device Technology”, OKI Technical Review, 2001, pp. 54-57.
Kusunoki, et al., “SPDT Switch MMIC Using E/D Mode GaAs JFETs for Personal Communications”, IEEE GaAs IC Symposium, 1992, pp. 135-138.
Caverly, et al., “SPICE Modeling of Microwave and RF Control Diodes”, IEEE, 2000, pp. 28-31.
Kuang, et al., “SRAM Bitline Circuits on PD SOI: Advantages and Concerns”, IEEE Journal of Solid State Circuits, vol. 32, No. 6, Jun. 1997.
Baker, et al., “Stacking Power MOSFETs for Use in High Speed Instrumentation”, American Institute of Physics, 1992, pp. 5799-5801.
Sanders, “Statistical Modeling of SOI Devices for the Low Power Electronics Program”, AET, Inc., 1995, pp. 1-109.
Maeda, et al., “Substrate Bias Effect and Source Drain Breakdown Characteristics in Body Tied Short Channel SOI MOSFETs”, IEEE Transactions on Electron Devices, vol. 46, No. 1, Jan. 1999, pp. 151-158.
Makioka, et al., “Super Self Aligned GaAs RF Switch IC with 0.25dB Extremely Low Insertion Loss for Mobile Communication Systems”, IEEE Transactions on Electron Devices, vol. 48, No. 8, Aug. 2001, pp. 1510-1514.
Karandikar, et al., “Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect”, ACM, 2001, pp. 1-14.
Huang, et al., “TFSOI Can It Meet the Challenge of Single Chip Portable Wireless Systems”, IEEE International SOI Conference, 1997, pp. 1-3.
Devlin, “The Design of Integrated Switches and Phase Shifters”, 1999.
Edwards, et al., “The Effect of Body Contact Series Resistance on SOI CMOS Amplifier Stages”, IEEE Transactions on Electron Devices, vol. 44, No. 12, Dec. 1997, pp. 2290-2294.
Hess, et al., “Transformerless Capacitive Coupling of Gate Signals for Series Operation of Power MOS Devices”, IEEE, 1999, pp. 673-675.
Sleight, et al., “Transient Measurements of SOI Body Contact Effectiveness”, IEEE Electron Device Letters, vol. 19, No. 12, Dec. 1998.
“uPG13xG Series L-Band SPDT Switch GaAs MMIC”, NEC, 1996, pp. 1-30.
Reedy, et al., “UTSi Cmos: A Complete RF SOI Solution”, Peregrine Semiconductor, 2001, pp. 1-6.
Hittite Microwave, “Wireless Symposium 2000 is Stage for New Product Introductions”, Hittite Microwave, 2000, pp. 1-8.
Montoriol, et al., “3.6V and 4.8V GSM/DCS1800 Dual Band PA Application with DECT Capability Using Standard Motorola RFICs”, 2000, pp. 1-20.
Wang, et al., “Efficiency Improvement in Charge Pump Circuits”, IEEE Journal of Solid-State Circuits, vol. 32, No. 6, Jun. 1997, pp. 852-860.
Numata, et al., “A +2.4/0 V Controlled High Power GaAs SPDT Antenna Switch IC for GSM Application”, IEEE Radio Frequency Integrated Circuits Symposium, 2002, pp. 141-144.
Huang, et al., “A 0.5-um CMOS T/R Switch for 900-MHz Wireless Applications”, IEEE Journal of Solid-State Circuits, 2001, pp. 486-492.
Tinella, et al., “A 0.7dB Insertion Loss CMOS—SOI Antenna Switch with More than 50dB Isolation over the 2.5 to 5GHz Band”, Proceeding of the 28th European Solid-State Circuits Conference, 2002, pp. 483-486.
Ohnakado, et al., “A 1.4dB Insertion Loss, 5GHz Transmit/Receive Switch Utilizing Novel Depletion-Layer Extended Transistors (DETs) in 0.18um CMOS Process”, Symposium on VLSI Circuits Digest of Technical Papers, 2002, pp. 162-163.
Nakayama, et al., “A 1.9 GHz Single-Chip RF Front-End GaAs MMIC with Low-Distortion Cascade FET Mixer for Personal Handy-Phone System Terminals”, IEEE, 1998, pp. 205-208.
McGrath, et al., “A 1.9-GHz GaAs Chip Set for the Personal Handyphone System”, IEEE Transaction on Microwave Theory and Techniques, 1995, pp. 1733-1744.
Nakayama, et al., “A 1.9GHz Single-Chip RF Front End GaAs MMIC for Personal Communications”, Microwave and Millimeter-Wave Monolithic Circuits Symposium, 1996, pp. 69-72.
Valeri, et al., “A Silicon-on-Insulator Circuit for High Temperature, High-Voltage Applications”, IEEE, 1991, pp. 60-61.
Gu, et al., “A 2.3V PHEMT Power SP3T Antenna Switch IC for GSM Handsets”, IEEE GaAs Digest, 2003, pp. 48-51.
Darabi, et al., “A 2.4GHz CMOS Transceiver for Bluetooth”, IEEE, 2001, pp. 89-92.
Huang, et al., “A 2.4-GHz Single-Pole Double Throw T/R Switch with 0.8-dB Insertion Loss Implemented in a CMOS Process”, Silicon Microwave Integrated Circuits and Systems Research, 2001, pp. 1-4.
Huang, et al., “A 2.4-GHz Single-Pole Double Throw T/R Switch with 0.8-dB Insertion Loss Implemented in a CMOS Process (slides)”, Silicon Microwave Integrated Circuits and Systems Research, 2001, pp. 1-16.
Yamamoto, et al., “A 2.4GHz Band 1.8V Operation Single Chip SI-CMOS T/R MMIC Front End with a Low Insertion Loss Switch”, IEEE Journal of Solid-State Circuits, vol. 36, No. 8, Aug. 2001, pp. 1186-1197.
Kawakyu, et al., “A 2-V Operation Resonant Type T/R Switch with Low Distortion Characteristics for 1.9GHz PHS”, IEICE Trans Electron, vol. E81-C, No. 6, Jun. 1998, pp. 862-867.
Huang, et al., “A 900-MHz T/R Switch with a 0.8-dB Insertion Loss Implemented in a 0.5-um CMOA Process”, IEEE Custom Integrated Circuits Conference, 2000, pp. 341-344.
Workman, et al., “A Comparative Analysis of the Dynamic Behavior of BTG/SOI MOSFET's and Circuite with Distributed Body Resistance”, IEEE Transactions and Electron Devices, vol. 45, No. 10, Oct. 1998, pp. 2138-2145.
Valeri, et al., “A Composite High Voltage Device Using Low Voltage SOI MOSFET's”, IEEE, 1990, pp. 169-170.
Miyatsuji, et al., “A GaAs High Power RF Single Pole Double Throw Switch IC for Digital Mobile Communication System”, IEEE International Solid-State Circuits Conference, 1994, pp. 34-35.
Miyatsuji, et al., “A GaAs High Power RF Single Pole Dual Throw Switch IC for Digital Mobile Communication System”, IEEE Journal of Solid-State Circuits, 1995, pp. 979-983.
Puechberty, et al., “A GaAs Power Chip Set for 3V Cellular Communications”, 1994.
Yamamoto, et al., “A GaAs RD Transceiver IC for 1.9GHz Digital Mobile Communication Systems”, ISSCC96, 1996, pp. 340-341, 469.
Choumei, et al., “A High Efficiency, 2V Single Supply Voltage Operation RF Front End MMIC for 1.9GHz Personal Handy Phone Systems”, IEEE, 1998, pp. 73-76.
Schindler, et al., “A High Power 2-18 GHz T/R Switch”, IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium, 1990, pp. 119-122.
Gu, et al., “A High Power DPDT MMIC Switch for Broadband Wireless Applications”, IEEE MTT-S Digest, 2003, pp. 173-176.
Tinella, et al., “A High Performance CMOS-SOI Antenna Switch for the 2.5-5-GHz Band”, IEEE Journal of Solid-State Circuits, 2003, pp. 1279-1283.
Gu, et al., “A High Performance GaAs SP3T Switch for Digital Cellular Systems”, IEEE MTT-S Digest, 2001, pp. 241-244.
Numata, et al., “A High Power Handling GSM Switch IC with New Adaptive Control Voltage Generator Circuit Scheme”, IEEE Radio Frequency Integrated Circuits Symposium, 2003, pp. 233-236.
Madihian, et al., “A High Speed Resonance Type FET Transceiver Switch for Millimeter Wave Band Wireless Networks”, 26th EuMC, 1996, pp. 941-944.
Tokumitsu, et al., “A Low Voltage High Power T/R Switch MMIC Using LC Resonators”, IEEE Transactions on Microwave Theory and Techniques, 1995, pp. 997-1003.
Colinge, et al., “A Low Voltage Low Power Microwave SOI MOSFET”, IEEE International SOI Conference, 1996, pp. 128-129.
Johnson, et al., “A Model for Leakage Control by MOS Transistor Stacking”, ECE Technical Papers, 1997, pp. 1-28.
Matsumoto, et al., “A Novel High Frequency Quasi-SOI Power MOSFET for Multi-Gigahertz Application”, IEEE, 1998, pp. 945-948.
Giugni, “A Novel Multi-Port Microwave/Millimeter-Wave Switching Circuit”, Microwave Conference, 2000.
Caverly, “A Project Oriented Undergraduate CMOS Analog Microelectronic System Design Course”, IEEE, 1997, pp. 87-88.
Harjani, et al., “A Prototype Framework for Knowledge Based Analog Circuit Synthesis”, IEEE Design Automation Conference, 1987, pp. 42-49.
DeRossi, et al., “A Routing Switch Based on a Silicon-on-Insulator Mode Mixer”, IEEE Photonics Technology Letters, 1999, pp. 194-196.
Kanda, et al., “A Si RF Switch MMIC for the Cellular Frequency Band Using SOI-CMOS Technology”, The Institute of Electronics, Information and Communication Engineers, 2000, pp. 79-83.
Caverly, et al., “A Silicon CMOS Monolithic RF and Microwave Switching Element”, 27th European Microwave Conference, 1997, pp. 1046-1051.
Gu, et al., “Low Insertion Loss and High Linearity PHEMT SPDT and SP3T Switch Ics for WLAN 802.11a/b/g Application”, 2004 IEEE Radio Frequency Integrated Circuits Symposium, 2004, pp. 505-508.
Koudymov, et al., “Low Loss High Power RF Switching Using Multifinger AlGaN/GaN MOSHFETs”, University of South Carolina Scholar Commons, 2002, pp. 449-451.
Abidi, “Low Power Radio Frequency IC's for Portable Communications”, IEEE, 1995, pp. 544-569.
Kuo, et al., “Low Voltage SOI CMOS VLSI Devices and Circuits”, Wiley, 2001, pp. 57-60, 349-354.
Wei, et al., “Measuremenets of Transient Effects in SOI DRAM/SRAM Access Transistors”, IEEE Electron Device Letters, vol. 17, No. 5, May 1996.
De La Houssaye, et al., “Microwave Performance of Optically Fabricated T-Gate Thin Film Silicon on Sapphire Based MOSFET's”, IEEE Electron Device Letters, 1995, pp. 289-292.
Smuk, et al., “Monolithic GaAs Multi-Throw Switches with Integrated Low Power Decoder/Driver Logic”, 1997, IEEE Radio Frequency Integrated Circuits.
McGrath, et al., “Multi Gate FET Power Switches”, Applied Microwave, 1991, pp. 77-88.
Smuk, et al., “Multi-Throw Plastic MMIC Switches up to 6GHz with Integrated Positive Control Logic”, IEEE, 1999, pp. 259-262.
Razavi, “Next Generation RF Circuits and Systems”, IEEE, 1997, pp. 270-282.
Gould, et al., “NMOS SPDT Switch MMIC with >48dB Isolation and 30dBm IIP3 for Applications within GSM and UMTS Bands”, Bell Labs, 2001, pp. 1-4.
Caverly, “Nonlinear Properties of Gallium Arsenide and Silicon FET-Based RF and Microwave Switches”, IEEE, 1998, pp. 1-4.
Tieu, Notice of Allowance and Fee(s) Due from the USPTO dated May 2004 relating to U.S. Appl. No. 10/267,531.
Tieu, Notice of Allowance and Fee(s) Due from the USPTO dated Jul. 2008 relating to U.S. Appl. No. 11/582,206.
Tieu, Notice of Allowance and Fee(s) Due from the USPTO dated Jun. 2006 relating to U.S. Appl. No. 10/922,135.
Tran, Notice of Allowance and Fee(s) Due from the USPTO dated Jun. 2010 relating to U.S. Appl. No. 11/501,125.
Tieu, Notice of Allowance and Fee(s) Due from the USPTO dated Apr. 2010 relating to U.S. Appl. No. 11/347,014.
Tieu, Notice of Allowance and Fee(s) Due from the USPTO dated Dec. 2008 relating to U.S. Appl. No. 11/127,520.
Luu, Notice of Allowance and Fee(s) Due from the USPTO dated Jul. 2009 relating to U.S. Appl. No. 11/351,342.
Miyajima, Notice of Reasons for Refusal from the Japanese Patent Office dated Feb. 2006 relating to appln. No. 2003-535287.
McGrath, et al., “Novel High Performance SPDT Power Switches Using Multi-Gate FET's”, IEEE, 1991, pp. 839-842.
Tieu, Office Action from the USPTO dated Nov. 2007 relating to U.S. Appl. No. 11/582,206.
Tieu, Office Action from the USPTO dated Jun. 2005 relating to U.S. Appl. No. 10/922,135.
Tieu, Notice of Allowance from the USPTO dated Jun. 2006 relating to U.S. Appl. No. 10/922,135.
Chow, Office Action from the USPTO dated Apr. 2010 relating to U.S. Appl. No. 11/347,671.
Tieu, Office Action from the USPTO dated Sep. 2009 relating to U.S. Appl. No. 11/347,014.
Luu, Office Action from the USPTO dated Oct. 2008 relating to U.S. Appl. No. 11/351,342.
Chow, Office Action from the USPTO dated Aug. 2010 relating to U.S. Appl. No. 11/347,671.
Suematsu, “On-Chip Matching SI-MMIC for Mobile Communication Terminal Application”, IEEE, 1997, pp. 9-12.
Caverly, et al., “On-State Distortion in High Electron Mobility Transistor Microwave and RF Switch Control Circuits”, IEEE Transactions on Microwave Theory and Techniques, 2000, pp. 98-103.
Kelly, Proposed Amendment After Final from the USPTO dated Jun. 2009 relating to U.S. Appl. No. 11/351,342.
“Radiation Hardened CMOS Dual DPST Analog Switch”, Intersil, 1999, pp. 1-2.
Gibson, “The Communication Handbook”, CRC Press, 1997.
Hanzo, “Adaptive Wireless Transceivers”, Wiley, 2002.
Itoh, “RF Technologies for Low Power Wireless Communications”, Wiley, 2001.
Lossee, “RF Systems, Components, and Circuits Handbook”, Artech House, 1997.
Miller, “Modern Electronic Communications”, Prentice-Hall, 1999.
Minoli, “Telecommunications Technology Handbook”, Artech House, 2003.
Morreale, “The CRC Handbook of Modern Telecommunication”, CRC Press, 2001.
Sayre, “Complete Wireless Design”, McGraw-Hill, 2001.
Schaper, “Communications, Computations, Control, and Signal Processing”, Kluwer Academic, 1997.
Shafi, “Wireless Communications in the 21st Century”, Wiley, 2002.
Willtert-Porada, “Advances in Microwave Frequency Processing”, Springer, 2009.
Dang, Hung Q., Notice of Allowance received from the USPTO dated Oct. 1, 2012 for related U.S. Appl. No. 12/735,954, 67 pgs.
Caverly, “Development of a CMOS Cell Library for RF Wireless and Telecommunications Applications”, VLSI Symposium, 1998.
Caverly, “Distortion Properties of Gallium Arsenide and Silicon RF and Microwave Switches”, IEEE, 1997, pp. 153-156.
Luu, Final Office Action received from the USPTO dated Apr. 2009 relating to U.S. Appl. No. 11/351,342.
Colinge, “Fully Depleted SOI CMOS for Analog Applications”, IEEE Transactions on Electron Devices, 1998, pp. 1010-1016.
Flandre, et al., “Fully Depleted SOI CMOS Technology for Low Voltage Low Power Mixed Digital/Analog/Microwave Circuits”, Analog Integrated Circuits and Signal Processing, 1999, pp. 213-228.
Yamao, “GaAs Broadband Monolithic Switches”, 1986, pp. 63-71.
Gopinath, et al., “GaAs FET RF Switches”, IEEE Transactions on Electron Devices, 1985, pp. 1272-1278.
Lee, et al., “Harmonic Distortion Due to Narrow Width Effects in Deep Submicron SOI-CMOS Device for Analog RF Applications”, 2002 IEEE International SOI Conference, Oct. 2002.
HI-5042 thru HI-5051 Datasheet, Harris Corporation, 1999.
Eisenberg, et al., “High Isolation 1-20GHz MMIC Switches with On-Chip Drivers”, IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium, 1989, pp. 41-45.
Kohama, et al., “High Power DPDT Antenna Switch MMIC for Digital Cellular Systems”, GaAs IC Symposium, 1995, pp. 75-78.
Kohama, et al., “High Power DPDT Antenna Switch MMIC for Digital Cellular Systems”, IEEE Journal of Solid-State Circuits, 1996, pp. 1406-1411.
Yun, et al., “High Power-GaAs MMIC Switches wtih Planar Semi-Insulated Gate FETs (SIGFETs)”, International Symposium on Power Semiconductor Devices & ICs, 1990, pp. 55-58.
Caverly, “High Power Gallium Nitride Devices for Microwave and RF Control Applications”, 1999, pp. 1-30.
Caverly, “High Power Gallium Nitride Devices for Microwave and RF Control Applications”, 2000, pp. 1-33.
Masuda, et al., “High Power Heterojunction GaAs Switch IC with P-1dB of more than 38dBm for GSM Application”, IEEE, 1998, pp. 229-232.
De Boer, et al., “Highly Integrated X-Band Multi-Function MMIC with Integrated LNA and Driver Amplifier”, TNO Physics and Electronics Laboratory, 2002, pp. 1-4.
Suehle, et al., “Low Electric Field Breakdown of Thin Si02 Films Under Static and Dynamic Stress”, IEEE Transactions on Electron Devices, vol. 44, No. 5, May 1997.
Kanda, et al., “High Performance 19GHz Band GaAs FET Switches Using LOXI (Layerd Oxide Isolation—MESFETs”, IEEE, 1997, pp. 62-65.
Uda, et al., “High-Performance GaAs Switch IC's Fabricated Using MESFET's with Two Kinds of Pinch-Off Voltages and a Symmetrical Pattern Configuration”, IEEE Journal of Solid-State Circuits, vol. 29, No. 10, Oct. 1994, pp. 1262-1269.
Uda, et al., “High Performance GaAs Switch IC's Fabricated Using MESFETs with Two Kinds of Pinch Off Voltages”, IEEE GaAs IC Symposium, 1993, pp. 247-250.
Armijos, “High Speed DMOS FET Analog Switches and Switch Arrays”, Temic Semiconductors 1994, pp. 1-10.
Katzin, et al., “High Speed 100+ W RF Switches Using GaAs MMICs”, IEEE Transactions on Microwave Theory and Techniques, 1992, pp. 1989-1996.
Honeywell, “Honeywell SPDT Absorptive RF Switch”, Honeywell, 2002, pp. 1-6.
Honeywell, “Honeywell SPDT Reflective RF Switch”, Honeywell Advance Information, 2001, pp. 1-3.
Hirano, et al., “Impact of Actively Body Bias Controlled (ABC) SOI SRAM by Using Direct Body Contact Technology for Low Voltage Application”, IEEE, 2003, pp. 2.4.1-2.4.4.
Larson, “Integrated Circuit Technology Options for RFIC's—Present Status and Future Directions”, IEEE Journal of Solid-State Circuits, 1998, pp. 387-399.
Burghartz, “Integrated RF and Microwave Components in BiCMOS Technology”, IEEE Transactions on Electron Devices, 1996, pp. 1559-1570.
Kelly, “Integrated Ultra CMIS Designs in GSM Front End”, Wireless Design Magazine, 2004, pp. 18-22.
Bonkowski, et al., “Integraton of Triple Band GSM Antenna Switch Module Using SOI CMOS”, IEEE Radio Frequency Integrated Circuits Symposium, 2004, pp. 511-514.
Le, International Search Report from the USPTO dated Mar. 2003 relating to U.S. Appl. No. 10/267,531.
Marenk, et al., “Layout Optimization of Cascode RF SOI Transistors”, IEEE International SOI Conference, 2001, pp. 105-106.
Suematsu, et al., “L-Band Internally Matched Si-MMIC Front End”, IEEE, 1996, pp. 2375-2378.
Adan, et al., “Linearity and Low Noise Performance of SOIMOSFETs for RF Applications”, IEEE International SOI Conference, 2000, pp. 30-31.
Megahed, et al., “Low Cost UTSi Technology for RF Wireless Applications”, IEEE MTT-S Digest, 1998.
Yamamoto, et al., “A Single-Chip GaAs RF Transceiver for 1.9GHz Digital Mobile Communication Systems”, IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp. 1964-1973.
Tsutsumi, et al., “A Single Chip PHS Front End MMIC with a True Single +3 Voltage Supply”, IEEE Radio Frequency Integrated Circuits Symposium, 1998, pp. 105-108.
Wambacq, et al., “A Single Package Solution for Wireless Transceivers”, IEEE, 1999, pp. 1-5.
Eggert, et al., A SOI-RF-CMOS Technology on High Resistivity SIMOX Substrates for Microwave Applications to 5GHz, IEEE Transactions on Electron Devices, 1997, pp. 1981-1989.
Hu, et al., “A Unified Gate Oxide Reliability Model”, IEEE 37th Annual International Reliability Physic Symposium, 1999, pp. 47-51.
Szedon, et al., “Advanced Silicon Technology for Microwave Circuits”, Naval Research Laboratory, 1994, pp. 1-110.
Johnson, et al., “Advanced Thin Film Silicon-on-Sapphire Technology: Microwave Circuit Applications”, IEEE Transactions on Electron Devices, 1998, pp. 1047-1054.
Burgener, et al., Amendment filed in the USPTO dated Dec. 2005 relating to U.S. Appl. No. 10/922,135.
Burgener, et al., Amendment filed in the USPTO dated May 2008 relating to U.S. Appl. No. 11/582,206.
Kai, An English translation of an Office Action received from the Japanese Patent Office dated Jul. 2010 relating to appln. No. 2007-518298.
Burgener, et al., Amendment filed in the USPTO dated Apr. 2010 relating to U.S. Appl. No. 11/501,125.
Heller, et al., “Cascode Voltage Switch Logic: A Different CMOS Logic Family”, IEEE International Solid-State Circuits Conference, 1984, pp. 16-17.
Pylarinos, “Charge Pumps: An Overview”, Proceedings of the IEEE International Symposium on Circuits and Systems, 2003, pp. 1-7.
Doyama, “Class E Power Amplifier for Wireless Transceivers”, University of Toronto, 1999, pp. 1-9.
“CMOS Analog Switches”, Harris, 1999, pp. 1-9.
Madihian, et al., “CMOS RF Ics for 900MHz-2.4GHz Band Wireless Communication Networks”, IEEE Radio Frequency Integrated Circuits Symposium, 1999, pp. 13-16.
“CMOS SOI RF Switch Family”, Honeywell, 2002, pp. 1-4.
“CMOS SOI Technology”, Honeywell, 2001, pp. 1-7.
Analog Devices, “CMOS, Low Voltage RF/Video, SPST Switch”, Analog Devices, inc., 1999, pp. 1-10.
Eggert, et al., “CMOS/SIMOX-RF-Frontend for 1.7GHz”, Solid State Circuits Conference, 1996.
Orndorff, et al., CMOS/SOS/LSI Switching Regulator Control Device, IEEE International, vol. XXI, Feb. 1978, pp. 234-235.
Burgener, et al., Comments on Examiners Statements of Reasons for Allowance filed in the USPTO dated Aug. 2004 relating to U.S. Appl. No. 10/267,531.
Aquilani, Communication and supplementary European Search Report dated Nov. 2009 relating to appln. No. 05763216.
Van Der Peet, Communications pursuant to Article 94(3) EPC received from the EPO dated Jun. 2008 relating to appln. No. 02800982.7-2220.
Aquilani, Communications pursuant to Article 94(3) EPC received from the EPO dated Mar. 2010 relating to appln. No. 05763216.8.
Weman, Communication under Rule 71(3) EPC and Annex Form 2004 received from the EPO dated Nov. 2009 relating to appln. No. 020800982.7.
Van Der Peet, Communications pursuant to Article 94(3) EPC dated Aug. 2009 relating to appln. No. 02800982.7-2220.
Yamamoto, et al., “Design and Experimental Results of a 2V-Operation Single-Chip GaAs T/R MMIC Front-End for 1.9GHz Personal Communications”, IEEE, 1998, pp. 7-12.
Savla, “Design and Simulation of a Low Power Bluetooth Transceiver”, The University of Wisconsin, 2001, pp. 1-90.
Henshaw, “Design of an RF Transceiver”, IEEE Colloquium on Analog Signal Processing, 1998.
Baker, et al., “Designing Nanosecond High Voltage Pulse Generators Using Power MOSFET's”, Electronic Letters, 1994, pp. 1634-1635.
Wong, Alan, Office Action received from the USPTO dated Sep. 12, 2014 for U.S. Appl. No. 13/595,893, 11 pgs.
Peregrine Semiconductor Corporation, Response filed in the EPO dated Oct. 14, 2014 for appln. No. 10011669.8, 30 pgs.
Dang, Hung Q., Notice of Allowance received from the USPTO dated Nov. 18, 2014 for U.S. Appl. No. 12/735,954, 33 pgs.
Ranta, et al., Response filed in the USPTO dated Nov. 12, 2014 for U.S. Appl. No. 14/178,116, 8 pgs.
Ichikawa, Takenori, Office Action and English translation received from the JPO dated Nov. 18, 2014 for appln. No. 2013-181032, 15 pgs.
Wong, Alan, Notice of Allowance received from the USPTO dated Nov. 21, 2014 for U.S. Appl. No. 13/586,738, 205 pgs.
Burgener, et al., Response filed in the USPTO dated Nov. 24, 2014 for U.S. Appl. No. 14/062,791, 8 pgs.
Peregrine Semiconductor Corporation, Response filed in the EPO dated Dec. 10, 2014 for appln. No. 14165804.7, 76 pgs.
Reedy, et al., Response filed in the USPTO dated Dec. 12, 1 for U.S. Appl. No. 13/595,893, 24 pgs.
Tieu, Binh Kien, Notice of Allowance received from the USPTO dated Jan. 23, 2015 for U.S. Appl. No. 14/062,791, 8 pgs.
Weman, Eva, Communication of a notice of opposition received from the EPO dated Nov. 8, 2011 for related appln No. 028000982.7-2220, 33 pgs.
Caverly, Robert H., “Linear and Nonlinear Characteristics of the Silicon CMOS Monolithic 50-Ω Microwave and RF Control Element”, IEEE Journal of Solid-State Circuits, vol. 34, No. 1, Jan. 1999, pp. 124-126.
Philips Semiconductors, Product Specification, IC17 Data Handbook, Nov. 7, 1997, pp. 1-14.
Iyama, Yoshitada, et al., “L-Bank SPDT Switch Using Si-MOSFET”, IEICE Trans. Electronic, vol. E-79-C, No. 5, May 1996, pp. 636-643.
Yamamoto, Kazuya, et al., “A 2.2-V Operating, 2.4-GHz Single-Chip GaAs MMIC Transceiver for Wireless Applications”, IEEE Journal of Solid-State Circuits, vol. 34, No. 4, Apr. 1999, pp. 502-512.
Unterberger, Michael, Extended Search Report received from the EPO dated Sep. 30, 2011 for related appln. No. 10011669.8, 9 pgs.
Le, Dinh Thanh, Office Action received from the USPTO dated Dec. 1, 2011 for related appln. No. 12/803,064, 23 pgs.
Peregrine Semiconductor Corporation, Response filed in the EPO dated Feb. 10, 2012 for related appln .No. 09715932.1, 47 pgs.
Cole, Brandon S., Office Action received from the USPTO dated Feb. 24, 2012 for related U.S. Appl. No. 12/803,133, 36 pgs.
Ranta, Tero Tapio, Amendment filed in the USPTO dated Mar. 21, 2012 for related U.S. Appl. No. 12/735,954, 16 pgs.
Peregrine Semiconductor Corporation, Response to Notice of Opposition filed in the EPO dated Apr. 17, 2012 for related patent No. 1451890, 42 pgs.
Burgener, et al., First Preliminary Amendment filed in the USPTO dated Apr. 27, 2012 for related U.S. Appl. No. 12/980,161, 21 pgs.
Ranta, et al., Amendment submitted with RCE filed in the USPTO dated Apr. 30, 2012 for related U.S. Appl. No. 12/803,064, 16 pgs.
Kurisu, Masakazu, Japanese Office Action and translation thereof dated Apr. 17, 2012 for related appln. No. 2010-506156, 4 pgs.
Peregrine Semiconductor Corporation, Response filed in the EPO dated May 15, 2012 for related appln. No. 10011669.8, 19 pgs.
Ranta, et al., Response filed in the USPTO dated May 23, 2012 for related U.S. Appl. No. 12/803,133, 7 pgs.
Le, Dinh Thanh, Office Action received from the USPTO dated Jun. 13, 2012 for related U.S. Appl. No. 12/803,064, 14 pgs.
Cole, Brandon S., Notice of Allowance received from the USPTO dated Jun. 8, 2012 for related U.S. Appl. No. 12/803,133, 12 pgs.
Theunissen, Lars, Communication under Rule 71(3) EPC received from the EPO dated Jul. 2, 2012 for related appln. No. 09715932.1, 98 pgs.
Dang, Hung Q., Notice of Allowance received from the USPTO dated Jul. 12, 2012 for related U.S. Appl. No. 12/735,954, 20 pgs.
Peregrine Semiconductor Corporation, Response filed in the EPO dated Sep. 11, 2013 for appln. No. 1219418.6, 16 pgs.
Ranta, et al., Response filed in the USPTO dated Sep. 17, 2013 for U.S. Appl. No. 12/803,139, 14 pgs.
Volker, Simon, Communication pursuant to Article 94(3) EPC received from the EPO dated Sep. 24, 2013 for appln. No. 07794407.2, 5 pgs.
Tieu, Binh Kien, Notice of Allowance received from the USPTO dated Sep. 30, 2013 for U.S. Appl. No. 12/980,161, 8 pgs.
Unterberger, M, Summons to attend oral proceedings pursuant to Rule 115(1) EPC for appln. No. 02800982.7, 15 pgs.
Rojas, Daniel E. Notice of Allowance received from the USPTO dated Oct. 22, 2013 for U.S. Appl. No. 12/803,139, 142 pgs.
Funakoshi, Ryo, Japanese Office Action and English translation received from the JPO dated Oct. 29, 2013 for appln. No. 2013-006353, 15 pgs.
Brosa, Anna-Maria, Communication under Rule 71(3) EPC received from the EPO dated Nov. 12, 2013 for appln. No. 12194187.6, 94 pgs.
Peregrine Semiconductor Corporation, Response to Summons filed in the EPO dated Jan. 9, 2014 for appln. No. 02800982.7, 21 pgs.
Schussler, Andrea, Report regarding Opposition Conclusion received from associated dated Feb. 25, 2014 for appln. No. 02800982.7, 13 pgs.
Dang, Hung Q., Office Action received from the USPTO dated Feb. 26, 2014 for U.S. Appl. No. 12/735,954, 34 pgs.
Unterberger, Michael, Communication pursuant to Article 101(1) and Rule 81(2) to (3) EPC received from the EPO dated Mar. 3, 2014 for appln. No. 02800982.7, 3 pgs.
Weman, Eva, Provision of the minutes in accordance with Rule 124(4) EPC received from the EPO dated Apr. 10, 2014 for appln. No. 02800982.7, 9 pgs.
Gonzalez, Brosa, Decision to grant a European patent pursuant to Article 97(1) EPC received from the EPO dated Apr. 17, 2014 for appln. No. 12194187.6, 1 pg.
European Patent Office, Noting of loss of rights pursuant to Rule 112(1) EPC received from the EPO dated May 2, 2014 for appln. No. 07794407.2, 1 pgs.
Brosa, Anna-Maria, Extended Search Report received from the EPO dated May 27, 2014 for appln. No. 14165804.7, 8 pgs.
Tieu, Binh Kien, Office Action received from the USPTO dated Jun. 24, 2014 for U.S. Appl. No. 14/062,791, 7 pgs.
Ranta, Tero, Amendment filed in the USPTO dated Jun. 26, 2014 for U.S. Appl. No. 12/735,954, 33 pgs.
Peregrine Semiconductor Corporation, Response filed in the EPO dated Jul. 11, 2014 for appln. No. 07794407.2, 32 pgs.
European Patent Office, Communication pursuant to Rule 58 EPC received from the EPO dated Jul. 21, 2014 for appln. No. 07794407.2, 5 pgs.
Peregrine Semiconductor Corporation, Response filed in the EPO dated Jul. 30, 2014 for appln. No. 07794407.2, 25 pgs.
Rojas, Daniel E., Office Action received from the USPTO dated Aug. 12, 2014 for U.S. Appl. No. 14/178,816, 9 pgs.
Bawell, et al., Comments on Examiners Statement of Reasons for Allowance filed in the USPTO dated Feb. 23, 2015 for U.S. Appl. No. 13/586,738, 3 pgs.
Wong, Alan, Final Office Action received from the USPTO dated Mar. 4, 2015 for U.S. Appl. No. 13/595,893, 33 pgs.
Puentes, Daniel, Notice of Allowance received from the USPTO dated Mar. 31, 2015 for U.S. Appl. No. 14/178,116, 181 pgs.
Tieu, Binh Kien, Notice of Allowance received from the USPTO dated May 14, 2015 for U.S. Appl. No. 14/062,791, 211 pgs.
Ranta, Tero Tapio, Preliminary Amendment filed in the USPTO dated Jul. 8, 2015 for U.S. Appl. No. 14/638,917, 8 pgs.
Wong, Alan, Notice of Allowance received from the USPTO dated Aug. 17, 2015 for U.S. Appl. No. 13/595,893, 12 pgs.
Stuber, et al., Response/Amendment and Terminal Disclaimers filed in the USPTO dated Jul. 27, 2015 for U.S. Appl. No. 13/948,094, 26 pgs.
Tieu, Binh Kien, Notice of Allowance received from the USPTO dated Sep. 4, 2015 for U.S. Appl. No. 14/062,791, 12 pgs.
Peregrine Semiconductor Corporation, Response filed in the EPO dated Sep. 10, 2015 for appln. No. 14165804.7, 14 pgs.
Le, Dinh Thanh, Office Action received from the USPTO dated Sep. 22, 2015 for U.S. Appl. No. 14/165,422, 4 pgs.
Rahman, Hafizur, Office Action received from the USPTO dated Nov. 2, 2020 for U.S. Appl. No. 16/524,710, 68 pgs.
“An Ultra-Thin Silicon Technology that Provides Integration Solutions on Standard CMOS”, Peregrine Semiconductor, 1998.
Caverly, “Distortion in Microwave Control Devices”, 1997.
Masuda, et al., “RF Current Evaluation of ICs by MP-10L”, NEC Research & Development, vol. 40-41, 1999, pp. 253-258.
“Miniature Dual Control SP4T Switches for Low Cost Multiplexing”, Hittite Microwave, 1995.
Uda, “Miniturization and High Isolation of a GaAs SPDT Switch IC Mounted in Plastic Package”, 1996.
Marshall, “SOI Design: Analog, Memory and Digital Techniques”, Kluwer Academic Publishers, 2002.
Bernstein, “SOI Circuit Design Concepts”, IBM Microelectronics, 2007.
Brinkman, Paul, et al., “Respondents' Notice of Prior Art”, Aug. 31, 2012, 59 pgs.
Le, Dinh Thanh, Office Action received from the USPTO dated Nov. 20, 2013 for related U.S. Appl. No. 12/803,064, 6 pgs.
Simon, Volker, Communication Pursuant to Article 94(3) EPC dated Nov. 16, 2012 for related appln,. No. 09174085.2, 8 pgs.
Dang, Hung Q., Notice of Allowance received from the USPTO dated Jan. 25, 2013 for related U.S. Appl. No. 12/735,954, 42 pgs.
Rojas, Daniel, Office Action received from the USPTO dated Feb. 21, 2013 for related U.S. Appl. No. 12/803,139, 7 pgs.
Tieu, Binh Kien, Office Action received from the USPTO dated Feb. 19, 2013 for related U.S. Appl. No. 12/980,161, 97 pgs.
Ranta, et al., Response After Final filed in the USPTO dated Jan. 22, 2013 for related U.S. Appl. No. 12/803,064, 7 pgs.
Le, Dinh Thanh, Advisory Action received from the USPTO dated Feb. 6, 2013 for related U.S. Appl. No. 12/803,064, 2 pgs.
Ranta, et al., Second Response After Final filed in the USPTO dated Feb. 20, 2013 for related U.S. Appl. No. 12/803,064, 9 pgs.
Le, Dinh Thanh, Notice of Allowance received from the USPTO dated Mar. 4, 2013 for related U.S. Appl. No. 12/803,064, 6 pgs.
Brosa, Anna-Maria, European Search Report received from the EPO dated Feb. 1, 2013 for related appln. No. 12194187, 10 pgs.
Dang, Hung Q., Notice of Allowance received from USPTO dated May 10, 2013 for related U.S. Appl. No. 12/735,954, 22 pgs.
Ranta, et al., Response to Office Action filed in USPTO dated May 20, 2013 for related U.S. Appl. No. 12/803,139, 8 pgs.
Peregrine Semiconductor Corporation, Response filed in the EPO dated May 23, 2013 for related appln. No. 09174085.2, 16 pgs.
Patel, Reema, Office Action received from the USPTO dated Dec. 5, 2011 for U.S. Appl. No. 13/046,560, 13 pgs.
Englekirk, Robert Mark, Amendment filed in the USPTO dated Mar. 5, 2012 for U.S. Appl. No. 13/046,560, 4 pgs.
Patel, Reema, Notice of Allowance received from the USPTO dated May 24, 2012 for U.S. Appl. No. 13/046,560, 15 pgs.
Parwl, Reema, Notice of Allowance received from the USPTO dated Mar. 15, 2013 for U.S. Appl. No. 13/046,560, 10 pgs.
Englekirk, Robert Mark, Comments on Examiner's Statement of Reasons for Allowance filed in the USPTO dated Jun. 7, 2013 for U.S. Appl. No. 13/046,560, 3 pgs.
Ranta, Tero Tapio, Comments on Examiner's Statement of Reasons for Allowance filed in the USPTO dated Feb. 18, 2015 for U.S. Appl. No. 12/735,954, 3 pgs.
Mishra, et al., “High Power Broadband Amplifiers for 1-18 GHz Naval Radar” University of California, Santa Barbara, pp. 1-9, Jul. 1, 1998.
Perraud, et al., “A Direct-Conversion CMOS Transceiver for the 802.11a/b/g WLAN Standard Utilizing a Cartesian Feedback Transmitter”, IEEE Journal of Solid-State Circuits, vol. 39, No. 12, Dec. 2004, pp. 2226-2238.
Rohde, et al., “Optic/Millimeter-Wave Converter for 60 Ghz Radio-Over-Fiber Systems”, Fraunhofer-Institut für Angewandte Festkörperphysik Freiburg i. Br., Apr. 1997, pp. 1-5.
Darabi, et al. “A Dual-Mode 802.11b/Bluetooth Radio in 0.35-⋅m CMOS”, IEEE Journal of Solid-State Circuits, vol. 40, No. 3, Mar. 2005, pp. 698-706.
Schlechtweg, et al., “Multifunctional Integration Using HEMT Technology”, Fraunhofer Institute for Applied Solid State Physics, (date uncertain, believed Mar. 1997).
Chow, Charles Chiang, Office Action received from the USPTO dated Mar. 2, 2011 for related U.S. Appl. No. 11/347,671, 14 pgs.
Kelly, Dylan, Amendment filed in the USPTO dated May 2, 2011 for related U.S. Appl. No. 11/347,671, 6 pgs.
Nguyen, Patricia T., Office Action received from the USPTO dated Oct. 25, 2005 for related U.S. Appl. No. 10/875,405, 7 pgs.
Burgener, et al., Amendment filed in USPTO dated Jan. 25, 2006 for related U.S. Appl. No. 10/875,405, 11 pgs.
Nguyen, Patricia, Office Action received from USPTO dated Apr. 20, 2006 for related U.S. Appl. No. 10/875,405, 10 pgs.
Burgener, et al., Amendment filed in USPTO dated Aug. 21, 2006 for related U.S. Appl. No. 10/875,405, 10 pgs.
Ngyuen, Patricia, Notice of Allowance received from USPTO dated Sep. 27, 2006 for related U.S. Appl. No. 10/875,405, 6 pgs.
Burgener, et al., Comments on Examiner's Statement of Reasons for Allowance dated Dec. 26, 2006 for related U.S. Appl. No. 10/875,405, 2 pgs.
Le, Lana N., Notice of Allowance received from the USPTO dated Sep. 26, 2005 for related U.S. Appl. No. 11/158,597, 10 pgs.
Le, Lana, International Search Report received from USPTO dated Nov. 15, 2005 for related PCT appln. No. PCT/US2005/022407, 10 pgs.
Le, Lana N., Notice of Allowance received from the USPTO dated Feb. 27, 2006 for related U.S. Appl. No. 11/158,597, 8 pgs.
Dinh, Le T., International Search Report received from USPTO dated Mar. 28, 2003 for related application No. PCT/US02/32266, 3 pgs.
Lauterbach, et al. “Charge Sharing Concept and New Clocking Scheme for Power Efficiency and Electromagnetic Emission Improvement of Boosted Charge Pumps”, IEEE Journal of Solid-State Circuits, vol. 35, No. 5, May 2000, pp. 719-723.
Texas Instruments, “TPS60204, TPS60205, Regulated 3.3-V, 100-mA Low-Ripple Charge Pump Low Power DC/DC Converters”, published Feb. 2001, rev. Sep. 2001, pp. 1-18.
Nork, Sam, “New Charge Pumps Offer Low Input and Output Noise” Linear Technology Corporation, Design Notes, Design Note 243, published Nov. 2000, pp. 1-2.
Linear Technology, “LTC1550L/LTC1551L: Low Noise Charge Pump Inverters in MS8 Shrink Cell Phone Designs”, published Dec. 1998, pp. 1-2.
Maxim Integrated Products, “Charge Pumps Shine in Portable Designs”, published Mar. 15, 2001, pp. 1-16.
Tran, Pablo N., Office Action received from the USPTO dated Mar. 19, 2009 for related U.S. Appl. No. 11/501,125, 17 pgs.
Burgener, et al., Amendment filed in the USPTO dated Jun. 19, 2009 for related U.S. Appl. No. 11/501,125, 5 pgs.
Tran, Pablo N., Office Action received from the USPTO dated Oct. 29, 2009 for related U.S. Appl. No. 11/501,125, 19 pgs.
Lascari, Lance, “Accurate Phase Noise Prediction in PLL Synthesizers” Applied Microwave & Wireless, published May 2000, pp. 90-96.
Burgener, et al., Response (in Japanese) as filed in the Japanese Patent Office for related appln. No. 2007-518298 dated Oct. 15, 2010, 45 pages, plus translation of Response as filed dated Oct. 12, 2010, 10 pages.
Kai, Tetsuo, Translation of an Office Action received from the Japanese Patent Office dated Mar. 29. 2011 for related Japanese appln. No. 2010-232563, 4 pgs.
Chow, Charles Chiang, Office Action received from USPTO for related U.S. Appl. No. 11/347,671 dated Aug. 19, 2008, 14 pgs.
Kelly, Dylan, Amendment filed in the USPTO for related U.S. Appl. No. 11/347,671 dated Dec. 19, 2008, 15 pgs.
Chow, Charles Chiang, Office Action received from USPTO for related U.S. Appl. No. 11/347,671 dated Apr. 16, 2009, 16 pgs.
Kelly, Dylan, Response filed in the USPTO for related U.S. Appl. No. 11/347,671 dated Jun. 16, 2009, 14 pgs.
Chow, Charles Chiang, Office Action received from the USPTO for related U.S. Appl. No. 11/347,671 dated Jul. 20, 2009, 17 pgs.
Kelly, Dylan, Amendment filed in the USPTO for related U.S. Appl. No. 11/347,671 dated Jan. 20, 2010, 18 pgs.
Kelly, Dylan, Amendment filed in the USPTO for related U.S. Appl. No. 11/347,671 dated Jul. 28, 2010, 6 pgs.
Kelly, Dylan, Amendment filed in the USPTO for related U.S. Appl. No. 11/347,671 dated Dec. 20, 2010, 12 pgs.
Chow, Charles Chiang, Office Action received from the USPTO for related U.S. Appl. No. 11/347,671 dated Mar. 2, 2011, 15 pgs.
Chow, Charles Chiang, Advisory Action received from the USPTO for related U.S. Appl. No. 11/347,671 dated May 12, 2011, 3 pgs.
Shifrin, Mitchell, “Monolithic FET Structures for High-Power Control Component Applications”, IEEE Transactions on Microwave Theory and Techniques, vol. 37, No. 12, Dec. 1989, pp. 2134-2141.
Kelly, Dylan, Notice of Appeal filed in USPTO dated Jun. 2, 2011 for related U.S. Appl. No. 11/347,671, 6 pgs.
Peregrine Semiconductor Corporation, a Response (in Japanese), dated Aug. 14, 2006, for related Japanese application No. 2003-535287, 6 pgs.
Miyajima, Ikumi, translation of Notice of Reasons for Refusal, dated Oct. 5, 2006 for related Japanese application No. 2003-535287, 4 pgs.
Peregrine Semiconductor Corporation, Response filed in the EPO, dated Dec. 23, 2008 for related application No. 02 800 982.7-2220, 22 pgs.
Pozar, “Microwave and RF Design of Wireless Systems”, Wiley, 2001.
Maas, “The RF and Microwave Circuit Design Cookbook”, Artech House, 1998.
Smith, “Modern Communication Systems”, McGraw-Hill, 1998.
Van Der Pujie, “Telecommunication Circuit Design”, Wiley, 2002.
Razavi, “RF Microelectronics”, Prentice-Hall, 1998.
Van Der Pujie, “Telecommunication Circuit Design”, Wiley, 1992.
Weisman, “The Essential Guide to RF and Wireless”, Prentice-Hall, 2000.
Wetzel, “Silicon-on-Sapphire Technology for Microwave Power Application”, University of California, San Diego, 2001.
Johnson, “Silicon-on-Sapphire Technology for Microwave Circuit Applications”, Dissertation, UCSD, 1997, pp. 1-184.
Le, Dinh Thanh, Office Action received from the USPTO dated Jun. 23, 2011 for related U.S. Appl. No. 12/803,064, 16 pgs.
Kao, W.H., et al., “Parasitic extraction: current state of the art and future trends”, Proceedings of the IEEE, May 2001, vol. 89, Issue 5, pp. 729-739.
Brambilla, A., et al., “Measurements and extractions of parasitic capacitances in ULSI layouts”, Electron Devices, IEEE Transactions, Nov. 2003, vol. 50, Iss 11, pp. 2236-2247.
Xu, et al., “An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution”, Circuits and Systems I: Regular papers, IEEE Transactions, Jun. 2004, vol. 51, Issue 6, pp. 1223-1233.
Nabors, et al., “FastCap: A Multipole Accelerated 3-D Capacitance Extraction Program”, IEEE Transactions on Computer-Aided Design, vol. 10, No. 11, Nov. 1991, pp. 1447-1459.
Nabors, et al., “Fast Capacitance Extraction of General Three-Dimensional Structures”, IEEE Transactions on Microwave Theory and Techniques, vol. 40, No. 7, Jul. 1992, pp. 1496-1506.
Nabors, et al., “Multipole-Accelerated Capacitance Extraction Algorithms for 3-D Structures with Multiple Dielectrics” IEEE Transactions on Circuits and Systems, 1: Fundamental Theory and Applications, vol. 39, No. 11, Nov. 1992, pp. 946-954.
Tausch, et al., “Capacitance Extraction of 3-D Conductor Systems in Dielectric Media with High-Permittivity Ratios”, IEEE Transactions on Microwave Theory and Techniques, vol. 47, No. 1, Jan. 1999, pp. 18-26.
Nabors, et al., “A Fast Multipole Algorithm for Capacitance Extraction of Complex 3-D Geometries”, IEEE 1989 Custom Integrated Circuits Conference May 1989, pp. 21.7.1-21.7.4.
Nabors, et al., “Fast Capacitance Extraction of General Three-Dimensional Structures”, Proc. Int. Conf. on Computer Design, Cambridge, MA, Oct. 1991, pp. 479-484.
Nabors, et al., “Including Conformal Dielectrics in Multipole-Accelerated Three-Dimensional Interconnect Capacitance Extraction” proceedings of NUPAD IV, Seattle, WA, May 1992, pp. 167-172.
Nabors, et al., Multipole-Accelerated 3-D Capacitance Extraction Algorithms for Structures with Conformal Dielectrics Proceeding of the 29th Design Automation Conference, Anaheim, CA, Jun. 1992, pp. 710-715.
Phillips, et al., “A Precorrected-FFT method for Capacitance Extraction of Complicated 3-D Structures” Int. Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 1994, 4 pages.
Phillips, et al., “Efficient Capacitance Extraction of 3D Structures Using Generalized Pre-Corrected FFT Methods”, Proceedings of the IEEE 3rd Topical Meeting on Electrical Performance of Electronic Packaging, Monterey, CA, Nov. 1994, 3 pages.
Cai, et al., Efficient Galerkin Techniques for Multipole-Accelerated Capacitance Extraction of 3-D Structures with Multiple Dielectrics Proceedings of the 16th Conference on Advanced Research in VLSI, Chapel Hill, North Carolina, Mar. 1995, 12 pages.
Kamon, et al., “FastPep: A Fast Parasitic Extraction Program for Complex Three-Dimensional Geometries”, Proceedings of the IEEE Conference on Computer-Aided Design, San Jose, Nov. 1997, pp. 456-460.
Englekirk, Robert, Preliminary Amendment filed in the USPTO dated Sep. 11, 2009 for related U.S. Appl. No. 11/796,522, 9 pgs.
Reema, Patel, Office Action received from the USPTO dated Oct. 2, 2009 for related U.S. Appl. No. 11/796,522, 6 pgs.
Englekirk, Robert, Response filed in the USPTO dated Nov. 2, 2009 for related U.S. Appl. No. 11/796,522, 3 pgs.
Shifrin, Mitchell, et al., “Monolithic FET Structures for High-Power Control Component Applications”, IEEE Transactions on Microwave Theory and Techniques, vol. 37, No. 12, Dec. 1989, pp. 2134-2141.
Shifrin, Mitchell, et al., “High Power Control Components Using a New Monolithic FET Structure”, IEEE 1989, Microwave and Millimeter-Wave Monolithic Circuits Symposium, pp. 51-56.
Volker, Simon, Communication from the European Patent Office for related appln. No. 09174085.2-1233 dated Dec. 3, 2009, 6 pgs.
European Patent Office, Communication Pursuant to Rules 161 and 162 EPC received for related appln. No. 07794407.2 dated Dec. 10, 2009, 2 pgs.
Volker, Simon, European Search Report received from the EPO for related appln. No. 07794407.2 dated Mar. 12, 2010, 8 pgs.
Reema, Patel, Office Action received from the USPTO dated Mar. 2, 2010 for related U.S. Appl. No. 11/796,522, 8 pgs.
Englekirk, Robert, Amendment filed in the USPTO dated Jun. 2, 2010 for related U.S. Appl. No. 11/796,522, 10 pgs.
Volker, Simon, Communication Pursuant to Article 94(3) EPC received from the EPO for related appln. No. 09174085.2 dated May 4, 2010, 1 pg.
Volker, Simon, Communication Pursuant to Article 94(3) EPC received from the EPO for related appln. No. 07794407.2 dated Jun. 15, 2010, 1 pg.
Englekirk, Robert, Response filed in the EPO for related application No. 07794407.2 dated Oct. 20, 2010, 13 pgs.
Englekirk, Robert, Response filed in the EPO for related application No. 09174085.2 dated Oct. 20 2010, 14 pgs.
Reema, Patel, Office Action received from the USPTO dated Aug. 30, 2010 for related U.S. Appl. No. 11/796,522, 15 pgs.
Englekirk, Robert, Amendment filed in the USPTO dated Dec. 30, 2010 for related U.S. Appl. No. 11/796,522, 12 pgs.
Patel, Reema, Notice of Allowance received from the USPTO dated Jan. 28, 2011 for related U.S. Appl. No. 11/796,522, 9 pgs.
Englekirk, Robert, Comments on Examiner's Statement of Reasons for Allowance filed in the USPTO dated Apr. 28, 2011 for related U.S. Appl. No. 11/796,522, 3 pgs.
Young, Lee W., International Search Report and Written Opinion received from the U.S. Receiving Office dated Feb. 15, 2008 for related appln. No. PCT/US2007/010331, 14 pgs.
Copenheaver, Brian, International Search Report and Written Opinion for related appln. No. PCT/US2009/001358 dated May 27, 2009, 11 pages.
Peregrine Semiconductor Corporation, Article 19 Amendment Letter Under Section 205(b) and Rule 46.5(b) PCT filed in WIPO for related appln. No. PCT/US2009/001358, dated Aug. 11, 2009, 12 pages.
Novak, Rodd, “Overcoming the RF Challenges of Multiband Mobile Handset Design”, RF/Microwave Switches and Connectors, published Jul. 20, 2007, www.rfdesign.com, 3 pgs.
Qiao, et al., “Antenna Impedance Mismatch Measurement and Correction for Adaptive CDMA Transceivers”, Published Jun. 12-17, 2005, by the IEEE in the 2005 Microwave Symposium Digest, 2005 IEEE MTT-S International, pp. 4, et seq.
Sjoblom, Peter, “An Adaptive Impedance Tuning CMOS Circuit for ISM 2.4-GHz Band”, Published in the IEEE Transactions on Circuits and Systems—1: Regular Papers, vol. 52, No. 6, pp. 1115-1124, Jun. 2005.
Sjoblom, Peter, “Measured CMOS Switched High-Quality Capacitors in a Reconfigurable Matching Network”, IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 54, No. 10, Oct. 2007, pp. 858-862.
Brosa, Anna-Marie, Extended European Search Report received from the EPO dated Jul. 15, 2011 for related appln. No. 09715932.1, 12 pgs.
Tombak, Ali, et al., “Cellular Antenna Switches for Multimode Applications Based on a Silicon-on-Insulator Technology”, 2010 IEEE Radio Frequency Integrated Circuits Symposium, RMO3D-5, pp. 271-274.
Wang, Dawn, et al., High Performance SOI RF Switches for Wireless Applications (Invited Paper), Apr. 2010 IEEE, 4 pgs.
Burgener, Mark L., “CMOS SOS Switches Offer Useful Features, High Integration”, Microwaves and RF, Aug. 2001, pp. 107-118.
Drozdovsky, et al., “Large Signal Modeling of Microwave Gallium Nitride Based HFETs”, Asia Pacific Microwave Conference, 2001, pp. 248-251.
Ayasli, “Microwave Switching with GaAs FETs”, Microwave Journal, 1982, pp. 719-723.
Eron, “Small and Large Signal Analysis of MESETs as Switches” Microwave Journal, 1992.
“A Voltage Regulator for GaAs FETs”, Microwave Journal, 1995.
Slobodnik, et al., “Millimeter Wave GaAs Switch FET Modeling”, Microwave Journal, 1989.
Madihian, et al., “A 2-V, 1-10GHz BiCMOS Transceiver Chip for Multimode Wireless Communications Networks”, IEEE, 1997, pp. 521-525.
Caverly, “Distortion in GaAs MESFET Switch Circuits”, 1994.
Chen, et al., “Dual-Gate GaAs FET: A Versatile Circuit Component for MMICs”, Microwave Journal, Jun. 1989, pp. 125-135.
Bullock, “Transceiver and System Design for Digital Communication”, Noble, 2000.
Crols, “CMOS Wireless Transceiver Design”, Kluwer Academic, 1997.
Hickman, “Practical RF Handbook”, Newnes, 1997.
Hagen, “Radio Frequency Electronics”, Cambridge University Press, 1996.
Kuo, “Low Voltage SOI CMOS VLSI Devices and Circuits”, John Wiley & Sons, Inc., 2001.
Leenaerts, “Circuits Design for RF Transceivers” Kluwer Academic, 2001.
Johnson, “Advanced High-Frequency Radio Communication”, Artech House, 1997.
Larson, “RF and Microwave Circuit Design for Wireless Communications”, Artech House, 1996.
Misra, “Radio Frequency and Microwave Communication Circuits”, Wiley, 2001.
Hiramoto, Toshiro, et al., “Low Power and Low Voltage MOSFETs with Variable Threshold Voltage Controlled by Back-Bias”, IEICE Trans. Electron, vol. E83-C, No. 2, Feb. 2000, pp. 161-169.
Su, Pin, et al., “On the Body-Source Built-In Potential Lowering of SOI MOSFETs”, IEEE Electron Device Letters, vol. 24, No. 2, Feb. 2003, pp. 90-92.
Yang, Min, “Sub-100nm Vertical MOSFET's with Si1-x-y GexCy Source/Drains”, a dissertation presented to the faculty of Princeton University, Jun. 2000, 272 pgs.
Ytterdal, T., et al., “MOSFET Device Physics and Operation”, Device Modeling for Analog and RF CMOS Circuit Design, 2003 John Wiley & Sons, Ltd., 46 pgs.
Cherne, et al., “SOI CMOS Device Having Body Extension for Providing Sidewall Channel Stop and Bodytie”, U.S. Statutory Invention Registration No. H1435, published May 2, 1995, 12 pgs.
Tieu, Binh Kien, Notice of Allowance received from the USPTO for related U.S. Appl. No. 12/315,395, dated Aug. 11, 2010, 26 pgs.
Tieu, Binh Kien, Supplemental Notice of Allowance received from the USPTO for related U.S. Appl. No. 12/315,395, dated Oct. 29, 2010, 10 pgs.
Kelly, et al., Comments on Examiner's Statement of Reasons for Allowance filed in the USPTO for related U.S. Appl. No. 11/347,014, dated Jul. 29, 2010, 2 pgs.
Raab, et al., “Power Amplifiers and Transmitters for RF and Microwave”, IEEE Transactions on Microwave Theory and Techniques, vol. 50, No. 3, pp. 814-826, Mar. 2002, USA.
Ueda, et al., “A 5GHz-Band On-Chip Matching CMOS MMIC Front-End”, 11th GAAS Symposium—Munich 2003, pp. 101-104, Germany.
Nelson Pass, Pass Labs, “Cascode Amp Design”, Audio Electronics, pp. 1-4, Mar. 1978.
Lester F. Eastman, P.I., “High Power, Broadband, Linear, Solid State Amplifier”, 16th Quarterly Rep. under MURI Contract No. N00014-96-1-1223 for period Jun. 1, 2000-Aug. 31, 2000, Sep. 2000.
Jeon, et al., “A New “Active” Predistorter with High Gain Using Cascode-FET Structures”, IEEE Radio Frequency Integrated Circuits Symposium, 2002, pp. 253-256.
Hsu, et al., “Comparison of Conventional and Thermally-Stable Cascode (TSC) AlGaAs/GaAs HBTs for Microwave Power Applications”, Jml of Solid-State Electronics, V. 43, Sep. 1999.
Kim, et al., “High-Performance V-Band Cascode HEMT Mixer and Downconverter Module”, IEEE Transactions on Microwave Theory and Techniques, vol. 51, No. 3, p. 805-810, Mar. 2003.
Peregrine Semiconductor Corporation, Response filed in the EPO, dated Oct. 7, 2009 for related application No. 02 800 982.7-2220, 23 pgs.
Theunissen, Lars, Communication under Rule 71(3) EPC received from the EPO dated Oct. 2, 2017, for appln. No. 14165804.7, 94 pgs.
Puentes, Daniel Calrissian, Office Action received from the USPTO dated Nov. 22, 2017 for U.S. Appl. No. 15/442,491, 19 pgs.
Dang, Hung Q., Office Action received from the USPTO dated Oct. 14, 2016 for U.S. Appl. No. 14/638,917, 19 pgs.
Patel, Reema, Notice of Allowance received from the USPTO dated Nov. 2, 2016 for U.S. Appl. No. 14/883,122, 14 pgs.
Ranta, et al., Response filed in the USPTO dated Nov. 7, 2016 for U.S. Appl. No. 14/814,404, 8 pgs.
Reedy, et al., Response filed in the USPTO dated Sep. 29, 2016 for U.S. Appl. No. 14/883,512, 16 pgs.
Reedy, et al., Response to Final Office filed in the USPTO dated Jun. 15, 2017 for U.S. Appl. No. 14/883,512, 15 pgs.
Willoughby, Terrence Ronique, Notice of Allowance received from the USPTO dated Jul. 26, 2017 for U.S. Appl. No. 14/883,512, 5 pgs.
Peregrine Semiconductor Corporation, Response filed in the USPTO dated Apr. 11, 2016 for U.S. Appl. No. 14/165,422, 5 pgs.
Puentes, Daniel Calrissian, Office Action received from the USPTO dated May 10, 2016 for U.S. Appl. No. 14/814,404, 8 pgs.
Patel, Reema, Office Action received from the USPTO dated Jun. 22, 2016 for U.S. Appl. No. 14/883,122, 8 pgs.
Le, Dinh Thanh, Notice of Allowance received from the USPTO dated Jun. 29, 2016 for U.S. Appl. No. 14/165,422, 24 pgs.
Willoughby, Terrence Ronique, Office Action received from the USPTO dated Jun. 29, 2016 for U.S. Appl. No. 14/883,512, 10 pgs.
Patel, Reema, Office Action received from the USPTO dated Aug. 15, 2014 for U.S. Appl. No. 14/028,357, 8 pgs.
Patel, Reema, Final Office Action received from the USPTO dated Apr. 7, 2015 for U.S. Appl. No. 14/028,357, 159 pgs.
Patel, Reema, Notice of Allowance received from the USPTO dated Jun. 25, 2015 for U.S. Appl. No. 14/028,357, 12 pgs.
Englekrik, Robert Mark, Response filed in the USPTO dated Dec. 15, 2014 for U.S. Appl. No. 14/028,357, 10 pgs.
Englekrik, Robert Mark, Response After Final Office Action filed in the USPTO dated Jun. 8, 2015 U.S. Appl. No. 14/028,357, 3 pgs.
Willoughby, Terrence Roniquie, Final Office Action received from the USPTO dated May 19, 2017 for U.S. Appl. No. 14/883,512, 38 pgs.
Brosa, Anna-Maria, Communication pursuant to Article 94(3) EPC received from the EPO dated Mar. 20, 2017 for appln. No. 14165804.7, 6 pgs.
Puentes, Daniel Calrissian, Notice of Allowance received from the USPTO dated May 3, 2017 for U.S. Appl. No. 14/814,404, 29 pgs.
Meulemans, et al., Communication under Rule 71(3) EPC received from the EPO dated Dec. 13, 2016 for appln. No. 07794407.2, 33 pgs.
Meulemans, et al., Communication under Rule 71(3) EPC received from the EPO dated Dec. 13, 2016 for appln. No. 09174085.2, 30 pgs.
Ranta, Tero Tapio, Response filed in the USPTO dated Jan. 16, 2017 for U.S. Appl. No. 14/638,917, 12 pgs.
Puentes, Daniel Calrissian, Office Action received from the USPTO dated Feb. 1, 2017 for U.S. Appl. No. 14/814,404, 13 pgs.
Dang, Hung, Notice of Allowance received from the USPTO dated Feb. 13, 2017 for U.S. Appl. No. 14/638,917, 13 pgs.
Ranta, et al., Response filed in the USPTO dated Feb. 24, 2017 for U.S. Appl. No. 14/814,404, 4 pgs.
Tadashige, Itoh, et al, Office Action and English translation received from the JPO dated Feb. 7, 2017 for appln. No. 2015-225020, 10 pgs.
Ichikawa, Takenori, Office Action and English translation received from the JPO dated Aug. 1, 2015 for appln. No. 2013-181032, 15 pgs.
Ranta, et al., Response filed in the USPTO dated Nov. 6, 2015 for U.S. Appl. No. 14/165,422, 2 pgs.
Wong, Alan, Notice of Allowance received from the USPTO dated Dec. 18, 2015 for U.S. Appl. No. 13/586,738, 21 pgs.
Le, Dinh Thanh, Office Action received from the USPTO dated Jan. 11, 2016 for U.S. Appl. No. 14/165,422, 47 pgs.
Henderson, Richard, Summons to Attend Oral Proceedings pursuant to Rule 115(1) received from the EPO dated Jun. 30, 2020 for appln. No. 18157696.8, 11 pgs.
Tieu, Binh Kien, Final Office Action received from the USPTO dated Jan. 17, 2006 for U.S. Appl. No. 10/922,135, 8 pgs.
Weman, Eva, Communication under Rule 71(3) EPC received from the EPO dated Nov. 27, 2009 for appln. No. 02800982.7, 68 pgs.
Aquilani, Dario, Communication and Supplementary European Search Report dated Nov. 27, 2009 for appln. No. 05763216, 10 pgs.
Ajjkuttira, et al., “A Fully Integrated CMOS RFIC for Bluetooth Applications”, IEEE International Solid-State Circuits Conference, 2001, pp. 1-3.
Apel, et al., “A GaAs MMIC Transceiver for 245 GHz Wireless Commercial Products”, Microwave and Millimeter-Wave Monolithic Circuits Symposium, 1994, pp. 15-18.
Assaderaghi, et al., “Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra Low Voltage VLSI”, IEEE Transactions on Electron Devices, vol. 44, No. 3, Mar. 1997, pp. 414-422.
Bolam, et al., “Reliability Issues for Silicon-on-Insulator”, IBM Micro Electronics Division, IEEE 2000, pp. 6.4.1-6.4.4.
Caverly, et al., “CMOS RF Circuits for Integrated Wireless Systems”, IEEE, 1998, pp. 1-4.
Chao, et al., “High-Voltage and High-Temperature Applications of DTMOS with Reverse Schottky Barrier on Substrate Contacts”, vol. 25, No. 2, Feb. 2004, pp. 86-88.
Devlin, et al., “A 2.4 GHz Single Chip Transceiver”, Microwave and Millimeter-Wave Monolithic Circuits Symposium, 1993, pp. 23-26.
Fiorenza, et al., “RF Power Performance of LDMOSFETs on SOI: An Experimental Comparison with Bulk Si MOSFETs”, IEEE Radio Frequency Integrated Circuits Symposium, 2001, pp. 43-46.
Giffard, et al., “Dynamic Effects in SOI MOSFETs”, IEEE SOS/SOI Technology Conference, Oct. 1991, pp. 160-161.
Imai, et al., “Novel High Isolation FET Switches”, IEEE Transactions on Microwave Theory and Techniques, 1996, pp. 685-691.
Ishida, et al., “A Low Power GaAs Front End IC with Current Reuse Configuration Using 0.15um Gate GaAs MODFETs”, IEEE, 1997, pp. 669-672.
Iwata, et al., “Gate Over Driving CMOS Architecture for 0.5V Single Power Supply Operated Devices”, IEEE, 1997, pp. 290-291, 473.
Kumar, et al., “A Simple High Performance Complementary TFSOI BiCMOS Technology with Excellent Cross-Talk Isolation”, 2000 IEEE International SOI Conference, 2000, pp. 142-143.
Kwok, “An X-Band SOS Resistive Gate Insulator Semiconductor (RIS) Switch”, IEEE Transactions on Electron Device, 1980, pp. 442-448.
Lee, et al. “Effect of Body Structure on Analog Performance of SOI NMOSFETs”, 1998 IEEE International SOI Conference, Oct. 1998, pp. 61-62.
Lee, “CMOS RF: (Still) No Longer an Oxymoron (Invited)”, IEEE Radio Frequency Integrated Circuits Symposium, 1999, pp. 3-6.
McRory, et al., “Transformer Coupled Stacked FET Power Amplifier”, IEEE Journal of Solid State Circuits, vol. 34, No. 2, Feb. 1999, pp. 157-161.
Nagayama, et al., “Low Insertion Los DP3T MMIC Switch for Dual Band Cellular Phones”, IEEE Jounral of Solid State Circuits, 1999, pp. 1051-1055.
Niishijima, et al., “A High Performance Transceiver Hybrid IC for PHS Hand Set Operating with Single Positive Voltage Supply”, Microwave Symposium Digest, 1997, pp. 1155-1158.
O, et al., “CMOS Components for 802.11b Wireless LAN Applications”, IEEE Radio Frequency Integrated Circuits Symposium, 2002, pp. 103-106.
Peczalski, “RF/Analog/Digital SOI Technology GPS Receivers and Other Systems on a Chip”, IEEE Aerospace Conference Proceedings, 2002, pp. 2013-2017.
Shifrin, et al., “A New Power Amplifier Topology with Series Biasing and Power Combining of Transistors”, IEEE 1992 Microwave and Millimeter-Wave Monolithic Circuits Symposium, 1992, pp. 39-41.
Shimura, et al., “High Isolation V-Band SPDT Switch MMIC for High Power Use”, IEEE MTT-S International Microwave Symposium Digest, 2001, pp. 245-248.
Uda, et al., “A High Performance and Miniturized Dual Use (antenna/local) GaAs SPDT Switch IC Operating at +3V/0V”, Microwave Symposium Digest, 1996, pp. 141-144.
Ranta, et al., Comments on Examiner's Statement of Reasons for Allowance filed in the PTO dated Sep. 10, 2012 for related U.S. Appl. No. 12/803,133, 3 pgs.
Ranta, et al., Amendment filed in the PTO dated Sep. 12, 2012 for related U.S. Appl. No. 12/803,064, 13 pgs.
Shimura, et al., “High Isolation V-Band SPDT Switch MMIC for High Power Use”, 2001 IEEE MTT-S Digest, pp. 245-248.
Lee, et al., “Analysis of Body Bias Effect with PD-SOI for Analog and RF Application”, Solid State Electron, vol. 46, 2002, pp. 1169-1176.
Ippoushi, “SOI Structure Avoids Increases in Chip Area and Parasitic Capacitance Enables Operational Control of Transistor Threshold Voltage”, Renesas Edge, vol. 2004.5, Jul. 2004, p. 15.
Hittite Microwave, Floating Ground SPNT MMIC Switch Driver Techniques, 2001.
Caverly, et al., “Gallium Nitride-Based Microwave and RF Control Devices”, 2001.
Sedra, et al., “Microelectronic Circuits”, University of Toronto, Oxford University Press, Fourth Edition, 1982,1987,1991,1998, pp. 374-375.
Bahl, “Lumped Elements for RF and Microwave Circuits”, Artech House, 2003, pp. 353-394.
“Positive Bias GaAs Multi-Throw Switches with Integrated TTL Decoders”, Hittite Microwave, 2000.
Park, Jooyoun, “A Regulated, Charge-Pump CMOS DC/DC Converter for Low-Power Applications”, Massachusetts Institute of Technology, Apr. 1, 2998, 62 pgs.
Barker, Communications Electronics-Systems, Circuits, and Devices, 1987, Prentice-Hall.
Carr, “Secrets of RF Circuit Design”, McGraw-Hill, 1997.
Couch, “Digital and Analog Communication Systems”, 2001, Prentice-Hall.
Couch, “Modern Telecommunication System”, Prentice-Hall, 1995.
Freeman, “Radio System Design for Telecommunications”, Wiley, 1997.
Related Publications (1)
Number Date Country
20200280312 A1 Sep 2020 US
Divisions (2)
Number Date Country
Parent 15829773 Dec 2017 US
Child 16813459 US
Parent 11796522 Apr 2007 US
Child 13046560 US
Continuations (4)
Number Date Country
Parent 15061909 Mar 2016 US
Child 15829773 US
Parent 14883122 Oct 2015 US
Child 15061909 US
Parent 14028357 Sep 2013 US
Child 14883122 US
Parent 13046560 Mar 2011 US
Child 14028357 US