Particular embodiments generally relate to digitally controlled oscillators (DCOs).
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A digitally controlled oscillator (DCO) is used in systems including an all-digital phase lock loop (DLL), frequency lock loop (FLL), or in DLLs that perform clock synthesis and data recovery. In one example, the DCO is used in the all-digital DLL to generate a radio frequency (RF) signal with a frequency proportional to a reference clock.
where fosc is the output signal of DCO 200 (or LC tank 202), Δ fosc is the frequency variation of the output signal, and ΔCtank is the variance of the tuning capacitance of tuning capacitor 208. For example, if a 2 kHz frequency resolution at 3.3 GHz is desired where the capacitance value of capacitor 206 is Ctank=4.5 pF and the inductance value of inductor 204 is L=500 pH, then tuning capacitor 208 has a tuning capacitance of ΔCtank=5 actoFarads (aF). ΔCtank may be the value of each capacitor in the capacitor bank. In this case, the tuning capacitance is a capacitance that is smaller than technology can implement effectively.
One solution for solving the problem of having a tuning capacitance that is too small to implement is to use dithering.
b shows a signal 404 output by a digital ΣΔ 408 of
In the implementation of
Dithering may lower the equivalent capacitance and allow larger capacitances to be used, but noise is increased from the 3 bit signal. The quantization noise is moved to higher frequencies where generally the noise-phase specifications are more challenging. Due to this problem, the frequency of dithering may be significantly increased.
In one embodiment, an apparatus includes a first circuit of a digitally controlled oscillator (DCO). The first circuit has a loss component. A second circuit is coupled to the first circuit and configured to transform a positive impedance into a negative impedance in series with a negative resistance. The negative impedance includes an adjustable reactive component used to adjust a frequency of an output signal of the DCO. An equivalent reactance seen by the first circuit is less than a reactance of the adjustable reactive component.
In one embodiment, wherein the reactive component comprises a matrix of varactors. A first set of varactors are coupled to a first reference voltage; a second set of varactors are coupled to a second reference voltage; and a variable varactor is coupled to a variable voltage signal.
In one embodiment, the second circuit comprises a cross coupled pair of transistors in series with the reactive component.
In one embodiment, a method includes receiving an error estimate of an output signal of a DCO. The error estimate is determined by comparing the output signal to a reference signal. The method further includes adjusting a reactance of a reactive component to adjust a frequency of the output signal based on the error estimate. An equivalent reactance seen by a tank circuit of the DCO is less than the reactance of the reactive component.
In one embodiment, the method coupling a first set of varactors to a first reference voltage; coupling a second set of varactors to a second reference voltage; and coupling a variable varactor to variable voltage signal.
In one embodiment, a system includes the apparatus. The DCO receives an input signal of an error estimation of an output signal of the DCO and a reference signal and adjusts the capacitance value of the capacitor based on the input signal.
The following detailed description and accompanying drawings provide a more detailed understanding of the nature and advantages of the present invention.
a shows an example of a DCO model using a dithering implementation.
b shows a signal output by a digital ΣΔ of
a shows an example of a DCO according to one embodiment.
b shows a graph of the DCO frequency vs. the capacitance C of a tuning capacitor according to one embodiment.
a shows an example of the tuning of capacitor according to one embodiment.
b shows an example of a varactor coupled to the voltage VDAC according to one embodiment.
c shows an example of capacitance values that are provided based on the value of the voltage VDAC.
Described herein are techniques for a DCO. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. Particular embodiments as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.
An impedance transformer 510 allows a capacitive variation (ΔCeq) seen by LC tank 202 to be lower than a capacitive variance of a capacitor (ΔC) 512. An equivalent capacitance ΔCeq may be:
where A is a shrinking factor. The shrinking factor may be an amount of capacitive reduction that is seen by LC tank 502. ΔCeq may be the resolution in capacitive tuning that can be used.
The term (ω0RC)2 is 1/Qf2. The transistors will be described below in an implementation of a DCO. R is the resistance of resistor 604 and C is the capacitance of capacitor 602. Qf is a shrinking factor of the negative capacitance in series with the negative resistance. In one example, the capacitance −C is reduced by a factor proportional to the square of a transistor transductance, which will be described below. The negative resistance (−R) used to compensate the losses of LC tank 202 does not change significantly in that:
−Req≈−R
Accordingly, the equivalent capacitance −Ceq depends on the value of the transductance gm. As will be described below, the value of the negative resistance −R depends on a cross-coupled pair of transistors that are coupled to LC tank 202. The impedance transformation depends on the transductance of the cross coupled pair of transistors.
a shows an example of a DCO 700 according to one embodiment. DCO 700 includes an LC tank 502, which includes inductor 504 and capacitor 506. Capacitor 506 may provide coarse tuning to account for process and temperature variations. A circuit for transforming a positive impedance into a negative impedance is provided. For example, the circuit includes a cross-coupled pair of transistors (M1 and M2) 702 and a tuning capacitor (C) 704. Cross-coupled pair of transistors 702 synthesize a negative resistance. Transistors M1 and M2 have their gates cross-coupled to the drains of each other. Also, the drains of transistors M1 and M2 are respectively coupled to LC tank 502. The sources of transistors M1 and M2 are coupled to a reactive component shown as tuning capacitor (C) 704. Tuning capacitor 704 provides the negative capacitance that is shown in series with the negative resistance in
Tuning capacitor 704 allows fine tuning of the frequency of an output signal output by LC tank 502 (or DCO 700).
For the capacitance value C>>gm/ω, then the following output signal is provided
For C>>gm/ω:
where gm is the transductance of transistors M1 and M2, L is the inductance of LC tank 502, and fosc is the output signal of LC tank 502. The capacitance C at the sources of transistors M1 and M2 is reflected in parallel to LC tank 502 and is reduced by a factor proportional to the square of the transductance of transistors M1 and M2. The capacitance C of tuning capacitor 704 at the sources of transistors M1 and M2 produces the same effect as a capacitor of a reduced capacitance in parallel to LC tank 502. The placing of the tuning capacitor 704 at the sources of transistors M1 and M2 also does not affect the intrinsic phase noise of DCO 700.
The value of the transductance gm required to sustain the oscillation of DCO 700 (and to synthesize the negative resistance) may make the value of the capacitance C large. Transistors M1 and M2 may be separated from the cross-coupled pair of transistors that synthesize the negative resistance to allow for the capacitance C to be selected independently.
In this implementation, tuning capacitor 704 is used along with a fixed capacitor (Cfixed) 802. The value of the capacitance Cfixed is adjusted by the capacitance C.
Current sources (I1) 706a are used to bias transistors M1 and M2. A current source (I2) 706b is used to bias transistors M3 and M4. By programming currents I1 and I2, the fine tuning range and resolution of capacitance can be tuned without changing the signal amplitude of the output signal for DCO 800.
The coarse tuning of capacitor Ctank 506 is used to compensate for processing temperature variations and to select a channel for the output signal DCO 800. Coarse tuning may use 8 bits denoted as c0-c7.
The fine tuning may have a 13-bit resolution represented by b0-b12. The bits are used to configure a capacitor bank.
A matrix of capacitors are used for tuning the capacitance. In one embodiment, a matrix 900 of varactors are used. A varactor may be a type of diode that has a variable capacitance that is a function of the voltage impressed on its terminals. Matrix 900 of varactors are coupled to a row decoder 902, a column decoder 904, and a digital-to-analog (DAC) converter 906.
Row decoder 902 receives bits b9-b12, column decoder 904 receives bits b5-b8, and DAC 906 receives bits b0-b4. Depending on bits b0-b12, different values of capacitance may be provided. For example, a varactor may be coupled to a supply voltage (Vdd), ground (Gnd), or a voltage VDAC. The varactors are toggled in and out to determine a total capacitance. For example, varactors coupled to the supply voltage are turned on and varactors coupled to ground are turned off. Also, the varactor coupled to the voltage VDAC is also turned on. The varactors coupled to the supply voltage provide a fixed amount of capacitance and the varactor coupled to the voltage VDAC has a variable capacitance.
b shows an example of a varactor 908 coupled to the voltage VDAC according to one embodiment. As shown, the varactor may be coupled to ground, supply voltage VDD, or voltage VDAC. When varactor 908 is coupled to voltage VDAC, different values of capacitance are provided depending on the value of the voltage VDAC. For example,
For 5 bits, 32 quantization levels are provided. As shown, the values of the capacitance (Cvaractor) may vary from 4fF to 12fF. Using this varying capacitance, fewer varactors may be needed to achieve a 13-bit resolution of capacitance for tuning capacitor 704. For example, if a 13-bit resolution is needed, 1313 varactors are needed to achieve this resolution. However, using a matrix of 256 varactors, the 13-bit resolution can be achieved using a variable capacitance provided by varactor 908. Less area on a chip is used and routing is also simplified.
The coarse tuning of capacitor 506 may also use a structure similar to matrix 900. However, the matrix may be smaller to due to the 8-bit resolution. The 3 least significant bits of the matrix used in the coarse-tuning array may be substituted with a varactor able to be tuned to different capacitances using a voltage VDAC as described in
At 1006, an error estimate of the output signal of DCO 700 as compared to a reference clock frequency is determined. At 1008, the capacitance C of capacitor 704 is adjusted to adjust the frequency of the output signal of DCO 700 based on the error estimation.
As used in the description herein and throughout the claims that follow, “a”, “an”, and “the” includes plural references unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents may be employed without departing from the scope of the invention as defined by the claims.
The present disclosure claims priority to U.S. Provisional App. No. 61/266,063 for “Very High Resolution Tuning Circuit for LC Tank Digitally Controlled Oscillators” filed Dec. 2, 2009, which is incorporated herein by reference in its entirety for all purposes.
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Number | Date | Country | |
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61266063 | Dec 2009 | US |