1. The Field of the Invention
This application relates to optical receivers and, more particularly, for receivers including electronic dispersion compensation.
2. The Relevant Technology
In an electronic dispersion compensating (EDC) system, signals are received over a transmission channel, such as an optical fiber, from a transmitter. Optical signals are converted to electrical signals, such as by means of a photodiode. The electrical signals are supplied to an analog front end (AFE) of the EDC, which typically includes a clock recovery unit (CRU), a variable gain amplifier (VGA), and an analog to digital converter (ADC). The VGA both amplifies and applies a bias to the electrical signal prior to sampling by the ADC. The clock recovery unit detects bit transitions in the electrical signal in order to generate a clock signal in phase with the received signal. The ADC samples the electrical signal at a time offset relative to the recovered clock signal in order to generate a sampled signal. Each sample typically includes a multi-bit value, such as four, eight, or sixteen bits.
The samples are supplied to a maximum likelihood sequence estimator (MLSE) which examines a sequence of samples simultaneously to decode the information encoded in the transmitted signal. Multiple samples are examined simultaneously to enable equalization of intersymbol interference (ISI) caused by pulse spreading during transmission.
In some MLSEs, such as the MLSE disclosed in U.S. patent application Ser. No. 11/736,515, filed Apr. 17, 2007, which is incorporated herein by reference, a channel estimator is used to model the channel over which the signal is transmitted. More specifically, the channel estimator models intersymbol interference experienced by the transmitted signal. Accordingly, the channel estimator will output for a given multi bit sequence, an expected sampled value for a given bit in that sequence. For example, for the bit sequence 010, the model of the transmission channel may predict a sampled value of 14 (b1110), for the second bit of the bit sequence.
The channel estimates for some or all possible combinations of the multi bit sequence, e.g. 000, 001, 010 . . . , for a three bit sequence, are compared to the sampled values. The MLSE chooses a series of bit sequences such that a combined error metric of a sequence of sampled values relative to the estimates corresponding to the chosen series of bit sequences is at a minimum relative to other possible series of bit sequences. The series of bit sequences are decoded to yield a data word.
In a typical receiver system, the EDC may not receive information regarding the bit error rate (BER) of the decoded data relative to the originally transmitted data. Transmitted data may include parity bits that are analyzed to determine whether data has been correctly decoded. However, because the EDC does not receive this information it is not able to tune its operation such that the BER is reduced.
In view of the foregoing, it would be an advancement in the art to provide a system and method for reducing the BER of a received signal by tuning an EDC without providing the actual BER to the EDC.
In one aspect of the invention, a data signal is transmitted over a channel to generate a distorted signal. The distorted signal is received and conditioned according to signal conditioning parameters and sampled according to at least one sampling parameter. The samples are then decoded by comparing them to expected values determined according to a model of the channel. The expected values are also compared to the sampled values in order to update the model of the channel. Updating of the model causes the expected values to vary over time. The variation of the expected values over time is calculated. The variation and mean of the expected values are used to calculate a simulated bit error rate (BER). One or both of the signal conditioning parameters and the sampling parameter are adjusted such that the simulated BER is reduced.
In another aspect of the invention, the signal conditioning parameters include a gain and a bias applied to a received signal and the sampling parameter is an offset time relative to a clock signal recovered from the received signal.
In another aspect of the invention, the bias and gain are adjusted until the simulated BER reaches a first end condition. The gain is then adjusted until the mean of the estimates reaches a second end condition corresponding to the length of the transmission channel.
In another aspect of the invention, values for the bias and gain are selected according to a numerical method such as the Nelder-Mead algorithm such that over time the simulated BER is reduced.
In another aspect of the invention, decoding the sampled values includes comparing a sequence of sampled values to the expected value and selecting a sequence of expected values such that a combined error metric of the sequence of sampled values relative to the sequence of expected values satisfies an error threshold.
In another aspect of the invention, the sampled values are decoded according to a version of the Viterbi algorithm. For example, a parallel, time-reversed, sliding window Viterbi decoding algorithm may be used.
These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.
To further clarify the above and other advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:
Referring to
Most optical transmission channels 14 are somewhat dispersive, which causes data symbols encoded in the transmitted signal to broaden during transmission and interfere with one another, an artifact known as intersymbol interference (ISI). An electronic dispersion compensator (EDC) 18 may be used to reconstruct a transmitted signal from a highly dispersion-distorted received signal according to a model of the transmission channel 14. In some embodiments of the present invention, the EDC 18 is embodied as the system disclosed in U.S. patent application Ser. No. 11/736,515, filed Apr. 17, 2007.
The EDC 18 may include an analog front end (AFE) 20 that conditions an analog output from the receiver 16 and converts that analog output of the receiver 16 to digital signal. For example, the AFE 20 may amplify and/or bias the received signal prior to sampling the received signal.
The AFE 20 produces a digital output that is provided to a decoder 22. The decoder 22 also receives estimates from a model 24 of the transmission channel 14. The model 24 generates estimates of the output of the AFE 20 for a given originally transmitted sequence of bits. The model 24 preferably outputs estimates corresponding to multi-bit sequences such that the estimates reflect an estimate of intersymbol interference that occurs during transmission. The decoder compares the estimates to the actual output of the AFE 10 and selects a series of bit sequences having corresponding estimates that best approximate the actual outputs from the AFE. This selected series of bit sequences is then translated into an output representing an estimate of the originally transmitted data.
The model 24 is updated periodically by comparing the estimates to the actual AFE observations. The BER at the output of the decoder can be strongly affected by the AFE parameters. A quality of transmission (QoT) module 26 measures the estimates over time and calculates a simulated BER based on the mean and variation associated with each estimate. The QoT module 26 adjusts parameters within the AFE 20 such that the simulated BER is reduced. Experiments conducted by the inventor have shown that the simulated BER corresponds closely to the actual BER of the system 10.
Referring to
At step 34, the received signal is conditioned according to signal conditioning parameters. For example the received signal may be biased and/or amplified. At step 36 the conditioned signal is sampled to generate a series of sampled values. The sampled values are typically multi-bit values such as four, eight, or sixteen bits. The sampling step may include detecting bit transitions in the conditioned signal and sampling the conditioned signal a given offset time after each bit transition.
At step 38, the sampled values are compared to estimated observations calculated according to a model of the transmission channel. Each of the estimates represents an expected sampled value for a specific bit in a specific transmitted bit sequence. For example, one estimate for the middle bit of a transmitted sequence 101 may be 5 whereas the estimate for the middle bit of the sequence 000 may be 2. In some embodiments, a sequence of multiple sampled values is compared to the estimates at step 38. At step 40, a series of bit sequences is selected such that the aggregate error of a series of sampled values relative to the estimates corresponding to the series of bit sequences is below a threshold error or at a minimum relative to other possible series of bit sequences as constrained by a selection algorithm. The selected series of bit sequences represents the reconstructed data signal. Step 40 may include outputting a specific bit from one or more of the selected bit sequences.
At step 42, the channel model is updated according to a comparison of the estimates corresponding to the selected bit sequences and the actual sampled values. In this manner, the channel estimates generated by the channel model may be tuned to correspond to actual operating conditions of the system 10. In some embodiments, step 42 is not performed for every iteration of the method 28, but rather is performed only during certain iterations.
Referring to
At step 50, the variation calculated at step 48 is evaluated relative to an end condition. The end condition may be a threshold value. The end condition may also be a minimum change relative to one or more values calculated at step 48 for previous iterations of the method 46, indicating that the variation is converging on a minimum value. If the end condition is reached the method 46 may end. Alternatively, the method 46 may return to step 48 in order to continuously monitor and reduce the variation.
If the end condition is not reached, step 52 may be performed, wherein AFE settings such as signal conditioning and sampling parameters are chosen in order to reduce the variation. The signal conditioning parameters may include, for example, the gain and/or bias applied to the received signal. A sampling parameter may include an offset time relative to a recovered clock signal at which the received signal is sampled. The values for the signal conditioning parameters and offset time may be chosen according to a numerical method. For example, a plurality of data points may be generated, each including a calculation of variation and the gain, bias, and/or offset time settings that were being used when the estimates on which the variation is based were generated. The data points are processed according to a numerical minimization method, such as the Nelder-Mead algorithm, to select values at step 52 for the next iteration of the method 46 with the objective of minimizing the parameters representing the QoT of the system 10 calculated at step 48. At step 54 the AFE settings are adjusted according to the values selected at step 52.
With respect to the method 46, the parameters adjusted to improve the QoT of the system 10 may include one or more of the bias, gain, and offset time. In some embodiments, all three parameters are adjusted simultaneously. In other embodiments, only one parameter is adjusted until an end condition is reached, followed by the next parameter. In a preferred embodiment, the bias and gain are adjusted simultaneously until an end condition is reached and the offset time is then adjusted singly until another end condition is reached. In another preferred embodiment, the bias and gain are adjusted simultaneously until an end condition is reached, the gain is then adjusted singly until a second end condition is reached. The second end condition may include having the mean of the channel estimates be greater than or equal to a threshold value.
Referring to
The ADC 60 includes a clock recovery unit (CRU) 66 or clock data recovery (CDR) circuit 66. The CRU 66 detects bit transitions in the received signal and outputs a clock signal corresponding to the bit transitions. The ADC 60 samples the received signal in synchronization with the recovered clock signal to generate sampled values. The ADC 60 may include an adjustable offset time 68 that dictates a time following a rising or falling edge of the clock signal at which the ADC 60 will sample the received signal.
In some embodiments, the EDC 18 includes a decoder 22 and model 24 embodied as a maximum likelihood sequence estimator (MLSE) 70. The MLSE 70 may be embodied as the MLSE disclosed in U.S. patent application Ser. No. 11/736,515, filed Apr. 17, 2007, which discloses an MLSE performing a parallel, time reversed, sliding window Viterbi algorithm to decode a received signal. Other decoding schemes, particularly those using convolution codes, such as other versions of the Viterbi algorithm, may be used.
The MLSE 70 includes a channel estimator 72 that outputs estimates corresponding to the expected outputs of the ADC 60 for a given bit in a given bit sequence. For example, the channel estimator 72 may output an expected value for each possible value of an N-bit sequence. The channel estimator 72 will therefore output 2N estimates or eight estimates for N=3.
The channel estimator may include channel parameters 74 used to model the channel. For example, in one embodiment, the channel parameters are weights w0, w1 . . . wk multiplied by the bits, or combinations of bits, in the N-bit sequence. The weights may be applied to each possible bit sequence to yield estimates accounting, at least in part, for intersymbol interference. For example, for a three bit sequence [d0, d1, d2], an estimate may be equal to the following: w0 d0+w1 d1+w2 d2+w3 d0 d1+w4 d0 d2+w5 d1 d2+w6.
The channel estimates are input to a decoder 76. The decoder 76 analyzes M sample sequences with respect to the 2N estimates to decode P bits of data. For example, the decoder 76 may have a 12 bit look-ahead such that 12 samples are analyzed for every one or two output bits.
The decoder 76 may decode the sampled values by comparing a sequence of sampled values to the 2N estimates and selecting the a series of N bit sequences for which an aggregate error of the estimates corresponding to the selected series of N-bit sequences with respect to the sampled values is at or near a minimum. The selected series of N bit sequences are then mapped to specific data symbols and the data symbols are output by the decoder 76 to an output port 79. For example, a sample value equal to 14 may be mapped to the estimate for 010 based on a comparison of the sample value and a number of preceding or succeeding samples with the channel estimates. The decoder will therefore output a binary 1 for this sample value in embodiments where the estimates correspond to the expected sampled value for the second bit of a three bit sequence. Various methods known in the art may be used to accomplish the functionality of the decoder 76, including various convolution code decoding schemes such as the Viterbi algorithm and the methods disclosed in U.S. patent application Ser. No. 11/736,515.
The channel estimator 72 includes a channel updating module 78 that receives the selected estimates, or decoded data symbols, and the actual sampled values. The channel updating module 76 compares estimates selected by the decoder 76 to the actual sampled values for which the estimates were selected and updates the channel parameters such that the estimates will adapt to the actual sampled values. For example, if the decoder selects the estimate for bit sequence 101 for the sampled value of 6, then the channel parameters 74 may be updated such that the estimate for 101 will be closer to 6 in following iterations. Updating of the channel parameters may be accomplished by adjusting the weights w0, w1 . . . wk such that the estimates conform more closely to the actual sampled values.
The channel estimates generated by the channel estimator 72 may be provided to the QoT module 26. The QoT module maintains histograms 80 corresponding to each possible combination of an N-bit sequence. For example, in embodiments where each estimate corresponds to a three bit sequence, eight histograms may be stored, one for each combination of a three bit sequence (000, 001, 010, 011, 100, 101, 110, 111). Inasmuch as the channel parameters are updated during operation of the MLSE 70, the estimates for each state of the N-bit sequence will vary with time. Each histogram will therefore reflect this variation. In some embodiments, the histograms 80 include a number of stored estimates for each state of the N-bit sequence. In other embodiments, the histograms 80 include a mean and a variance stored for each state. In some embodiments, the histograms 80 are stored by the channel estimator 72 itself and accessed by the QoT module 20.
The QoT module includes a simulated bit error rate (BER) module 82. The simulated BER module 82 calculates a simulated BER corresponding to the variation in the channel estimates over time. Large variations indicate the likelihood of a higher bit error rate inasmuch as the histograms for the estimates are more likely to overlap one another, resulting in an increased likelihood of incorrect decoding of sampled values.
The simulated BER is input to an AFE coordinate selection module 84. The AFE coordinate selection module 84 selects values for one or more of the gain 62, bias 64, and offset time 68 such that the simulated BER is reduced. The AFE coordinate selection module selects the coordinates according to a numerical minimization method. For example, a plurality of data points may be generated, each including a simulated BER and the gain, bias, and/or offset time settings that were being used when the estimates on which the simulated BER is based were generated. The data points are processed according to a numerical minimization method by the AFE coordinate selection module, such as the Nelder-Mead algorithm, to select future values for one or more of the gain 62, bias 64, and offset time 68 such that the simulated BER is reduced.
The selected coordinates are then input to the AFE 20 to change the values of one or more of the gain 62, bias 64, and offset time 68. In some embodiments, the AFE 20 permits only analog adjustment of the gain 62, bias 64, or offset time 68. In such embodiments, these parameters are input to the AFE 20 by means of a digital to analog converter (DAC) 86.
Referring to
At step 102, 2N channel estimates {circumflex over (r)}0 . . . {circumflex over (r)}k . . . {circumflex over (r)}2
At step 104, each sample in a sequence of M samples r0 . . . rj . . . rM−1 is compared to all of the channel estimates {circumflex over (r)}0 . . . {circumflex over (r)}k . . . {circumflex over (r)}2
At step 106, a series of M N-bit sequences b0 . . . bj . . . bM−1 is selected for the samples r0 . . . rj . . . rM−1 such that an aggregation of the errors of the samples r0 . . . rj . . . rM−1 relative to estimates {circumflex over (r)}0 . . . {circumflex over (r)}k . . . {circumflex over (r)}2
At step 108, an M-bit decoded word {circumflex over (d)}0 . . . {circumflex over (d)}j . . . {circumflex over (d)}M−1 is output based on the M N-bit sequences selected at step 106. For example, each bit {circumflex over (d)}j of the output word may be chosen to be the i-th bit of the selected N-bit sequence bj.
At step 110, some or all of the estimates {circumflex over (r)}k,j corresponding to the selected N-bit sequences are compared to the corresponding sample rj of the M sample sequence for which the series of M N-bit sequences were selected at step 106.
At step 112, the channel parameters are updated according to the comparison at step 110 such that the channel estimator 72 will subsequently output estimates {circumflex over (r)}k,j closer to the value rj, for example. At step 114, the histogram for each estimate index k is updated to include the observed sample rj for the current iteration of the method 106.
Referring to
In some embodiments, the simulated BER accounts for the look-ahead of the MLSE 70. For example, where the MLSE has a look-ahead of M samples, the simulated BER may be based on the likelihood of overlap between sequences of M-N+1 estimates, where N is the length of the N-bit sequences for which the estimates are calculated.
Referring to
For each estimate index vector {right arrow over (y)} an estimate mean vector {right arrow over (h)}=
The noise vectors {right arrow over (λ)} and mean vector {right arrow over (h)} for each M-bit vector {right arrow over (w)} may be used to determine a simulated BER with respect to one or more M-bit vectors {right arrow over (w)} having adjacent mean vectors {right arrow over (h)} in Euclidean space. In a preferred embodiment, a simulated BER is only calculated for the closest of one to four mean vectors {right arrow over (h)}. In a preferred embodiment, only the two closest mean vectors are used.
The simulated BER of an M-bit vector {right arrow over (w)}a with respect to another M-bit vector {right arrow over (w)}b may be calculated by first calculating a unit vector
and a Euclidean distance between the mean vectors {right arrow over (h)}a and {right arrow over (h)}b according to the equation da→b=√{square root over (Σi=0M−N(hb,i−ha,i)2)}. A noise standard deviation σa→b from {right arrow over (w)}a to {right arrow over (w)}b may then be calculated according to the equation σa→b=√{square root over ({right arrow over (u)}a→bT{right arrow over (λ)}a{right arrow over (u)}a→b)}, where {right arrow over (λ)}a is the noise vector for M-bit vector {right arrow over (w)}a. The simulated BER may be calculated according to the equation
In some embodiments, σa→b may be normalized according to the equation
where {right arrow over (r)}max is the largest of the estimates. In other embodiments, the estimates {circumflex over (r)}0 . . . {circumflex over (r)}k . . . {circumflex over (r)}2
In some embodiments, the simulated BER for an M-bit vector {right arrow over (w)}a with respect to another M-bit vector {right arrow over (w)}b may be calculated in a way that takes into account unequal noise distributions for the vectors {right arrow over (w)}a and {right arrow over (w)}b in order to more accurately measure overlap between the noise distributions. In such embodiments, the simulated BER may be calculated to be equal to
where x is a point of intersection calculated according to the equation:
As noted above, in some embodiments, the MLSE 70 is constrained such that the first two bits {right arrow over (d)}0 and {right arrow over (d)}1 in each series are equal to the most recently decoded bits {right arrow over (d)}M−2 and {right arrow over (d)}M−1 selected in a previous iteration of the estimate selection step 106 of the method 88 shown in
In some embodiments, a simulated BER is only calculated for each M-bit vector {right arrow over (w)}a with respect to two M-bit vectors {right arrow over (w)}b and {right arrow over (w)}c, wherein {right arrow over (w)}b has the closest mean vector {right arrow over (h)}b of all M-bit vectors satisfying the relation wa,
In still other embodiments, an aggregate BER is calculated with reference to the histograms alone, without reference to particular M-bit vectors {right arrow over (w)}a and {right arrow over (w)}b. For example, a histogram divergence may be calculated for some or all of the histograms corresponding to the estimates {circumflex over (r)}0 . . . {circumflex over (r)}k . . . {circumflex over (r)}2
where B is the number of possible ADC values, e.g. 0 to 15 for a four bit ADC, and Pk(x) and Qk(x) represent the frequency of ADC value x in a histogram of estimates {circumflex over (r)}k for index k.
Referring again to
If not, then AFE coordinates are selected at step 124. As noted above, the AFE coordinates include one or more of the bias 64, gain 62, and offset time 68 of the AFE 20 and are selected according to a numerical method such that over multiple iterations the aggregate simulated BER will converge on a minimum value. In some embodiments, the AFE coordinates are first selected in order to sweep the entire coordinate space. For example, both the gain 62 and the bias 64 may be adjusted by a step size for each iteration in order to obtain an aggregate simulated BER for a grid of bias and gain values. Following sweeping the coordinate space, the AFE coordinates at which the aggregate simulated BER was at a minimum may be used as a first seed point for performing the Nelder-Mead algorithm. The Nelder-Mead algorithm requires N+1 seed points when adjusting N variables. The second seed point may be obtained by adding the step size to the gain and the third seed point may be obtained by adding the step size to the bias. Subsequent AFE coordinates may then be selected according to the Nelder-Mead algorithm as known in the art. In some embodiments, the value for the offset time 68 is adjusted separately following selection of values for the gain 62 and bias 64.
At step 126, channel estimates are accumulated. Step 126 may include waiting for a specific period time, for a specific number of sampled values to be received, or for some other event to occur. If the end condition is reached at step 122, the method 116 may end. In other embodiments, the method 116 goes to step 126 to accumulate more channel estimates without adjusting the AFE coordinates when the end condition is reached.
Referring to
Accordingly, in the method of
Referring to
In accordance with the foregoing, the method 140 of
The simulated BER for a truncated pair may be calculated as in the above described embodiments. For example, the vectors {right arrow over (w)}a and {right arrow over (w)}b of each pair may be decomposed into estimate index vectors {right arrow over (y)}a and {right arrow over (y)}b, respectively, wherein each element yi of each index vector is equal to wi . . . wi+N−1 of its corresponding truncated vector {right arrow over (w)}a, {right arrow over (w)}b. For the estimate index vectors {right arrow over (y)}a and {right arrow over (y)}b estimate mean vectors {right arrow over (h)}a and {right arrow over (h)}b are calculated where {right arrow over (b)}=
The simulated BER of truncated vector pair {right arrow over (w)}a, {right arrow over (w)}b may be set equal to
In some embodiments the MLSE 70 is programmed or otherwise configured to make l bit decisions at a time. For example, the MLSE disclosed in U.S. patent application Ser. No. 11/736,515 includes embodiments wherein two bits are decided at a time. Where l bit decisions are made at a time, the simulated BER may be calculated according to which of the l bit decisions is most likely to result in an error, based on the abovenoted assumption that only one bit error will occur for each decision of the MLSE.
Referring to
As shown in
Referring again to
If the end condition is reached then the process 140 may end. In some embodiments, if the end condition is reached, then steps 128-134 of the method illustrated in
If the end condition is found not to have been achieved at step 148, then AFE coordinates are selected at step 150 and channel estimates are accumulated at step 152 preparatory to another iteration of the method 140.
The method of
Referring to
The Viterbi algorithm may be visualized using a trellis having nodes 154 representing state transitions and edges 156 extending between nodes of the trellis representing possible sequences of transitions. In the illustrated embodiments, the state transitions include four possible bit transitions 00, 01, 10, and 11. The trellis includes a number of stages with each stage including four nodes representing the four possible bit transitions. Each node of each stage has two edges emanating therefrom to two nodes of a subsequent stage representing the two possible bit transitions that may follow the bit transition of that node. For example, a node 00 is connected to two edges to nodes 00 and 01 of a subsequent stage inasmuch as these are the only possible bit transitions following a 00 bit transition.
In some embodiments, a given vector {right arrow over (w)}a is associated with a path 158 spanning the trellis by mapping the bit transitions of the vector {right arrow over (w)}a to edges of the trellis. In the illustrated example, the vector {right arrow over (w)}a=01101100 is associated with a path intersecting node 01 of the first stage, node 11 of the second stage, node 10 of the third stage, and so on until node 00 of the seventh stage.
Referring to
At step 164, edges extending from the second stage to the third stage are removed that correspond to bit sequences having both third and fourth bits (B2 and B3) that are identical to bits B2 and B3 of the vector {right arrow over (w)}a. In some MLSEs, such as may be used in accordance with the invention, only the third and fourth bits represent actual bit decisions that are output and therefore can result in bit errors. The remaining bits of the vector represent the look-ahead of the MLSE, which is to say the additional samples that are used to decode the samples corresponding to the third and fourth bits. Accordingly, in some embodiments, only edges between the first and second stage that correspond to bit sequences for which one or both of the third and fourth bits are different correspond to possible errors. In embodiments where l bit decisions are made at a time, with l being a number that may be other than two, step 164 may include removing edges between the second stage and stage I+1 that do not lie on a path for which at least one of bits B2 through Bl+1 are different from the corresponding bit of the vector {right arrow over (w)}a.
In some embodiments, for l>N−1, the algorithm may be simplified by using a trellis having a first stage with 2l states. In this manner, evaluating which paths satisfy the constraint that one of bits B2 through Bl+1 be different from {right arrow over (w)}a can be evaluated by examining paths up to the nodes of the third stage. Where a trellis having only 2N−1 states per stage is used, multiple stages (l) must be examined before some edges may be removed to ensure that only paths not satisfying the constraint are removed. For example for the example vector of 01101100 and l=3, bit sequences that are described by identical paths through the trellis for stages two and three (0110) but are different at stage four (01100) will satisfy the constraint. Therefore, edges that fail to satisfy this constraint may not be removed until stages two through four have been evaluated.
At step 166, edges that lie only on paths that do not span the entire trellis are removed. Inasmuch as some edges are removed at steps 162 and 164, some of the nodes in following stages do not have any edges extending to them from the previous stage. Any paths including these nodes do not satisfy the constraints imposed by the algorithm and therefore any edges emanating from nodes for which all edges from the previous stage connecting to that node have been removed do not span the trellis and are therefore removed at step 166. Step 166 may be repeated for each stage, such as prior to executing step 172.
Referring to
At step 172, an accumulated error metric (AEM) is calculated for all remaining paths up to and including the nodes of the next stage of the trellis. The first time step 172 is executed for a vector {right arrow over (w)}a, the next stage is the stage following the initial stage and the l stages that are constrained to include at least one transition that is not identical to the vector path Pa corresponding to the vector {right arrow over (w)}a.
Step 172 is executed for each stage of the trellis following the one or more initial stages that are constrained to be the same as the vector {right arrow over (w)}a. For each subsequent iteration of the step 172 during processing of the same vector {right arrow over (w)}a, the next stage is the stage following the stage used in the previous iteration of the step 172.
For a given stage F, the AEM is equal to the Euclidean distance between a mean vector corresponding to a bit vector {right arrow over (C)}a equal to bits 0 through F of {right arrow over (w)}a and mean vectors corresponding to bit vectors {right arrow over (C)}b of length F+1 corresponding to the bit transitions of remaining paths up to and including the nodes of stage F. Remaining paths are those the edges of which are not removed during execution of the method 160.
As in other methods described hereinabove, the mean vectors are calculated by first decomposing the vector {right arrow over (C)}a and one of the vectors {right arrow over (C)}b into estimate index vectors {right arrow over (y)}a and {right arrow over (y)}b, respectively, wherein each element yi of each index vector is equal Ci . . . Ci+N−1 of its corresponding vector {right arrow over (C)}a, {right arrow over (C)}b. For the estimate index vectors {right arrow over (y)}a and {right arrow over (y)}b estimate mean vectors {right arrow over (h)}a and {right arrow over (h)}b are calculated where {right arrow over (h)}=
The AEM of a remaining path may be calculated according to the equation AEM=√{square root over (Σi=0N−1(hb,i−ha,i)2)}. In other embodiments, the AEM is calculated according to the equation AEM=ρi=0N−1(hb,i−ha,i)2. In this manner the AEM at each stage is equal to the AEM of paths up to the previous stage plus a single additional term equal to (hb,F−ha,F)2.
At step 174, the AEMs calculated at step 172 for stage F are compared to the AEM for the remaining path PF that intersects the same node of stage F that intersects the path Pa corresponding to the vector {right arrow over (w)}a. Any edges lying only on paths having an AEM higher than the path PF are removed. At step 176, edges emanating from the node of stage F that intersects the path Pa are removed. Step 176 includes removing edges that extend from the nodes of the stage F to the stage F+1. Preceding portions of remaining paths path (i.e. stages 1 through F−1) are not removed at step 176 inasmuch as they are still possible minimum paths.
Steps 174 and 176 rely on the observation that for a path Pa corresponding to vector {right arrow over (w)}a and a path Pk that intersects Pa at the kth stage, the minimal extension of the path Pk and the corresponding distance is known: it is the path that coincides with Pa for the remainder of the trellis. Hence, it is not necessary to extend this path in subsequent iterations of the Viterbi algorithm. Furthermore, any path whose accumulated distance metric at an intermediate stage of the trellis is larger than that of a path that intersects Pa can be disregarded, i.e., no longer extended, since such a path clearly cannot be of minimum distance.
Referring to
At step 184, the method 160 includes evaluating whether any non-intersecting paths remain. If so, then the method 160 includes evaluating whether the stage F is the last stage of the trellis at step 186. If the last stage has not been reached and non-intersecting paths remain, then any edges that lie on paths that do not span the entire trellis are removed according to step 166 for stage F and step 172 is then repeated for the next stage of the trellis, i.e. F=F+1.
If no non intersecting paths remain or the current stage is the last stage in the trellis, then the method 160 includes evaluating which of the remaining paths has a minimum AEM at step 188. Step 188 may include identifying two of the remaining paths one of which has a minimum AEM of paths corresponding a vector {right arrow over (w)}b that satisfies the relation wa,
Referring to
The final remaining paths are as shown in
The one or more closest vectors identified for each vector {right arrow over (w)}a using the method 160 are then used to calculate simulated BERs in accordance with the methods of
Referring to
In the event that multiple paths remain upon reaching the final stage of the trellis, any remaining paths may be compared at step 196 to identify the minimum path as constrained by the initial constraints of steps 162 and 164.
Referring to
In an alternative embodiment, the method of
The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.