Claims
- 1. An emitter, comprising:
an electron supply; a porous cathode layer having nanohole openings; and a tunneling layer disposed between the electron supply and the cathode layer.
- 2. The emitter of claim 1 wherein the nanohole openings were formed in an annealing process of the emitter.
- 3. The emitter of claim 2 wherein the annealing process is performed in an environment containing nitrogen.
- 4. The emitter of claim 2 wherein the annealing process subjects the emitter to a temperature between about 400 and about 650 degrees C. for about 20 to about 30 minutes.
- 5. The emitter of claim 2 wherein the annealing process decreases the tunneling resistance of the tunneling layer by at least a factor of 2.
- 6. The emitter of claim 1 wherein the tunneling layer is at least one of a metal cluster dielectric, a rapid thermal process grown silicon dioxide, polysilicon, silicon oxide, silicon nitride, silicon oxynitrides or silicon carbide.
- 7. The emitter of claim 1 wherein the tunneling layer is deposited on or includes a ballast layer.
- 8. The emitter of claim 1 wherein the porous cathode layer is selected from the group consisting of platinum, gold, and gold and tantalum.
- 9. The emitter of claim 1 operable to provide an emission current of greater than 1×10−2 Amps per square centimeter.
- 10. The emitter of claim 1 operable to provide an emission current of greater than 1 Amp per square centimeter.
- 11. The emitter of claim 1 operable to provide an emission efficiency of greater than 1%.
- 12. The emitter of claim 1 wherein the tunneling layer has a thickness less than about 500 Angstroms.
- 13. The emitter of claim 1 wherein the narrowest dimension of the nanohole openings are on the order of between 1 and 10 nanometers.
- 14. The emitter of claim 1 wherein the longest dimension of the nanohole openings are on the order of between 10 and 100 nanometers.
- 15. The emitter of claim 1 wherein the nanohole openings are uniformly distributed on average but randomly spaced across the surface of the cathode layer.
- 16. The emitter of claim 1 wherein the porous cathode layer has a porosity of more than 12.5%.
- 17. An integrated circuit, comprising:
a substrate; the emitter of claim 1 disposed on the substrate; and circuitry for operating the emitter formed on the substrate with the emitter.
- 18. An electronic device, comprising:
the emitter of claim 1 capable of emitting energy; and an anode structure capable of receiving the emitted energy and generating at least a first effect in response to receiving the emitted energy and a second effect in response to not receiving the emitted energy.
- 19. The electronic device of claim 18 wherein the electronic device is a mass storage device and the anode structure is a storage medium, the electronic device further comprising a reading circuit for detecting the effect generated on the anode structure.
- 20. The electronic device of claim 18 wherein the electronic device is a display device and the anode structure is a display screen that creates a visible effect in response to receiving the emitted energy.
- 21. The electronic device of claim 20 wherein the display screen includes one or more phosphors operable for emitting photons in response to receiving the emitted energy.
- 22. A storage device, comprising:
at least one emitter to generate an electron beam current, wherein the at least one emitter has a cathode emission surface having nanohole openings; a lens for focusing the electron beam current to create a focused beam; and a storage medium in close proximity to the at least one emitter, the storage medium having a storage area being in one of a plurality of states to represent the information stored in that storage area; such that:
an effect is generated when the focused beam strikes the storage area; the magnitude of the effect depends on the state of the storage area; and the information stored in the storage area is read by measuring the magnitude of the effect.
- 23. The storage device of claim 22 wherein the effect is a signal current.
- 24. The storage device of claim 22 wherein the emitter has been subjected to an annealing process in a environment containing nitrogen.
- 25. An emitter, comprising:
an electron supply layer; an insulator layer formed on the electron supply layer and having an opening defined within; a tunneling layer formed over the electron supply layer in the opening; and a cathode layer formed on the tunneling layer having nanohole openings; wherein the emitter has been subjected to an annealing process to increase the supply of electrons tunneled from the electron supply layer to the cathode layer for energy emission.
- 26. The emitter of claim 25 wherein the tunneling layer tunneling resistance has been decreased by at least an order of 2 by the annealing process.
- 27. The emitter of claim 25 wherein the emitter has an electron emission density greater than about 0.01 Amps per square centimeter.
- 28. The emitter of claim 25 wherein the narrowest dimension of the nanohole openings in the cathode layer are on the order of about 1 to about 10 nanometers.
- 29. The emitter of claim 25 wherein the longest dimension of the nanohole openings in the cathode layer are on the order of about 10 to about 100 nanometers.
- 30. A storage device, comprising:
an integrated circuit including the emitter of claim 25 wherein the emitter creates an electron beam current; and a storage medium in close proximity to the emitter, the storage medium having a storage area being in one of a plurality of states to represent the information stored in that storage area; such that:
an effect is generated when the electron beam current strikes the storage area; the magnitude of the effect depends on the state of the storage area; and the information stored in the storage area is read by measuring the magnitude of the effect.
- 31. An electronic device, comprising:
an integrated circuit including the emitter of claim 25; and a focusing device for converging the emissions from the emitter.
- 32. A computer system, comprising:
a microprocessor; the electronic device of claim 31 coupled to the microprocessor; and memory coupled to the microprocessor, the microprocessor operable of executing instructions from the memory to transfer data between the memory and the electronic device.
- 33. The computer system of claim 32 wherein the electronic device is a storage device.
- 34. The computer system of claim 32 wherein the electronic device is a display device.
- 35. An emitter, comprising:
an electron supply surface; an insulator layer formed on the electron supply surface and having a first opening defined within; an adhesion layer disposed on the insulator layer, the adhesion layer defining a second opening aligned with the first opening; a conductive layer disposed on adhesion layer and defining a third opening aligned with the first and second openings; a tunneling layer formed over the electron supply layer within the first, second, and third openings; and a cathode layer disposed on the tunneling layer and portions of the conductive layer, wherein the portion of the cathode layer on the tunneling layer has nanohole-sized openings providing electron emission sites.
- 36. The emitter of claim 35 wherein the electron emitting surface has an emission rate of at least 0.1 Amps per square centimeter.
- 37. The emitter of claim 35, wherein the narrowest dimension of the nanohole-sized openings in the cathode layer are on the order of about 1 to about 10 nanometers.
- 38. The emitter of claim 35, wherein the longest dimension of the nanohole-sized openings in the cathode layer are on the order of about 10 to about 100 nanometers.
- 39. The emitter of claim 35, wherein the nanohole-sized openings in the cathode layer are on the order of less than 10% the thickness of the tunneling layer.
- 40. The emitter of claim 34 wherein the nanohole-sized openings in the cathode layer are uniformly on average but randomly spaced over the surface of the cathode emission surface.
- 41. An emitter, comprising:
an emitting surface having a first area, the emitter surface having cathode surface with nanohole-sized emission site openings; a first chamber having substantially parallel sidewalls interfacing to the emitting surface; and a second chamber interfacing to the first chamber and having sidewalls diverging to an opening having a second area larger than the first area.
- 42. The emitter of claim 41, wherein the cathode layer is disposed on the emitting surface, and sidewalls of the first and second chambers and wherein the emitter has been subjected to an annealing process in a nitrogen containing environment thereby increasing the emission capability of the emitter.
- 43. The emitter of claim 41 wherein the first chamber is formed within an adhesion layer.
- 44. The emitter of claim 41 wherein the second chamber is formed within a conductive layer.
- 45. An integrated circuit comprising at least one emitter of claim 41.
- 46. A display device comprising at least one emitter of claim 41.
- 47. A storage device comprising at least one emitter of claim 41.
- 48. An integrated circuit, comprising:
a conductive surface to provide an electron supply; at least one emitter formed on the electron supply including,
an insulator layer having at least one opening to define the location and shape of the at least one flat emitter device, a conductive layer disposed over the insulator layer, the conductive layer having at least one opening in alignment with the at least one opening; a tunneling layer disposed within the at least one opening of the insulator layer; and a cathode layer disposed partially over the conductive layer and over the tunneling layer, wherein at least the portion of the cathode layer over the tunneling layer has nanohole-sized openings.
- 49. The integrated circuit of claim 48 wherein the integrated circuit has been subjected to an annealing process having a nitrogen environment.
- 50. The integrated circuit of claim 28 wherein the integrated circuit has been subjected to an annealing process that ramps to an maintains a temperature of at least about 400 to about 650 degrees C. for about 20 to 30 minutes before cooling.
- 51. The integrated circuit of claim 48 wherein the tunneling layer is at least one of a metal cluster, a rapid thermal process grown silicon dioxide, a polysilicon, a silicon oxide, a silicon oxynitride, a silicon nitride, or a silicon carbide dielectric.
- 52. The integrated circuit of claim 48 wherein the tunneling layer has a thickness less than about 500 Angstroms.
- 53. The integrated circuit of claim 48 wherein the tunneling layer is TiOx.
- 54. The integrated circuit of claim 48 wherein the nanohole-sized openings are less than about 500 nanometers and randomly spread over the tunneling layer.
- 55. A method for creating an emitter on an electron supply, comprising the steps of:
forming a tunneling emitter using semiconductor thin-film layers on the electron supply, at least one of the thin-film layers being a film characterized as a porous cathode layer having nanohole openings less than about 500 nanometers in one dimension.
- 56. An emitter created by the process of claim 55.
- 57. The method of claim 55 further comprising the step of annealing the processed emitter to increase the tunneling current of the tunneling emitter.
- 58. The method of claim 57 wherein the step of annealing the processed emitter to increase the tunneling current of the tunneling emitter further creates the nanohole openings in the cathode layer.
- 59. The method of claim 57 wherein the step of annealing the processed emitter is performed in an environment containing nitrogen.
- 60. The method of claim 55 wherein the nanohole openings are uniformly spaced on average over the emission surface and have randomly sized openings between about 1 and 10 nanometers.
- 61. A method for creating an emitter on an electron supply, comprising the steps of:
applying a conductive layer to adhere to an insulator layer disposed on the electron supply, the insulator layer defining an opening to the electron supply; applying a patterning layer on the conductive layer; creating an opening in the patterning and conductive layer to the electron supply; applying a tunneling layer over the patterning layer and the opening; etching the patterning layer to remove it from under the tunneling layer thereby removing the tunneling layer not disposed in the opening by lift-off from the conductive layer; and applying a porous cathode layer having nanohole-sized openings on the tunneling layer.
- 62. An emitter created by the process of claim 61.
- 63. The method of claim 61 further comprising the step of annealing the processed emitter to increase the tunneling current.
- 64. The method of claim 63 wherein the tunneling current is increased by at least a factor of 2.
- 65. The method of claim 63 wherein the step of annealing the processed emitter creates the nanohole-sized openings.
- 66. The method of claim 61 wherein the nanohole-sized openings are on the order of about less than 10% of the thickness of the applied tunneling layer.
- 67. The method of claim 61 wherein the nanohole-sized openings have a narrowest dimensional opening the order of about 1 to about 10 nanometers.
- 68. A method for creating an emitter on an electron supply surface, the method comprising the steps of:
creating an insulator layer on the electron supply surface; defining an emission area within the insulator layer; applying an adhesion layer on the insulator layer; applying a conduction layer on the adhesion layer; applying a patterning layer on the conduction layer; creating an opening to the conduction layer in the patterning layer; etching the conduction layer in the opening to the adhesion layer; etching the adhesion layer to the electron supply; applying a tunneling layer over the patterning layer and the opening; etching the patterning layer beneath the tunneling layer and thereby lifting off the tunneling layer except a portion adhered to the electron supply surface in the opening; applying a cathode layer over the portion of the tunneling layer and a portion of the conduction layer; etching the cathode layer; and creating nanohole-sized openings in the cathode layer.
- 69. An emitter created by the process of claim 68.
- 70. The method of claim 68 wherein the step of creating nanohole-sized openings further comprising the step of annealing the processed emitter.
- 71. The method of claim 68 wherein the nanohole-sized openings are on the order of less than about 500 nanometers.
- 72. The method of claim 67 wherein the nanohole-sized openings are on the order of about 1 to about 100 nanometers.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation in part of commonly assigned U.S. patent application Ser. No. 09/846,127, filed Apr. 30, 2001, which is hereby incorporated by reference.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09846127 |
Apr 2001 |
US |
Child |
10263055 |
Oct 2002 |
US |