Non-volatile memory technologies are constantly advancing and have reached a point where three dimensional (3D) arrays may be the best option for achieving the desired high density. A switching device with a large forward to backward current ratio could more easily enable the 3D stacking of memory cells. Most standard semiconductor switches don't provide the necessary ratio and may require high temperature processes that are incompatible with memory device fabrication. Therefore, there remains a need for new switching devices.
One particular embodiment of this disclosure is a transistor that includes a source; a drain; a gate region, the gate region including: a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and the gate and island are coactively coupled to each other; and a source barrier and a drain barrier, wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region.
Another particular embodiment of this disclosure is a memory array that includes a first memory array layer that includes a plurality of memory units, each memory unit having a transistor electrically coupled to a memory cell; and a second memory array layer that includes a plurality of memory units, each memory unit having a transistor electrically coupled to a memory cell, wherein the transistors include: a source; a drain; a gate region, the gate region including a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and the gate and island are coactively coupled to each other; and a source barrier and a drain barrier, wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region.
Yet another particular embodiment of this disclosure is a transistor that includes a source; a drain; a gate region, the gate region including a gate; an island; and a gate oxide, wherein the gate oxide is positioned between the gate and the island; and the gate and island are coactively coupled to each other; and a source barrier and a drain barrier, wherein the source barrier separates the source from the gate region and the drain barrier separates the drain from the gate region, and wherein the source barrier and drain barrier are thinner proximate the island than they are proximate the gate.
These and various other features and advantages will be apparent from a reading of the following detailed description.
The disclosure may be more completely understood in consideration of the following detailed description of various embodiments of the disclosure in connection with the accompanying drawings, in which:
The figures are not necessarily to scale. Like numbers used in the figures refer to like components. However, it will be understood that the use of a number to refer to a component in a given figure is not intended to limit the component in another figure labeled with the same number.
The present disclosure is directed to various embodiments of switching devices, or more specifically, transistors.
In the following description, reference is made to the accompanying set of drawings that form a part hereof and in which are shown by way of illustration several specific embodiments. It is to be understood that other embodiments are contemplated and may be made without departing from the scope or spirit of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense. Any definitions provided herein are to facilitate understanding of certain terms used frequently herein and are not meant to limit the scope of the present disclosure.
Unless otherwise indicated, all numbers expressing feature sizes, amounts, and physical properties used in the specification and claims are to be understood as being modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the foregoing specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by those skilled in the art utilizing the teachings disclosed herein.
As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” encompass embodiments having plural referents, unless the content clearly dictates otherwise. As used in this specification and the appended claims, the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.
While the present disclosure is not so limited, an appreciation of various aspects of the disclosure will be gained through a discussion of the examples provided below.
The gate 160 and the island 140 are coactively coupled to each other. In embodiments, the gate 160 is coactively coupled to the island 140 through the gate oxide 150. Two structures being “coactively coupled” generally means that the two structures are connected in their behavior. In embodiments, two structures (such as the gate 160 and the island 140) can be electrically coactively coupled, meaning that the electrical behavior of the two structures is connected. For example, applying a positive charge to one of the structures could elicit a negative charge in the other structure. In embodiments, application of a charge (either positive or negative) to the gate 160 can cause the opposite charge (either negative or positive) to build up in regions of the island 140 that are most proximate the gate 160. In embodiments, an applied bias on the gate can generate accumulation of the charge carriers (electrons or holes) in the region close to the gate oxide. The accumulation of the charge carriers depletes the charge carriers in the region of the island on the opposite end. Thus, the band structure of this depleted region can change, resulting in an increase of the energy barrier.
The source 110 and drain 120 can generally be made of either n- or p-type doped silicon (Si). The source 110 and drain 120 are generally either both n- or both p-type doped silicon. The gate 160 can generally be made of metals, metal oxides or poly-silicon. Exemplary metals that can be used for the gate 160 can include those having an appropriate band gap, such as tantalum, tungsten, tantalum nitride, and titanium nitride. Exemplary metal oxides that can be used for the gate 160 can include ruthenium oxide, SrRuO3, CaRuO3, and (Sr,Ca)RuO3. In embodiments where poly-silicon is used for the gate 160, the poly-silicon can be highly doped poly-silicon. The gate oxide 150 can generally be made of silicon dioxide (SiO2), or materials having a high dielectric constant (k) (compared to SiO2). Exemplary high k materials can include zirconium dioxide (ZrO2), yttrium oxide (Y2O3), hafnium dioxide (HfO2), and silicon oxynitrides (SiOxNy). Solid solutions of high k materials (such as those listed above) can also be utilized for the gate oxide. The source barrier 115 and the drain barrier 125 can generally be made of SiO2, or materials having a high dielectric constant (k) (compared to SiO2). Exemplary high k materials can include ZrO2, Y2O3, HfO2, and SiOxNy. Solid solutions of high k materials (such as those listed above) can also be utilized for the source barrier 115 and drain barrier 125. The island 140 can generally be made of appropriately doped silicon with a particular level of carrier concentration, in embodiments, the silicon can be doped to a degenerate level. The island 140 can generally be made of an n- or p-type doped Si or a semiconductor oxide. Exemplary semiconductor oxides can include tin oxide (SnO), non-stoichiometric tin oxide (Sn2O3), and indium oxide (In2O3). Solid solutions of semiconductor oxides (such as those listed above) can also be utilized for the island 140.
In embodiments, the gate 160 can be made of degenerate poly-silicon. In embodiments, the gate oxide 150 can be made of SiO2. In embodiments, the source barrier 115 and the drain barrier 125 can be made of SiO2. In embodiments, the island 140 can be made of doped Si. In embodiments, the gate 160 can be made of degenerate poly-silicon; the gate oxide 150 can be made of SiO2; the source barrier 115 and the drain barrier 125 can be made of SiO2; and the island 140 can be made of doped Si.
Transistors disclosed herein utilize the metal-oxide-semiconductor field effect (MOSFET).
In embodiments the source barrier and drain barrier can have variable thicknesses. In embodiments, the source barrier and drain barrier can be thinner proximate the island than they are proximate the gate. As seen in
Such an exemplary transistor can yield a larger junction surface (than the embodiment depicted in
The memory cells 224 can be spin torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. The plurality of memory array layers 210, 211, 212, and 213 can be stacked in a co-planar arrangement where each of the layers are electrically isolated form each other. Each of the plurality of memory array layers 210, 211, 212, and 213 are electrically coupled to the base circuitry layer 202 and can be operated by the base circuitry layer 202.
Thus, embodiments of TUNNELLING TRANSISTORS are disclosed. The implementations described above and other implementations are within the scope of the following claims. One skilled in the art will appreciate that the present disclosure can be practiced with embodiments other than those disclosed. The disclosed embodiments are presented for purposes of illustration and not limitation, and the present disclosure is limited only by the claims that follow.
Number | Name | Date | Kind |
---|---|---|---|
3982233 | Crookshanks | Sep 1976 | A |
3982235 | Bennett | Sep 1976 | A |
3982266 | Matzen | Sep 1976 | A |
4056642 | Saxena | Nov 1977 | A |
4110488 | Risko | Aug 1978 | A |
4160988 | Russell | Jul 1979 | A |
4232057 | Ray | Nov 1980 | A |
4247915 | Bartlett | Jan 1981 | A |
4323589 | Ray | Apr 1982 | A |
4576829 | Kaganowicz | Mar 1986 | A |
4901132 | Kawano | Feb 1990 | A |
5135878 | Bartur | Aug 1992 | A |
5278636 | Williams | Jan 1994 | A |
5330935 | Dobuzinsky | Jul 1994 | A |
5412246 | Dobuzinsky | May 1995 | A |
5443863 | Neely | Aug 1995 | A |
5580804 | Joh | Dec 1996 | A |
5614430 | Liang | Mar 1997 | A |
5739564 | Kosa | Apr 1998 | A |
5872052 | Iyer | Feb 1999 | A |
5913149 | Thakur | Jun 1999 | A |
5923948 | Cathey, Jr. | Jul 1999 | A |
5929477 | McAllister | Jul 1999 | A |
6011281 | Nunokawa | Jan 2000 | A |
6013548 | Burns | Jan 2000 | A |
6034389 | Burns | Mar 2000 | A |
6077745 | Burns | Jun 2000 | A |
6100166 | Sakaguchi | Aug 2000 | A |
6114211 | Fulford | Sep 2000 | A |
6121642 | Newns | Sep 2000 | A |
6121654 | Likharev | Sep 2000 | A |
6165834 | Agarwal | Dec 2000 | A |
6300205 | Fulford | Oct 2001 | B1 |
6341085 | Yamagami | Jan 2002 | B1 |
6346477 | Koloyeros | Feb 2002 | B1 |
6376332 | Yankagita | Apr 2002 | B1 |
6448840 | Kao | Sep 2002 | B2 |
6462931 | Tang et al. | Oct 2002 | B1 |
6534382 | Sakaguchi | Mar 2003 | B1 |
6617642 | Georgesca | Sep 2003 | B1 |
6624463 | Kim | Sep 2003 | B2 |
6653704 | Gurney | Nov 2003 | B1 |
6667900 | Lowrey | Dec 2003 | B2 |
6724025 | Takashima | Apr 2004 | B1 |
6750540 | Kim | Jun 2004 | B2 |
6753561 | Rinerson | Jun 2004 | B1 |
6757842 | Harari | Jun 2004 | B2 |
6781176 | Ramesh | Aug 2004 | B2 |
6789689 | Beale | Sep 2004 | B1 |
6800897 | Baliga | Oct 2004 | B2 |
6842368 | Hayakawa | Jan 2005 | B2 |
6853031 | Liao | Feb 2005 | B2 |
6917539 | Rinerson | Jul 2005 | B2 |
6940742 | Yamamura | Sep 2005 | B2 |
6944052 | Subramanian | Sep 2005 | B2 |
6979863 | Ryu | Dec 2005 | B2 |
7009877 | Huai | Mar 2006 | B1 |
7045840 | Tamai | May 2006 | B2 |
7051941 | Yui | May 2006 | B2 |
7052941 | Lee | May 2006 | B2 |
7098494 | Pakala | Aug 2006 | B2 |
7130209 | Reggiori | Oct 2006 | B2 |
7161861 | Gogl | Jan 2007 | B2 |
7180140 | Brisbin | Feb 2007 | B1 |
7187577 | Wang | Mar 2007 | B1 |
7190616 | Forbes | Mar 2007 | B2 |
7200036 | Bessho | Apr 2007 | B2 |
7215568 | Liaw | May 2007 | B2 |
7218550 | Schwabe | May 2007 | B2 |
7224601 | Panchula | May 2007 | B2 |
7233537 | Tanizaki | Jun 2007 | B2 |
7236394 | Chen | Jun 2007 | B2 |
7247570 | Thomas | Jul 2007 | B2 |
7272034 | Chen | Sep 2007 | B1 |
7272035 | Chen | Sep 2007 | B1 |
7273638 | Belyansky | Sep 2007 | B2 |
7274067 | Forbes | Sep 2007 | B2 |
7282755 | Pakala | Oct 2007 | B2 |
7285812 | Tang | Oct 2007 | B2 |
7286395 | Chen | Oct 2007 | B2 |
7289356 | Diao | Oct 2007 | B2 |
7345912 | Luo | Mar 2008 | B2 |
7362618 | Harari | Apr 2008 | B2 |
7378702 | Lee | May 2008 | B2 |
7379327 | Chen | May 2008 | B2 |
7381595 | Joshi | Jun 2008 | B2 |
7382024 | Ito | Jun 2008 | B2 |
7391068 | Kito | Jun 2008 | B2 |
7397713 | Harari | Jul 2008 | B2 |
7413480 | Thomas | Aug 2008 | B2 |
7414908 | Miyatake | Aug 2008 | B2 |
7416929 | Mazzola | Aug 2008 | B2 |
7432574 | Nakamura | Oct 2008 | B2 |
7440317 | Bhattacharyya | Oct 2008 | B2 |
7456069 | Johansson | Nov 2008 | B2 |
7465983 | Eldridge | Dec 2008 | B2 |
7470142 | Lee | Dec 2008 | B2 |
7470598 | Lee | Dec 2008 | B2 |
7502249 | Ding | Mar 2009 | B1 |
7515457 | Chen | Apr 2009 | B2 |
7542356 | Lee | Jun 2009 | B2 |
7646629 | Hamberg | Jan 2010 | B2 |
7692610 | Kimura | Apr 2010 | B2 |
7697322 | Leuschner | Apr 2010 | B2 |
7738279 | Siesazeck | Jun 2010 | B2 |
7738881 | Krumm | Jun 2010 | B2 |
7829875 | Scheuerlein | Nov 2010 | B2 |
20010046154 | Forbes | Nov 2001 | A1 |
20020081822 | Yanageta | Jun 2002 | A1 |
20020136047 | Scheuerlein | Sep 2002 | A1 |
20030045064 | Kunikiyo | Mar 2003 | A1 |
20030049900 | Forbes | Mar 2003 | A1 |
20030102514 | Sato | Jun 2003 | A1 |
20030168684 | Pan | Sep 2003 | A1 |
20040084725 | Nishiwaki | May 2004 | A1 |
20040114413 | Parkinson | Jun 2004 | A1 |
20040114438 | Morimoto | Jun 2004 | A1 |
20040257878 | Morikawa | Dec 2004 | A1 |
20040262635 | Lee | Dec 2004 | A1 |
20050044703 | Liu | Mar 2005 | A1 |
20050092526 | Fielder | May 2005 | A1 |
20050122768 | Fukumoto | Jun 2005 | A1 |
20050145947 | Russ | Jul 2005 | A1 |
20050169043 | Yokoyama | Aug 2005 | A1 |
20050218521 | Lee | Oct 2005 | A1 |
20050253143 | Takaura | Nov 2005 | A1 |
20050280042 | Lee | Dec 2005 | A1 |
20050280061 | Lee | Dec 2005 | A1 |
20050280154 | Lee | Dec 2005 | A1 |
20050280155 | Lee | Dec 2005 | A1 |
20050280156 | Lee | Dec 2005 | A1 |
20050282356 | Lee | Dec 2005 | A1 |
20060073652 | Pellizzer | Apr 2006 | A1 |
20060076548 | Park | Apr 2006 | A1 |
20060091490 | Chen et al. | May 2006 | A1 |
20060105517 | Johansson | May 2006 | A1 |
20060131554 | Joung | Jun 2006 | A1 |
20060275962 | Lee | Dec 2006 | A1 |
20070007536 | Hidaka | Jan 2007 | A1 |
20070077694 | Lee | Apr 2007 | A1 |
20070105241 | Leuschner | May 2007 | A1 |
20070113884 | Kensey | May 2007 | A1 |
20070115749 | Gilbert | May 2007 | A1 |
20070253245 | Ranjan | Nov 2007 | A1 |
20070279968 | Luo | Dec 2007 | A1 |
20070281439 | Bedell | Dec 2007 | A1 |
20070297223 | Chen | Dec 2007 | A1 |
20080007993 | Saitoh | Jan 2008 | A1 |
20080025083 | Okhonin | Jan 2008 | A1 |
20080029782 | Carpenter | Feb 2008 | A1 |
20080032463 | Lee | Feb 2008 | A1 |
20080037314 | Ueda | Feb 2008 | A1 |
20080038902 | Lee | Feb 2008 | A1 |
20080048327 | Lee | Feb 2008 | A1 |
20080064153 | Qiang Lo et al. | Mar 2008 | A1 |
20080094873 | Lai | Apr 2008 | A1 |
20080108212 | Moss | May 2008 | A1 |
20080144355 | Boeve | Jun 2008 | A1 |
20080170432 | Asao | Jul 2008 | A1 |
20080191312 | Oh | Aug 2008 | A1 |
20080261380 | Lee | Oct 2008 | A1 |
20080265360 | Lee | Oct 2008 | A1 |
20080273380 | Diao | Nov 2008 | A1 |
20080310213 | Chen | Dec 2008 | A1 |
20080310219 | Chen | Dec 2008 | A1 |
20090014719 | Shimizu | Jan 2009 | A1 |
20090040855 | Luo | Feb 2009 | A1 |
20090052225 | Morimoto | Feb 2009 | A1 |
20090072246 | Genrikh | Mar 2009 | A1 |
20090072279 | Moselund | Mar 2009 | A1 |
20090146185 | Suh et al. | Jun 2009 | A1 |
20090161408 | Tanigami | Jun 2009 | A1 |
20090162979 | Yang | Jun 2009 | A1 |
20090185410 | Huai | Jul 2009 | A1 |
20090296449 | Slesazeck | Dec 2009 | A1 |
20100007344 | Guo | Jan 2010 | A1 |
20100066435 | Siprak | Mar 2010 | A1 |
20100067281 | Xi | Mar 2010 | A1 |
20100078758 | Sekar | Apr 2010 | A1 |
20100110756 | Khoury | May 2010 | A1 |
20100142256 | Kumar | Jun 2010 | A1 |
20100149856 | Tang | Jun 2010 | A1 |
20110079844 | Hsieh | Apr 2011 | A1 |
Number | Date | Country |
---|---|---|
102008026432 | Dec 2009 | DE |
1329895 | Jul 2003 | EP |
WO 0062346 | Oct 2000 | WO |
WO 0215277 | Feb 2002 | WO |
WO 2005124787 | Dec 2005 | WO |
WO 2006100657 | Sep 2006 | WO |
WO 2007100626 | Sep 2007 | WO |
WO 2007128738 | Nov 2007 | WO |
Entry |
---|
Adee, S., “Quantum Tunneling Creates Fast Lane for Wireless”, IEEE Spectrum, Oct. 2007. |
Berger et al., Merged-Transitor Logic (MTL)—A Low-Cost Bipolar Logic Concept, Solid-State Circuits, IEEE Journal, vol. 7, Issue 5, pp. 340-346 (2003). |
Chung et al., A New SOI Inverter for Low Power Applications, Proceedings 1996 IEEE International SOI Conference, Oct. 1996. |
Hosomi et al., A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM, 2005 IEEE. |
Hwang et al., Degradation of MOSFET's Drive Current Due to Halo Ion Implantation, Electron Devices Meeting, 1996, International Date: Dec. 8-11, 1996, pp. 567-570. |
Internet website www.en.wikipedia.org/wiki/High-k dated Nov. 12, 2008. |
Likharev, K., “Layered tunnel barrier for nonvolatile memory devices”, Applied Physics Letters vol. 73, No. 15; Oct. 12, 1998. |
Londergran et al., Interlayer Mediated Epitaxy of Cobalt Silicide on Silicon (100) from Low Temperature Chemical Vapor Deposition of Cobalt, Journal of the Electrochemical Society, 148 (1) C21-C27 (2001) C21. |
Sayan, S., “Valence and conduction band offsets of a ZrO2/SiOxNy/n-Si CMOS gate stack: A combined photoemission and inverse photoemission study”, Phys. Stat. Sol. (b) 241, No. 10, pp. 2246-2252 (2004). |
Takato et al., High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSIs, Downloaded on Apr. 14, 2009 from IEEE Xplore, pp. 222-225. |
U.S. Appl. No. 12/175,545, filed Jul. 18, 2008, Inventors: Lou et al. |
U.S. Appl. No. 12/120,715, filed May 15, 2008, Inventors: Tian et al. |
U.S. Appl. No. 12/498,661, filed Jul. 7, 2009, Inventor: Khoury. |
U.S. Appl. No. 12/502,211, filed Jul. 13, 2009, Inventor: Lu. |
Wang et al., Precision Control of Halo Implanation for Scaling-down ULSI Manufacturing, IEEE International Symposium on Sep. 13-15, 2005, pp. 204-207. |
Giacomini, R., et al., Modeling Silicon on Insulator MOS Transistors with Nonrectangular-Gate Layouts, Journal of the Electrochemical Society, 2006, pp. G218-G222, vol. 153, No. 3. |
PCT/ISA/210 Int'l. Search Report and PCT/ISA/237 Written Opinion for PCT/US2010/041134 from the EPO. |
Romanyuk, A., et al., Temperature-induced metal-semiconductor transition in W-doped VO2 films studied by photoelectron spectroscopy, Solar Energy Materials and Solar Cells, 2007, pp. 1831-1835, No. 91, Elsevier, Switzerland. |
Zahler, James, et al., Wafer Bonding and Layer Transfer Processes for High Efficiency Solar Cells, NCPV and Solar Program Review Meeting, pp. 723-726, 2003. |
Number | Date | Country | |
---|---|---|---|
20120153400 A1 | Jun 2012 | US |