The present disclosure generally relates to insulated gate bipolar transistors (IGBT). More specifically, the present disclosure is concerned with a configuration and a method to limit the turn-off overvoltage on the IGBTs to thereby improve their overall efficiency.
With the limited space allowed for the power inverter circuits in electric and/or electric hybrid automotive applications and the high cost of the semiconductors, the demand for integration of power electronics increases.
A known way of reducing the space occupied by the semiconductors in vehicles inverters is to increase their efficiency to allow the size of the cooling surface to be reduced.
The losses in IGBT modules present in conventional inverter designs are mainly caused by two sources; conduction losses and switching losses. One way to improve IGBT module switching losses is generally by accelerating the IGBT turn-on and turn-off. However, with faster IGBT turn-off, the overvoltage due to the stray inductance of the high-frequency loop increases so much that slow down of the turn-off is often required to protect the device, thereby seriously impacting the efficiency of the inverter.
In the appended drawings:
According to an illustrative aspect, there is provided a DC to AC power converter including first and second IGBTs each provided with a gate, a collector and an emitter, the gate of the each IGBT is connected to a gate driver including a reference; the gate driver reference of the first IGBT being connected to a ground bus of the power converter while the gate driver reference or the second IGBT being connected to the collector of the first IGBT; the parasitic inductance of the emitter of the second IGBT being increased to allow the control to limit an overvoltage at turn off of the second IGBT.
In accordance to another illustrative aspect, there is provided a DC to AC power converter including a first IGBT provided with a collector, an emitter, a gate and a gate driver including a reference and a second IGBT provided with a collector, an emitter, a gate and a gate driver including a reference, the power converter including:
first and second resistors connected in series and connected across a parasitic inductance of an emitter of the first IGBT; the gate driver reference of the first IGBT being connected to the connection point between the first and second resistor;
a transformer having a primary connected across the parasitic inductance of a collector of the second IGBT and a secondary connected to the parasitic inductance of an emitter of the second IGBT, the reference of the gate driver of the second IGBT being connected to the secondary of the transformer.
According to yet another illustrative aspect, there is provided a DC to AC power converter including a first IGBT provided with a collector, an emitter, a gate and a gate driver including a reference and a second IGBT provided with a collector, an emitter, a gate and a gate driver including a reference, the power converter including:
first and second resistors connected in series and connected across a parasitic inductance of the emitter of the first IGBT; the gate driver reference of the first IGBT being connected to the connection point between the first and second resistor;
a transformer having a primary connected across the parasitic inductance of the collector of the second IGBT and a secondary connected in series with the parasitic inductance of the emitter of the second IGBT, the gate driver reference of the second IGBT being connected to the secondary of the transistor.
The use of the word “a” or “an” when used in conjunction with the term “comprising” in the claims and/or the specification may mean “one”, but it is also consistent with the meaning of “one or more”, “at least one”, and “one or more than one”. Similarly, the word “another” may mean at least a second or more.
As used in this specification and claim(s), the words “comprising” (and any form of comprising, such as “comprise” and “comprises”), “having” (and any form of having, such as “have” and “has”), “including” (and any form of including, such as “include” and “includes”) or “containing” (and any form of containing, such as “contain” and “contains”), are inclusive or open-ended and do not exclude additional, unrecited elements or process steps.
In the present specification and in the appended claims, various terminology which is directional, geometrical and/or spatial in nature such as “longitudinal”, “horizontal”, “front”, rear“, “upwardly”, “downwardly”, etc. is used. It is to be understood that such terminology is used for ease of description and in a relative sense only and is not to be taken in any way as a limitation upon the scope of the present disclosure.
Other objects, advantages and features will become more apparent upon reading of the following non-restrictive description of illustrative embodiments thereof, given by way of example only with reference to the accompanying drawings.
The dl/dt at turn-off of the IGBT generates a voltage across the stray inductance of the high frequency loop that is applied across the IGBT above the bus voltage. Proposed herein is a solution based on the injection of a sample of the overvoltage across the IGBT in the gate drive to slow down the slope of the gate voltage to decrease the overvoltage only during the overvoltage period above a predetermined value.
Since this kind of converter is believed well known it will not be described in details herein. It is however to be noted that the inductances, inherently provided in the wires, connections, decoupling capacitor and circuit board traces, have been represented in
As can be seen from
When the IGBT Q1 is turned off, the current transit from Q1 to D2, the period of the overvoltage; the IGBT must be able to support the overvoltage created by the dl/dt across the various parasitic inductances (Lc, L+bus, Lc-high, Le-high, Lc-low and Lc-low) that are present in the circuit. Indeed, since the inductances resist change of current therein, additive voltages develop in the circuit as can be seen by the polarity of the parasitic inductances illustrated in
Generally stated, by changing the reference of the gate driver from the logical pin of
In other words, a technique for connecting reference of the gate driver to the power tab of the IGBT instead of to the logical pin has been developed. The voltage across the emitter inductance is injected in the gate driver to create a negative voltage at the emitter of the IGBT to slow down the negative slope of Vge, as will be discussed hereinbelow. The result is a direct action on the gate voltage without any delay and dl/dt limitations.
Because there is no optimal emitter inductance between the logical and power connections of the emitter in a commercial IGBT module, a technique has been developed to optimize the sample of the overvoltage injected in the gate drive circuit using a resistive divider.
Again, discussing the bottom portion of the three-phase power converter 12 of
The values of the resistors R2 and R3 are selected according to the level of overvoltage allowed across Q1.
By setting the resistor values correctly, it is possible to reduce the effect of the emitter inductance to get the maximum overvoltage allowed to therefore improve the efficiency.
In other words, the normal practice consisting in using a resistor in the ground connection of the gate drive to limit the current in the diodes that protect the gate drive of the lower IGBT from a negative voltage when the upper IGBT turns off has been modified by splitting the resistor in two and adapt the ratio between them to limit the effect of the emitter inductance on the dl/dt. The total resistor remains the same but the voltage divider gives the desired weight of the emitter inductance to limit the overvoltage at the desired level.
The overvoltage should obviously be optimized as much as possible to reach the maximum IGBT rating; this is done by reducing the resistor connected to the logical emitters R3 compared to the resistor connected to the power tab R2. The voltage across the emitter inductance will be split in two and only the voltage across the logical resistor will be applied in the gate drive circuit to limit the gate voltage drop.
It is to be noted that while the resistors R2 and R3 are shown connected across both parasitic inductances Le-low and Lbus, they could be connected solely across parasitic inductance Le-low should this parasitic inductance be sufficient.
The duration of the plateau will impact greatly the losses during turn-off: the longer the plateau, the higher the losses. Because of the desire to limit at the same time the overvoltage and its length, a square wave shape of the overvoltage plateau is suitable. The intrinsic behavior (natural feedback) of the overvoltage gives this shape.
This technique works very well for the bottom IGBT because the emitter inductance is large enough but, for the top IGBT, the emitter inductance is often too small to suitably clamp the voltage without increasing the gate resistor to protect the device. In fact, in practice, the emitter inductance of the top IGBT is very often too low to be used to limit the overvoltage across the top IGBT at the desired level.
Indeed, because of the constraints on packaging of IGBT modules, the upper and lower semiconductors are packaged within close proximity of each other so the inductance of the upper IGBT, Le-high, is quite small, in the order of a few nH. On the other hand, because the only point of connection other than the logical emitter of the lower IGBT is the power tab of −Vbus, the inductance of the lower IGBT, Le-low, is 5 times the upper emitter inductance Le-high. The connection of the −Vbus tab is highly inductive because of its length and curves.
In other words, all IGBT modules have two power connections, part of the high-frequency loop, that are the most inductive: +Vbus and −Vbus. Because −Vbus is in the path of the emitter of the bottom IGBT, it can be used to inject a sample of the overvoltage across the IGBT in the gate driver of the bottom IGBT. Unfortunately, since the +Vbus connection is connected to the collector of the top IGBT, this inductance cannot be used directly as a feedback in the gate driver.
To use Le-high as a feedback in the gate driver, it is therefore required to somehow increase its inductance without unduly increase the overall inductance of the high frequency loop. Two possible techniques to increase the Le-high inductance will be described hereinbelow.
In order to optimize the top IGBT turn-off, a first technique using the collector parasitic inductance to inject a sample of the overvoltage across the top IGBT using a transformer to isolate the collector from the emitter has been designed.
Therefore, a negative voltage appears across the transformer when the current decrease in the top IGBT that applies a negative voltage at the emitter to slow down the slope of the gate voltage. In that case, the optimization of the overvoltage is also performed by the turn ratio of the transformer.
It will be understood that the principle of operation of the circuit of
A second technique to increase the emitter inductance of the top IGBT Q2 will now be described with reference to
One skilled in the art will understand that increasing the parasitic inductance of the upper IGBT may have an impact on the inductance of the total high frequency loop but its impacts on the control of the overvoltage is much more significant.
As can be seen from
The trace 114 also has collector pads 116 that are connected thereto.
The +Vbus tab is connected to trace 104 while the −Vbus tab is connected to trace 118. The phase tab 126 is connected to trace 114.
It is to be noted that the gates of the IGBTs 102 and 112 are not illustrated in
The pads 106 and 116 are interconnected by a U-shaped connector 128 having six (6) legs 130 so configured, sized and positioned as to connect to the pads 106 and 116. One skilled in the art will understand that the U-shaped connector 128 defined the parasitic inductance Le-high since it interconnects the emitter of Q2 and the collector of Q1. Since the U-shape connector 128 is relatively large and includes right angles, the Le-high inductance is relatively high and can be used to limit the overvoltage in the IGBT Q2 as discussed hereinabove. It will also be understood that the size and shape of the connector 128 may be determined according to the desired parasitic inductance required.
Turning now briefly to
Generally stated, the main difference between the layout of
It is to be understood that the turn-off overvoltage limiting for IGBT is not limited in its application to the details of construction and parts illustrated in the accompanying drawings and described hereinabove. The turn-off overvoltage limiting for IGBT is capable of other embodiments and of being practiced in various ways. It is also to be understood that the phraseology or terminology used herein is for the purpose of description and not limitation. Hence, although the above description has been done by way of illustrative embodiments thereof, it can be modified, without departing from the spirit, scope and nature of the subject invention.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/CA2012/001125 | 12/5/2012 | WO | 00 | 6/6/2014 |
Number | Date | Country | |
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61567800 | Dec 2011 | US |