1. Field of the Invention
The present invention relates to flash memory and fabrication method thereof. More particularly, the present invention relates to a two-bit flash memory cell utilizing sidewall storage mechanism and method for manufacturing the same.
2. Description of the Prior Art
Non-volatile memory is computer memory that can retain the stored information even when not powered. Examples of non-volatile memory include flash memory and electically erasable programmable read only memory (EEPROM). Flash memory is non-volatile memory that can be electrically erased and reprogrammed. It is a technology that is primarily used in memory cards or USB flash drives, which are used for general storage and transfer of data between computers and other digital products. Unlike EEPROM, it is erased and programmed in blocks consisting of multiple locations (in early flash the entire chip had to be erased at once). Flash memory costs far less than EEPROM and therefore has become the dominant technology wherever a significant amount of non-volatile, solid-state storage is needed.
At present, the flash memory can be sub-classified into two types: stack gate flash memory and split gate flash memory. Generally, a stack gate flash memory cell includes a floating gate for storing charge, an oxide-nitride-oxide (ONO) dielectric layer and a control gate. The floating gate is between the control gate and the substrate. Because the floating gate is isolated by its insulating oxide layer, any electrons placed on it get trapped there and thus store the information.
According to the prior art method, to program the flash memory 10a, a high voltage is applied to the control gate 28a and a fixed voltage is applied to the drain 18a. By doing this, channel hot electrons generated at the junction between the P type doping region 20a and the drain 18a are injected into the floating gate 24a through the tunnel oxide layer 22a. When electrons are on the floating gate 24a, they partially cancel out the electric field coupling from the control gate 28a, which modifies the threshold voltage (Vt) of the cell 10a. To erase the data stored in the flash memory 10a, the control gate 28a is typically connected to ground or negative voltages and the drain 16a is connected to a high voltage, thereby repelling the electrons in the floating gate 24a by Fowler-Nordheim tunneling mechanism.
As the demand for the small size portable electronic devises such as PDA or mobile phones increases, there is constantly a strong need in this industry to provide high quality and high-density flash memory products, thereby improving the reliability and performance of the electronic products.
It is one object of this invention to provide an improved two-bit flash memory structure in order to increase the integration of the flash memory device.
According to the claimed invention, a two-bit flash memory cell structure is disclosed. The two-bit flash memory cell structure includes a semiconductor substrate; a gate oxide layer on the semiconductor substrate; a gate electrode on the gate oxide layer; a first sidewall spacer stack comprising a first charge storage layer at one side of the gate electrode and a first spacer layer disposed directly above the first charge storage layer; a second sidewall spacer stack comprising a second charge storage layer at the other side of the gate electrode and a second spacer layer disposed directly above the second charge storage layer; an insulating layer between the gate electrode and the first spacer stack and between the gate electrode and the second spacer stack; a liner layer between the first charge storage layer and the semiconductor substrate and between the second charge storage layer and the semiconductor substrate, wherein the insulating layer separates the gate oxide layer from the liner layer; a first source/drain doping region in the semiconductor substrate next to the first sidewall spacer stack; and a second source/drain doping region in the semiconductor substrate next to the second sidewall spacer stack.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
A liner layer 12 is formed on the surface of the semiconductor substrate 10. The liner layer 12 may be a silicon oxide layer. Subsequently, a polysilicon layer 14 such as a doped polysilicon layer is deposited on the liner layer 12. A dielectric layer 16, such as silicon oxide, silicon nitride or oxynitride, is then deposited on the polysilicon layer 14. Preferably, the dielectric layer 16 is a silicon nitride layer.
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Thereafter, using the photoresist layer 20 as an etching mask, a dry etching process is performed to etch the dielectric layer 16, the polysilicon layer 14 and the liner layer 12 through the opening 22, thereby forming a gate trench 24 therein. The photoresist layer 20 is then stripped.
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Using the gate structure 100 as an ion implant mask, an ion implantation process is performed to implant N type or P type dopants into the semiconductor substrate 10 next to the polysilicon charge storage layer 46, thereby forming a source/drain doping region 52. The channel region 26 is between the source/drain doping regions 52. Preferably, the source/drain doping region 52 partially overlaps with the polysilicon charge storage layer 46 after performing thermal drive-in or activation processes.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Number | Date | Country | Kind |
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096117416 | May 2007 | TW | national |