Claims
- 1. A semiconductor device comprising:
- a semiconductor substrate;
- an element isolation region formed to define an element formation region in said semiconductor substrate;
- a first gate insulating layer formed in a part of a surface of said element formation region;
- a first planar gate electrode formed on said first gate insulating layer, wherein the planar gate electrode has at least one substantially vertical edge adjacent a substantially vertical edge of the element isolation region;
- a first insulating layer covering a top of said first gate electrode with a bottom surface of said first insulating layer being substantially in a same plane as that of a top surface of said first electrode;
- a second gate insulating layer formed on said first gate electrode; and
- a second gate electrode formed on said second gate insulating layer.
- 2. The semiconductor device according to claim 1, wherein said insulating layer has vertical edges.
- 3. The semiconductor device according to claim 1, wherein said element isolation comprises an oxidized layer formed on a surface of said semiconductor substrate.
- 4. The semiconductor device according to claim 1, wherein said first gate electrode is a floating electrode and said second gate electrode is a control electrode.
- 5. The semiconductor device according to claim 1, wherein the top surface of said element isolation region is kept substantially at the same level as that of said semiconductor substrate, and said insulating layer comprises at least a planarizing insulating layer formed in a gate width direction of said first gate electrode.
- 6. The semiconductor device according to claim 5, wherein said element isolation region comprises a trench formed in said semiconductor substrate.
- 7. The semiconductor device according to claim 1, wherein said first gate electrode is formed within a stepped portion formed in a part of said element isolation region.
- 8. A semiconductor device comprising:
- a semiconductor substrate;
- an element isolation region formed to define an element formation region in said semiconductor substrate;
- a first gate insulating layer formed in a part of a surface of said element formation region;
- a first gate electrode formed on said first gate insulating layer;
- a first insulating layer covering said first gate electrode and wherein the first insulating layer covers all of a planar top surface of said first electrode;
- a second gate insulating layer formed on said first gate electrode; and
- a second gate electrode formed on said second gate insulating layer.
Priority Claims (2)
Number |
Date |
Country |
Kind |
5-319090 |
Nov 1993 |
JPX |
|
6-060021 |
Mar 1994 |
JPX |
|
Parent Case Info
This is a continuation of application Ser. No. 08/345,719 filed Nov. 22, 1994, now abandoned.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
5036375 |
Mitchell |
Jul 1991 |
|
5472892 |
Gwen et al. |
Dec 1995 |
|
Continuations (1)
|
Number |
Date |
Country |
Parent |
345719 |
Nov 1994 |
|