The present invention relates to a dual modulus prescaler circuit applicable to frequency synthesizers and the like. Specifically, the present invention relates to a dual modulus prescaler circuit which can operate with small signal amplitude and with reduced power consumption.
A “divide-by 4/divide-by 5 divider” switchable between divide-by 4 and divide-by 5 modes, which is a basis for a dual modulus prescaler used for a pulse swallow type PLL synthesizer, is composed of a circuit as shown in
Further, by adding a frequency divider to the output of the circuit, a dual modulus prescaler circuit switchable between divide-by 2n and divide-by 2n+1 modes can be configured.
In the circuit of
Therefore, in order to reduce the power consumption of the dual modulus prescaler, it is important to reduce the power consumption of the “divide-by 4/divide-by 5 divider”. Generally, prescalers require high-speed operation, and so bipolar processes are often used. However, CMOS prescalers have been developed along with achieving higher speed CMOS processes in recent years.
In the case of CMOS processes, it is possible to conceive a DFF circuit using a current mode logic circuit as shown in
The transistors M5 and M6 and the transistors M12 and M13 are turned on and off by a clock inputted as a differential signal to switch current paths. When CN is Hi and CP is Low, the current path is through the M5 side in the master FF. At this time, if a gate voltage IN of M1 is higher than a gate voltage IP of M2, current flows through R1, and Low is read. If IN is lower than IP, current flows through R2, and H1 is read. Simultaneously, the current path Is through the M13 side in the slave FF, and an output is held by M10 and M11.
When CN is Low and CP is Hi, the current path is through the M6 side in the master FF, and data is held by M3 and M4. The current path is through the M12 side in the slave FF, and data is outputted through M8 and M9. This circuit operates as a DFF circuit according to the aforementioned operations.
The NOR circuit used in the “divide-by 4/divide-by 5 divider” can be easily implemented only by replacing the transistor M1 for data input in the DFF circuit of
In the DFF circuit with a NOR gate shown in
The DFF circuit with a NOR gate shown in
Larger signal amplitude provides larger operating margins but requires larger power supply voltage. The DFF circuit with a NOR gate of
The present invention according to the application was made to solve the aforementioned problem. Specifically, an aspect of the present invention according to claim 1 is a dual modulus prescaler circuit for dividing an inputted clock signal to obtain a divide ratio which is selected by a switching signal from a combination of predetermined divide ratios. The dual modulus prescaler circuit includes: n D flip-flop circuits, n being a natural number not less than three; a first multi-input logic gate circuit including at least two input terminals; and a second multi-input logic gate circuit including at least two input terminals. An output terminal of the first multi-input logic gate circuit is connected to a data input terminal of the first D flip-flop circuit; output terminals of the first to (n-2)th D flip-flop circuits are connected to data input terminals of the second to (n-1)th D flip-flop circuits; output terminals of the (n-1)th and nth D flip-flop circuits are connected to input terminals of the first multi-input logic gate circuit; the second multi-input logic gate circuit is connected to the output terminal of the (n-1)th D flip-flop circuit and receives the switching signal, and an output terminal of the second multi-input logic gate circuit is connected to the data input terminal of the nth D flip-flop circuit. Moreover, all the aforementioned connections are connections using differential signals.
Another aspect of the present invention according to claim 2 is the dual modulus prescaler circuit according to claim 1, in which a multi-input logic gate circuit is used for each of the first and second multi-input logic gate circuits, the multi-input logic gate circuit including a current source, first and second resistors each of which has an end connected to a power supply, m transistors connected in parallel, whose sources are connected to an output end of the current source and whose drains are connected to the other end of the first resistor, and further m transistors connected in series, whose sources and drains are connected between the output end of the current source and the other end of the second resistor. Herein, m is a natural number not less than two. Moreover, m differential input data are applied between gates of the transistors connected in parallel and gates of the transistors connected in series, and a differential signal is obtained as an output of the multi-input logic gate circuit at the other ends of the first and second resistors.
A still another aspect of the present invention according to claim 3 is the dual modulus prescaler according to claim 1, in which a D flip-flop circuit with a logic gate circuit is used for each of combinations of the first multi-input logic gate circuit and the first D flip-flop circuit and of the second multi-input logic gate circuit and the nth D flip-flop circuit, the logic gate circuit including: first and second current sources; first and second transistors whose sources are connected to an output end of the first current source; third and fourth transistors whose sources are connected to an output end of the second current source; fifth, sixth, and seventh transistors whose sources are connected to a drain of the first transistor; an eighth transistor whose source is connected to a drain of the seventh transistor; ninth and tenth transistors whose sources are connected to a drain of the second transistor; eleventh and twelfth transistors whose sources are connected to a drain of the third transistor; thirteenth and fourteenth transistors whose sources are connected to a drain of the fourth transistor; a first resistor whose terminal is connected to a power supply and whose other terminal is connected to drains of the fifth, sixth, and ninth transistors and to gates of the tenth and eleventh transistors; a second resistor whose terminal is connected to the power supply and whose other terminal is connected to drains of the eighth and tenth transistors and to gates of the ninth and twelfth transistors; a third resistor whose terminal is connected to the power supply and whose other terminal is connected to drains of the eleventh and thirteenth transistors and to a gate of the fourteenth transistor; and a fourth resistor whose terminal is connected to the power supply and whose other terminal is connected to drains of the twelfth and fourteenth transistors and to a gate of the thirteenth transistor. Moreover, differential clock signals are applied between gates of the first and fourth transistors and between gates of the second and third transistors; a first differential data is applied between gates of the fifth and eighth transistors; and a second differential data is applied between gates of the sixth and seventh transistors.
Still another aspect of the present invention according to claim 4 is the dual modulus prescaler circuit according to claim 3, in which, in the D flip-flop circuit with a logic gate circuit, the current sources are eliminated, and the sources of the first, second, third, and fourth transistors are connected to the ground.
In the present invention, as described above, the DFF circuit with a NOR gate is configured to receive differential inputs, so that the signal amplitude can be reduced. The use of differential signals allows the signal amplitude to be reduced to half, thus achieving reduced power supply voltage. Therefore, there are a method for constituting the DFF circuit with a NOR gate by use of a differential input/differential output NOR/OR circuit and a differential DFF circuit and a method for using a differential input DFF circuit with a NOR gate.
The circuit of
The circuit of
When CN is Hi and CP is Low, the current path is through the M5 side in the master FF. At this time, if a gate voltage IN of M1 is higher than a gate voltage IP of M2, current flows through R1, and Low is read. If IN is lower than IP, current flows through R2, and Hi is read. Simultaneously, the current path in the slave FF is through the M13 side, and the output is held by M10 and M11.
When CN is Low and CP is Hi, the current path is through the M6 side in the master FF, and data is held by M3 and M4. In the slave FF, the current path is through the M12 side, and data is outputted through M8 and M9. This circuit operates as a DFF circuit according to the aforementioned operations. A fully differential “divide-by 4/divide-by 5 divider” can be implemented by using the circuit of
In reading data when CP is Low, only in the case where AP and BP are Low, AN and BN are Hi, and current flows through R2. Accordingly, Hi is read. In other cases, current flows through any one or both of M1A and M1B, and any one or both of M2A and M2B are turned off. Accordingly, current flows through R1, and Low is read.
Therefore, the circuit of
Industrial Applicability
According to the present invention, all the circuits constituting the dual modulus prescaler are designed to be differential input and/or differential output circuits. Accordingly, compared to conventional circuits operating margins for signal amplitude and a signal direct current level can be increased, so that the dual modulus prescaler can operate with smaller signal amplitude. This offers advantages of reducing power supply voltage and power consumption.
Number | Date | Country | Kind |
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2001-386873 | Dec 2001 | JP | national |
Filing Document | Filing Date | Country | Kind |
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PCT/JP02/13190 | 12/17/2002 | WO |