Patent Application
20060114140
The present invention relates generally to semiconductor devices, and more particularly to the implementation of a two-step analog-to-digital converter.
Analog-to-digital converters (ADC) have existed for decades, and are instrumental in determining the quality and the speed of many electronic systems. One type of commonly-used ADC is the flash ADC. A flash ADC has many advantages. As an example, a flash ADC performs fast analog-to-digital conversions, has little intrinsic delays, and is easy to design. They are often used in high-load, high-availability electronic systems.
However, flash ADCs have disadvantages. As an example, flash ADCs consume more power than regular ADCs. As another example, flash ADCs require a larger component count than regular ADCs, and therefore require a larger physical footprint. In addition, because they inherently have lower resolutions, and require a higher input loading than regular ADCs, integrated circuit (IC) designers spend a huge amount of resources just to improve the performance-to-cost ratio. These disadvantages limit them to high frequency and expensive applications that typically cannot be addressed by other ADC types. For example, these applications include: real-time data acquisition, satellite communication, radar processing, sampling oscilloscopes, and high density disk drives.
Desirable in the art of flash analog-to-digital converter designs are improved designs that reduce the component count, physical size, input loading, power consumption, and cost.
This invention discloses a method and system for converting an analog signal to a digital signal using the following steps. The analog signal is compared with a plurality of reference levels dividing a reference voltage range to generate a first set of conversion bits indicating the reference level surpassed by the analog signal. A reference voltage sub-range defined by a first reference level and a second reference level is selected, wherein the analog signal has a voltage level higher than the first reference level and lower than the second reference level. The reference voltage sub-range is divided by a plurality of reference sub-levels. The analog signal is compared with the reference sub-levels to generate a second set of conversion bits indicating the reference sub-level surpassed by the analog signal. The digital signal representing the analog signal is generated based on the first set of conversion bits and the second set of conversion bits.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
In one embodiment of the invention, a new flash ADC circuit is disclosed implementing a two-step ADC decoding method that uses a voltage shift in a first-step conversion. The voltage shift in the first-step conversion eliminates the noise effect on the conversion. A second-step conversion completes the two-step ADC decoding method by recovering an offset voltage applied in the first-step conversion. The two-step ADC decoding method, which uses a novel voltage shift method, reduces the component count of the ADC comparator, improves the input loading, increases input signal bandwidth, reduces chip size, and reduces power consumption.
Inherent in the design of the conventional 8-bit flash ADC 100 is the large number of input comparators (255 in this 8-bit example). The large number of comparators add a huge capacitive load to the VIN signal, so much so that the input signal bandwidth is severely limited. The large number of comparators also consumes more power and requires a larger chip footprint. As such, the conventional 8-bit flash ADC 100 is both power-consuming and cost-ineffective.
In the 8-bit two-step flash ADC 200, the 6-bit flash ADC 204 is shown with a block 206, which includes the upper 32 LSB bit comparators and their corresponding decoder 228, and a block 208, which includes the lower 32 LSB bit comparators and their corresponding decoder 232. The subsequent decoded data from the 3-bit flash ADC 202 and the 6-bit flash ADC 204 are fed to a multiplexer 210 to generate an 8-bit signal 212, which is the digital equivalent of the VIN signal.
A total of 72 comparators (8 comparators for the 3-bit flash ADC 202 and 64 comparators for the 6-bit flash ADC 204) are required to implement the 8-bit two-step flash ADC 200. When compared to the 255 comparators required by the conventional 8-bit flash ADC 100, a significant reduction of component count (183 comparators=255−72) can be achieved. The two-step design reduces the ADC comparator component count, improves the input loading, increases the input signal bandwidth, reduces the required chip size, reduces power consumption, and hence reduces the ADC cost.
The first-step MSB conversion performed by the 3-bit flash ADC 202, which utilizes the full reference voltage range, provides a coarse decoding of the VIN signal. The second-step LSB conversion performed by the 6-bit flash ADC 204 provides a much finer decoding of the VIN signal, and uses the coarse decoding as a starting point for its decoding. The 6-bit flash ADC 204 utilizes only one-fourth of the full reference voltage range to achieve the finer decoding. When decoded data in both the first-step and the second-step conversions are combined, the 8-bit signal 212, which is an accurate digital representation of the VIN signal, is generated.
A reference resistive ladder is utilized to provide precise reference voltages for each comparator of the 3-bit flash ADC 202 and the 6-bit flash ADC 204. The 3-bit flash ADC 202 requires 8 reference voltage inputs by a reference resistive ladder. The input analog signal, or the VIN signal, is connected to one input line of each of the 8 comparators while the other input of the comparator receives one of the 8 reference voltages.
The 8 comparators compensate noise effects due to the conversion process by adding an offset voltage to the VREF signal going to the comparator input. Each of the 8 comparators compares the VIN signal to its specific reference voltage, and generates a high output when the VIN signal is higher than its reference voltage. If VIN signal is less than the comparator's reference voltage, the comparator's output remains low. The 3-bit flash ADC 202 comparator outputs are then decoded, and the 3 decoded digital bits of the ADC output are sent, via a line 214, to the multiplexer 212 to complete full analog-to-digital conversion.
A reference resistive ladder 216 is utilized to provide 64 precise reference voltages for 64 comparators 218 of the 6-bit flash ADC 204. The reference voltages generated from the reference resistive ladder 216 are selected via a line 220, by the decoded outputs of the 3-bit flash ADC 202, at a summing point 222. This summation is repeated for each of the comparators 218 before it is applied, as a comparator input 224, to each comparator. The VIN signal is tied to another comparator input 226. The upper 32 LSBs are compared and decoded in a decoder 228, with the upper 6 LSBs sent to the multiplexer 210 via a line 230. The lower 32 LSBs are compared and decoded in a decoder 232, with the lower 6 LSBs sent to the multiplexer 210 via a line 234. The decoded data sent to the multiplexer 210 via the lines 214, 230 and 234 are used to generate the 8-bit digital 212, which is the digital equivalent of the VIN signal.
Each of the 8 comparators compares the VIN signal to its specific summed reference voltage (VA0 through VA7) and generates a high output when the VIN signal is higher than its reference voltage. If the VIN signal is less than the comparator's reference voltage, the comparator's output remains low. Each of the 8 comparator outputs is sent to a thermo decoder 304 that generates a thermometer code. A thermometer code output is a sequence of the 8 bits in which the 8 bits are consecutively asserted, beginning with the low voltage level to high voltage level. The thermometer code generated by the comparators is then converted to a binary digital signal via the thermo decoder 304.
A table 1 shows the thermo-code output in the first-step MSB conversion, while a table 2 shows the reference voltage range in the second-step LSB conversion in accordance with one embodiment of the present invention. The second-step LSB conversion has a range of one-fourth of the full reference voltage. Therefore, for each of the 8 increments of MSB0 through MSB7, that is, from 10000000 to 11111111, the voltage range of the second-step LSB conversion increments by 2 analog reference voltage steps from VA0 through VA8. For example, for 1111000, the second-step LSB conversion has a voltage range of VA3 to VA5. This enables a finer decoding, or a more precise resolution when compared to the first-step MSB conversion.
As described earlier, a two-step conversion with offset voltage correction (or auto-zeroing in the MSB conversion) will eliminate this noise error. The diagram 402 shows the VIN signal without noise located above VA1 but less than VA2, which is similar to the diagram 400. The diagram 404 shows the addition of an offset voltage (VOFFSET) to the MSB reference voltage (VA1 through VA7) to eliminate the noise effect. In this case, the summation of the VIN signal and noise (VIN+noise) always falls below the summation of VA2 and the offset voltage (VA2+VOFFSET). Therefore, the MSB output is the original ideal case output of 11000000.
Where the offset voltage is added to the MSB reference voltage, an additional MSB bit is used to calibrate the analog signal underestimated by the offset voltage. In this embodiment, the offset voltage may underestimate the analog signal by one reference voltage segment, if the analog signal is not or insignificantly interfered by noise. For example, if the MSB bits equal to 2, the reference voltage sub-range will incorrectly select the underestimated reference segment, and the second step conversion will produce an incorrect result. In this embodiment, an additional bit is used to make the MSB bits equal to 3. Here, a reference voltage sub-range includes two reference segments, that is the segment where the analog signal falls in, and the segment right below it, which is where the analog signal should have fallen in but for the noise interference. Thus, the second step conversion based on this reference voltage sub-range is able to calibrate this underestimation, and produces a correct result.
As discussed above,
The timing diagram 502 shows that the reference voltage VREF is clocked into the comparator 504 at a point 510 and sampled by a sample and hold circuit controlled by the clock CK1. At the same time, the comparator auto-zeros the comparator's output signal during a period 512. The VIN signal is then fed to the comparator 504 and sampled by a sample and hold circuit during a period 514. The sample of the VIN signal is compared to the VREF signal during a period 516. The comparator 504 output is then latched by the latch 506 during a period 518 to synchronize this output with the other MSB comparator outputs. The first-step MSB conversion then repeats itself, starting at a point 520 and a period 522 with the VREF sampling and the auto-zero process.
The timing diagram 526 shows that the VIN signal is clocked into the comparator 504 at a point 528 and sampled by a sample and hold circuit controlled by the clock CK3. At the same time, the comparator auto-zeros the comparator's output signal during a period 530. The VREF signal is then fed to the comparator and sampled by a sample and hold circuit during a period 532. The sample of the VIN signal is compared to the VREF signal during a period 534. This is performed at least one-half clock cycle later than the period 516 when the VIN signal is compared to the VREF in the first conversion step. The comparator 504 output is then latched by the latch 506 during a period 536 to synchronize this output with the other LSB comparator outputs. The second-step LSB conversion then repeats itself, starting at a step 538 with the VIN sampling and the auto-zero process.
In this invention, the VIN signal is sampled only once for using in both the first and second steps of conversions. This differs from conventional ADC architectures, where the sampled analog signal is delayed in time for different bit conversions. This creates a problem that while a sampled analog signal is delayed, the signal can be interfered by noise.
The above disclosure provides many different embodiments or examples for implementing different features of the disclosure. Specific examples of components and processes are described to help clarify the disclosure. These are, of course, merely examples and are not intended to limit the disclosure from that described in the claims. For example, while the embodiment discloses a flash ADC implementing a two-step conversion method, the invention includes three or more step conversion method.
Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the disclosure, as set forth in the following claims.
