Patent Application
20090302885
1. Field
This disclosure relates generally to circuits, and more specifically, to two transistor tie circuits with body biasing.
2. Related Art
In many instances, logic inputs of a device cannot be directly tied to voltage supply terminals, such as VDD and ground terminals. Instead, a tie-high/tile-low circuit is inserted between the logic input and the voltage supply terminal. Such an arrangement is often necessary to protect the circuitry located on the device from electrostatic discharges. While these tie-high/tie-low circuits are effective in protecting the circuitry on the device, they create other issues. For example, traditional four transistor tie-high/tie-low circuits take up valuable space on the device. Certain tie-high/tie-low circuits use two transistors instead and thus take up less space. Such two transistor circuits, however, use complicated biasing schemes to ensure proper operation. That in turn results in wasted space and complex circuits.
Accordingly there is a need for a two transistor tie circuit with body biasing.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
In one aspect, a circuit, which may be used for body biasing is provided. The circuit includes: (1) a p-type transistor having a first current terminal, a second current terminal, a control terminal, and a bulk terminal, wherein the first current terminal of the p-type transistor is coupled to a first voltage supply; and (2) an n-type transistor having a first current terminal, a second current terminal, a control terminal, and a bulk terminal, wherein the first current terminal of the n-type transistor is coupled to a second voltage supply different from the first voltage supply, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to a second node different from the first node.
In another aspect, a circuit that may be used as a tie-high/tie-low circuit is provided. The circuit includes: (1) a p-type transistor having a first current terminal, a second current terminal, and a control terminal, wherein the first current terminal of the p-type transistor is coupled to a first voltage supply; and (2) an n-type transistor having a first current terminal, a second current terminal, and a control terminal, wherein the first current terminal of the n-type transistor is coupled to a second voltage supply different from the first voltage supply, wherein the second current terminal of the p-type transistor and the control terminal of the n-type transistor is coupled to a first node, wherein the control terminal of the p-type transistor and the second current terminal of the second transistor is coupled to a second node different from the first node.
In yet another aspect, an integrated circuit including at least one tie circuit is provided. The integrated circuit includes a first voltage terminal for receiving a first voltage supply and as second voltage terminal for receiving a second voltage supply, where the second voltage supply is different from the first voltage supply. The integrated circuit further includes at least one logic portion comprising a plurality of logic gates, wherein a first of the plurality of logic gates is configured to receive a first output value and wherein a second of the plurality of logic gates is configured to receive a second output value. The integrated circuit further includes at least one tie circuit comprising a first output terminal and a second output terminal, wherein the first output terminal is coupled to provide the first output value and the second output terminal is coupled to provide the second output value and wherein the at least one tie circuit is further coupled to receive the first voltage supply and the second voltage supply. The tie circuit includes: (1) a p-type transistor having a first current terminal, a second current terminal, a control terminal, and a bulk terminal, wherein the first current terminal of the p-type transistor is coupled to the first voltage supply; and (2) an n-type transistor having a first current terminal, a second current terminal, a control terminal, and a bulk terminal, wherein the first current terminal of the n-type transistor is coupled to the second voltage supply, wherein the bulk terminal of the p-type transistor, the second current terminal of the p-type transistor, and the control terminal of the n-type transistor is coupled to the first output terminal, wherein the control terminal of the p-type transistor, the bulk terminal of the n-type transistor, and the second current terminal of the second transistor is coupled to the second output terminal.
The terms “assert” or “set” and “negate” (or “deassert” or “clear”) when used herein, refer to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.
Each signal described herein may be designed as positive or negative logic, where negative logic can be indicated by a bar over the signal name or an asterix (*) following the name. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein can be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.
Referring still to
Furthermore, a bulk terminal and a current terminal of p-type transistor 24 and a control terminal of n-type transistor 26 may be coupled to node 28 providing a logic HIGH value. A bulk terminal and a current terminal of n-type transistor 26 and a control terminal of p-type transistor 24 may be coupled to node 30 providing a logic LOW value. In operation, the coupling of the bulk terminal of p-type transistor 24 to the current terminal of p-type transistor 24 results in body biasing of p-type transistor 24. Similarly, the coupling of the bulk terminal of n-type transistor 26 to the current terminal of n-type transistor 26 results in body biasing of n-type transistor 26. This arrangement relies on leakage currents flowing through the two transistors. The leakage currents are typically the result of short-channel effect and thus tend to worsen with technology scaling. In the embodiment shown in
Furthermore, a current terminal of p-type transistor 124 and a control terminal of n-type transistor 126 may be coupled to node 128 providing a logic HIGH value. A current terminal of n-type transistor 126 and a control terminal of p-type transistor 124 may be coupled to node 130 providing a logic LOW value. By way of example, tie-high/tie-low circuit 122 may be used with silicon-on-insulator (SOI) based transistors. In operation, drain-junction leakage will charge up the body of n-type transistor 126 and thus increase its body voltage. This would result in sub-threshold leakage current increase, which in turn will help pull nodes 128 and 130 back to their stable states.
Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits may be known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.
Although the invention has been described with respect to specific conductivity types or polarity of potentials, skilled artisans appreciated that conductivity types and polarities of potentials may be reversed.
It is to be understood that the various block diagram implementations depicted herein are merely exemplary, and that in fact many other variations can be implemented which achieve the same functionality. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.
Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
