The invention relates generally to analyzing jitter in a digital clock signal, and more specifically to a two-window recovered clock jitter analysis system and method.
When digital signals are transmitted across electrical connections, the impedances and other characteristics of the electrical connections have an effect on the signal. Conductors are imperfect to varying degrees, and the transmitted power must be of sufficient to result in an adequate signal-to-noise ratio where the signal is received.
Although digital signals are typically considered to have one of two voltage levels, in reality this is an ideal that is not physically possible to achieve. Digital signals must transition from one voltage to another over a period of time, which is dependent on the circuitry creating the signal and on the device or wire that is being driven. Also, various conductor or driven device characteristics can sometimes result in a digital signal's voltage overshooting its intended target voltage or to oscillate slightly about the intended voltage.
Because the transition from one voltage level to another can take a period of time that is influenced by other circuit factors, it is sometimes difficult to specify exactly when a digital signal's voltage level will cross a threshold point and be considered to be at one signal level or another. Variations in timing occur, even in relatively stable digital circuits such as digital clock signal circuits. This timing difference from the average or expected transition time is called jitter, and is often measured to ensure that a clock signal is of adequate quality for a particular intended use.
Unfortunately, standards for jitter measurement are not well-defined. Further, some digital clock systems now employ clocks that intentionally change slightly in frequency, and even in rate of change of frequency, making measurement of jitter and meaningful expression of the result even more difficult.
It is therefore desired to measure jitter in a meaningful way, even in the presence of a clock signal that varies in frequency.
In the following detailed description of sample embodiments of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific sample embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical, electrical, and other changes may be made without departing from the spirit or scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the invention is defined only by the appended claims.
The present invention provides in various embodiments a system for measuring jitter of a clock signal. The clock signal is in various embodiments an independently provided clock signal, or a clock signal derived or recovered from another signal such as a data signal. A clock period is determined by evaluating the clock signal within a first window. A clock's jitter is then evaluated within a second window, the second window being smaller than the first window and located within the first window. Determination of the clock signal's jitter within the second window comprises in some embodiments measurement of jitter with respect to the expected clock period determined by evaluating the clock signal within the first window. Such a system enables characterization of jitter in traditional digital clocks, as well as in clocks that change over time such as a spread spectrum clock or a clock undergoing thermal frequency drift.
Although some clock signals drift slightly due to thermal changes in electrical components, a case that is perhaps more significant to modern technology is what has become known as a spread spectrum clock. Such a clock changes slightly in frequency over time to reduce energy and electromagnetic emissions at any one specific frequency, and is often employed to reduce electromagnetic emissions to ensure that maximum emission limits such as those put forth by the Federal Communications Commission are not exceeded. These changes in frequency necessitate a local determination of clock frequency over a period significantly smaller than the period of variation of the clock frequency to make accurate jitter measurements.
In one particular embodiment of a PCI Express bus employing spread spectrum clocking, the clock period varies from 400 ps to 402 ps and back over a period of about 75,000 clock cycles. The first window size 102 of
The first window size is desirably small enough to remain substantially unaffected by the spread spectrum change in the clock frequency, but large enough to make an accurate determination of the average period size of the clock.
The first window size could simply be chosen to be 10,000 cycles or more based on the data of
In
The second window 103 over which jitter is measured is similarly susceptible to error as a result of sharp changes in the rate of frequency change of a spread spectrum clock, as is shown in
Along the rising and falling linear slopes of the frequency transition profile for the spread spectrum clock illustrated in
Next, jitter is determined relative to the recovered clock signal at 505 within the jitter analysis window, which is a 250 cycle window centered within the clock recovery window. From the determined jitter, various statistics can be calculated, including such things as maximums, averages, standard deviations, and other such data. At least one figure of merit quantifying the measured jitter is calculated at 506, and an eye diagram is plotted for comparison with a template defining the maximum allowable jitter.
At 508, the clock recovery window is evaluated to determine whether it is at the end of the clock period sampled at 501. If it is not at the end of the sampled data, the clock recovery window is moved forward one clock cycle at 509, and the process repeats from 505. If the clock recovery window is at the end of the sampled clock data, the process ends at 510.
These examples illustrate how a clock recovery window and a jitter analysis window positioned within the clock recovery window are employed together to perform measurement of jitter. Although one specific example of analysis of a PCI Express spread spectrum clock has been discussed here in detail, it is only one example of an application of the two-window jitter analysis method of the present invention. Various embodiments of the invention will include a variety of sampling techniques, clock types, and evaluation algorithms, all of which are within the scope of the present invention. The two-window jitter measurement system provided here is particularly versatile relative to previous systems because it can be used to measure jitter in both traditional and spread spectrum clocks, and can provide results that are meaningful for both cases. The method can also be employed repeatedly, such as in the example of
The examples presented here further illustrate how window selection results in filtering various signal variation frequency components from the jitter analysis, which has application outside the scope of spread spectrum clock signals. For example, a low-frequency clock variation caused by thermal drift can be filtered out by adequately small first window size selection.
Specific embodiments have been illustrated and described herein, but it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the invention. It is intended that this invention be limited only by the claims, and the full scope of equivalents thereof.