Claims
- 1. A preamplifier, comprising:
an input section, including a first input transistor and a second input transistor connected to a first tail current source transistor, and a third and a fourth transistor connected in cascode with the first and second transistor, where the input section amplifies an input signal; and an output section for increasing the output resistance of the preamplifier, including first and second current source transistors connected to the input section at an output of the preamplifier, where the first and second current source transistors act as load elements for the preamplifier, wherein the preamplifier has high output resistance and produces an output signal of high gain.
- 2. The preamplifier of claim 1, further comprising a reset transistor connected to the output of the preamplifier, the reset transistor responsive to a control signal at a gate of the reset transistor.
- 3. The preamplifier of claim 1, wherein the first and second transistors of the output section are PMOS transistors.
- 4. The preamplifier of claim 1, further comprising a common mode feedback loop, the loop comprising two common mode feedback loop transistors connected in parallel with the current sources for the output section, the output signal applied to gates of the feedback loop transistors, and a second tail current source transistor completing the feedback loop, said second tail current source transistor connected with the first tail current source transistor as a current mirror, and a gate of the second tail source transistor connected to a drain of the second tail source transistor, wherein a common mode voltage feedback to a gate of the first tail source transistor is set by a sum of gate-to-source voltages of the feedback transistors and the second tail source transistor.
- 5. The preamplifier of claim 4, wherein the common mode feedback loop transistors are NMOS.
- 6. The preamplifier of claim 4, further comprising an autozero section, wherein the autozero section has first and second capacitors connected with the first and second input transistors, and first and second autozero transistors connected between the first and second capacitors and the outputs of the preamplifier, the autozero transistors responsive to a signal input to gates of the autozero transistors.
- 7. The preamplifier of claim 6, wherein first and second autozero transistors comprise NMOS transistors.
- 8. The preamplifier of claim 6, wherein first and second autozero transistors comprise PMOS transistors.
- 9. The preamplifiers of claim 6, wherein first and second autozero capacitors comprise NMOS and PMOS transistors in parallel.
- 10. The preamplifier of claim 6, wherein the input transistors comprise NMOS transistors.
- 11. The preamplifier of claim 6, further comprising a reference section, wherein the reference section has first and second input voltage transistors and first and second reference voltage transistors connected in parallel with the capacitors, gates of the input voltage transistors connected to an input enable circuit, and gates of the reference voltage transistors connected to a reference enable circuit.
- 12. The preamplifier of claim 11, wherein the reference voltage transistors comprise NMOS transistors.
- 13. The preamplifier of claim, wherein the reference voltage transistors comprise PMOS transistors.
- 14. The preamplifier of claim 11, wherein the reference voltage transistors comprise NMOS and PMOS transistors in parallel.
- 15. A preamplifier, comprising:
a first current source transistor and a second current source transistor connected to a positive voltage supply; a first tail current source transistor, connected to a negative voltage supply; first and second input transistors connected to the current source transistor; first and second cascode transistors connected in series with the first and second input transistors and forming points of connection with the first and second current source transistors, said points of connection being outputs of the preamplifier, wherein a differential voltage applied to gates of the first and second input transistors is amplified and an output signal is formed and applied to the outputs.
- 16. The preamplifier of claim 15, further comprising a reset transistor connected across the outputs, the reset transistor responsive to a control signal applied to a gate of the reset transistor.
- 17. The preamplifier of claim 15, wherein the first and second current source transistors comprise PMOS transistors.
- 18. The preamplifier of claim 15, further comprising a common mode feedback loop, having first and second common mode feedback transistors connected in parallel with the first and second current source transistors to the voltage supply, the gates of said first and second feedback transistors connected to the outputs, and a second tail source transistor completing the feedback loop, said second tail source transistor connected between joined said common mode feedback transistors and a negative voltage supply or return,
wherein the first and second tail source transistors are configured as a current mirror, the common source being the negative voltage supply, wherein the feedback loop acts to equalize the currents in the first and second current source transistors with the first tail current transistor.
- 19. The preamplifier of claim 18, wherein the common mode feedback transistors comprise NMOS transistors.
- 20. The preamplifier of claim 18, further comprising an autozero section, wherein the autozero section has first and second autozero capacitors connected to gates of the first and second input transistors, and first and second autozero transistors connected between the first and second autozero capacitors and the outputs of the preamplifier, the autozero transistors responsive to a signal input to gates of the autozero transistors.
- 21. The preamplifier of claim 20, wherein the autozero capacitors comprise NMOS transistors.
- 22. The preamplifier of claim 20, wherein the input voltage transistors comprise NMOS transistors.
- 23. The preamplifier of claim 20, further comprising a reference section having a differential section and a reference enable and input enable,
the differential section having first and second differential input transistors and first and second differential reference transistors, said differential input transistors connected to the first and second input transistors through the autozero capacitors, and said differential reference transistors connected in parallel with the first and second differential input transistors, and a reference enable connected to gates of the reference transistors and an input enable connected to gates of the differential input transistors, wherein a reference voltage is applied to the capacitors when a signal is applied to the gates of the reference transistors, and an input voltage is subtracted from the voltage applied to the capacitors when a signal is applied to the gates of the input enable transistors.
- 24. The preamplifier of claim 23, wherein the reference voltage transistors comprise NMOS transistors.
- 25. The preamplifier of claim 23, wherein the reference voltage transistors comprise PMOS transistors.
- 26. The preamplifier of claim 23, wherein the reference voltage transistors comprise NMOS transistors in parallel with PMOS transistors.
- 27. A preamplifier, comprising:
an input section, including a first input transistor and a second input transistor connected to a first tail current source transistor, and a third and a fourth transistor connected in cascode with the first and second transistor, where the input section amplifies an input signal; and an output section for increasing the output resistance of the preamplifier, including first and second current source transistors connected to the input section at an output of the preamplifier, where the first and second current source transistors act as load elements for the preamplifier, wherein the preamplifier has high output resistance and produces an output signal of high gain.
- 28. The preamplifier of claim 27, further comprising a reset transistor connected to the output of the preamplifier, the reset transistor responsive to a control signal at a gate of the reset transistor.
- 29. The preamplifier of claim 27, wherein the first and second transistors of the output section are NMOS transistors.
- 30. The preamplifier of claim 27, further comprising a common mode feedback loop, the loop comprising a second tail current transistor and two common mode feedback transistors connected in parallel with the current sources for the output section, the output signal applied to gates of the common mode feedback loop transistors, said second tail current source transistor connected with the first tail current source transistor as a current mirror, and a gate of the second tail source transistor connected to a drain of the second tail source transistor, wherein a common mode voltage feedback to a gate of the first tail source transistor is set by a sum of gate-to-source voltages of the feedback transistors and the second tail source transistor.
- 31. The preamplifier of claim 27, wherein the common mode feedback transistors are PMOS.
- 32. A preamplifier, comprising:
a first tail current source transistor, connected to a positive voltage supply; a first current source transistor and a second current source transistor connected to a negative voltage supply or return; first and second input transistors connected to the first tail current source transistor; first and second cascode transistors connected in series with the first and second input transistors and forming points of connection with the first and second current source transistors, said points of connection being outputs of the preamplifier, wherein a differential voltage applied to gates of the first and second input transistors is amplified and an output signal is formed and applied to the outputs.
- 33. The preamplifier of claim 32, further comprising a reset transistor connected across the outputs, the reset transistor responsive to a control signal applied to a gate of the reset transistor.
- 34. The preamplifier of claim 32, wherein the first and second current source transistors comprise NMOS transistors.
- 35. The preamplifier of claim 32, further comprising a common mode feedback loop, having a second tail current source transistor and first and second common mode feedback transistors connected in parallel with the first and second current source transistors to the voltage supply, the gates of said first and second feedback transistors connected to the outputs, said second tail source transistor connected between joined said feedback transistors and a positive voltage supply or return,
wherein the first and second tail source transistors are configured as a current mirror, the common source being the positive voltage supply, wherein the feedback loop acts to equalize the currents in the first tail current transistor with the currents in the first and second current source transistors.
- 36. The preamplifier of claim 32, wherein the common mode feedback transistors comprise PMOS transistors.
RELATED APPLICATION
[0001] The present application is related to U.S. patent application ______, now U.S. Pat. No. ______ , entitled Ultra High Speed Clocked Analog Latch, filed on the same day as the present application by the inventor of the present invention and assigned to the assignee of the present invention. The entire contents of the application are hereby incorporated by reference.