Patent Application
20240356499
The invention relates to RF amplifiers and in particular a linear class AB, RF amplifier.
A novel class AB RF amplifier topology was introduced and patented as U.S. Pat. No. 8,378,750. However, this proposed design has some drawbacks which prevent it from being widely adopted. Recently, the inventor realized that this prior art amplifier design has several flaws that make it unsuitable for use as an RF power amplifier to produce high output power while still meeting the linearity requirements of modern communication standards (WIFI for example). One drawback was that the EVM characteristics of this prior art amplifier design falls below desired levels before the transistors in the amplifier run out of power supply voltage headroom. This ultimately results in poor efficiency. In short, the prior art amplifier topology is not competitive against the widely used common-emitter HBT GaAs RF amplifiers produced by the numerous companies, such as Qorvo® and Skyworks®.
To overcome the drawbacks of the prior art and provide additional benefits, disclosed is an amplifier system with matching networks which comprises an input matching network configured to receive an input signal to be amplified from a signal source and output a matching network output signal. The input matching network is configured to impedance match between the amplifier system and the signal source. Also part of the amplifier system is an input transformer configured to receive the matching network output signal and output an input transformer output. The input transformer comprising a step-down transformer configured to provide current gain. An amplifier is configured to receive and amplify the input transformer output from the input transformer to generate an amplified signal. An output transformer is configured to receive the amplified signal and output an output transformer output signal such that the output transformer comprises a transformer ratio of less than 2:1. Also part of this embodiment is an output matching network configured to receive the output transformer output signal from the output transformer and output an output signal. The output matching network configured to impedance match between the amplifier system and downstream component.
In one configuration the downstream component is an antenna. The input matching network and the output matching network may comprise one or more capacitors and one or more inductors. In one embodiment, the amplifier comprises a multi-stage amplifier. The amplifier system may be configured to operate in the radio frequency band and the input signal may be a radio frequency signal.
In one embodiment the input matching network is configured to perform phase matching and current gain. It is contemplated that the output matching network is configured to perform impedance matching and voltage step up modification. In one configuration the input transformer is configured to provide a 2:1 voltage step down to achieve current gain. The output transformer may have a 1:1 winding ratio.
Also disclosed is a method for amplifying an input signal with an amplifier system that comprises an amplifier system comprising an input matching network, input transformer, amplifier, output transformer, and output matching network. The method includes receiving the input signal at the input matching network such that the input matching network is configured to impedance match between the input signal source and the amplifier system and provide an output signal of the input matching network to the input transformer. Then, performing a voltage step down function on the output signal from the input matching network to provide current gain and impedance matching between the input matching network and the amplifier to generate a stepped-down signal. This method also amplifies the stepped down signal with the amplifier to generate an amplified signal and perform isolation between the amplifier and the antenna with an output transformer located between the amplifier and the output matching network to generate a output transformer output signal. Then, performing, with an output matching network, impedance matching and voltage step up between the output transformer and a downstream element, which may comprise an antenna.
The output transformer may be a 1:1 transformer and the input transformer may be a 2:1 step down transformer. In addition, the input transformer includes a first center tap connected to a first bias voltage and a second center tap connected to a second bias voltage. The step of amplifying may comprise amplifying with a first stage amplifier and one or more additional amplifier stages. The amplifier system may be configured to operate in the radio frequency band and the input signal is a radio frequency signal. In one embodiment, the input matching network is configured to perform phase matching and current gain.
Also disclosed is an amplifier system comprising an input matching network configured to receive an input signal from a signal source, the input matching network configured to impedance match between the amplifier system and the signal source. An input transformer configured to receive the impedance matched input signal and perform voltage step down and current step up. An amplifier is configured to receive and amplify an output signal from the input transformer to generate an amplified signal. An output transformer is configured to receive the amplified signal such that the output transformer configured with a 1:1 winding ratio. An output matching network is configured to impedance match to an antenna and provide voltage step up. The input transformer may have a ratio of 2N:N where N is any whole number. In addition, a center tap of the input transformer may connect to a bias voltage.
The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. In the figures, like reference numerals designate corresponding parts throughout the different views.
Included in this disclosure, as foundational information, is U.S. Pat. No. 8,378,750 (assigned application Ser. No. 13/004,183), issued on Feb. 19, 2013, which is incorporated by reference in its entirety herein.
Disclosed herein is an improved CMOS class AB RF amplifier that could deliver high output power levels at high linearity approaching that of an ideal linear RF power amplifier. A fully differential circuit design is shown because in CMOS which is by far the preferred choice. It is contemplated that this amplifier design may also be configured in a single ended configuration. Also, while only a single stage class AB amplifier is shown, it is contemplated that multiple of such stages (optionally scaled down appropriately for the front-end gain stages) could be cascaded to deliver an overall amplifier with a higher gain. Of course, the interstage RF transformers must be modified to interface to the drains of the back-to-back connected NMOS/PMOS transistors that are shown in
As shown in
As an overview, the inputs 104 connect to an input matching network 108, which in turn connects to an input RF transformer 112. The output of the input RF transformer connects to an amplifier 116, which provides an amplified signal to an output RF transformer 120. The RF transformer has an output that connects to an output matching network 124, which in turn provides the output signal on an output 128. Although shown as a differential signal input and a single ended output, referenced to ground 132A, it is disclosed that the circuit may be configured as fully differential or fully single ended.
The circuit of
Within the input RF transformer 112 are several inductors, windings, or signal paths configured to form at least one transformer with associated signal coupling. In this embodiment, the input transformer 112 comprises a 2:1 step down RF transformer configured for current gain and impedance matching.
The positive signal path connects to a winding 144, while the negative signal path connects to a winding 146. The windings 144, 146 are in series as shown. Located in proximity to enable signal coupling are series connected windings 158, 160, as well as series connected windings 158, 160. A center tap between windings 150, 154 connects to a Pbias source 162 which provides a bias for the PMOS FETs in the amplifier 116. Similarly, the center tap between windings 158, 150 connects to a Nbias source 164 which connects to the gate terminals of the NMOS FETs in the amplifier 116.
The signal through the windings 144, 146 couples into windings 150, 154, 158, 160 as occurs in transformers. As such, transformer operation is not described in detail. Any type transformer structure may be utilized that is suitable for operation in a radio frequency signal environment. A center tap connection point of windings L5/L6158, 160 connect to a capacitor C3, which in turn connects to an Nbias voltage source 164. A center tap connection point of windings L2/L3150, 154 connects to a Pbias voltage source 162. Windings L2/L3150, 154 also provide PMOS Gm boosting.
In this embodiment, there is boosting the PMOS devices and not the NMOS, although both could be boosted in other embodiments. The Gm boosting occurs because the gate of device 166 is connected to winding 154, while the source of device 166 is connected to winding 158 as shown. When connected with opposite polarity, as designated by the dot designation which indicates position, there is an increase gate to source voltage of device 166. Device 168 has a similar connection structure. With the source of device 166 is connected to the ‘not the dot’ winding terminal and the gate is connected to the ‘dot’ winding terminal. On the other side, the gate of device 168 is connected to the ‘not the dot’ winding terminal of winding 150, while the source terminal is connected to the ‘dot’ terminal of winding 160. The polarity is thus opposite of each other. If one voltage goes up, the other goes down. As a result, the gate winding provides opposite signal to the source winding which effectively drives the transistor 166, 168 stronger due to the greater differential between the respective gate and source terminals. The gate terminal is driven opposite to the source terminal which provides Gm boosting because the Gm becomes amplified or increased.
After the input RF transformer 112, the signal is presented to the amplifier 116. The amplifier includes PMOS FETs 166, 168 and NMOS FETs 170, 172. The outer terminals of the windings 150, 154 connect to the gate terminals PMOS FETs 166, 168. The outer terminals of the windings 158, 160 connect to the source terminals NMOS FETs 170, 172 and the source terminals of the PMOS FETs 166, 168. The drain terminal of the FETs 170, 166 and the drain terminals of the PMOS FETs 166, 168 connect to the outer terminals of windings 174, 180. The drain terminals of FETs 172, 168 connect to the outer terminals of windings 176, 182.
The amplifier also includes capacitors 194 connected as shown. These capacitors act as a harmonic rejection filter. These capacitors 194 (C4, C5) protect M1 and M3. C4 protect devices M1, M3166, 170 from being stressed or pushed to failure when the drain to source voltage is driven with a high swing. Normally, a transistor will be damaged if the drain to source voltage is driven too high in relation to its voltage handling capability. If driven with high swing, the transistor M1, M3 can be damaged, but with the inclusion of the capacitors C4, the capacitors prevent such damage. The damage can occur when the drain to source is too high, and the transistor is turned on with a gate drive voltage, the transistor will be damaged.
The protection occurs because the capacitor allows the opposite transistor, which is running low voltage to turn on, so it brings the voltage down to prevent the damage when the gate is turned on. Thus, when one device is at high voltage, the opposite transistor is at low voltage. The capacitor pulls this voltage down to prevent damage before the transistor is turned on with a gate signal. Absent this capacitor connection, the transistor would be damaged. Thus, without this stress protection the device will be damaged. Capacitor C5 functions in a similar capacity.
The output RF transformer 120 comprises windings 174, 176, 180, 182, which couple into proximally located windings 184, 186. A center tap located between windings 174, 176 connects to a voltage source Vdd, while a center tap between windings 180, 182 connects to ground 132B as shown. The signal through the windings 174, 176, 180, 182 couples into windings 184, 186 as occurs in transformers. As such, transformer operation is not described in detail. Any type transformer structure may be utilized that is suitable for operation in a radio frequency signal environment. In one embodiment, the output RF transformer comprises a 1:1 output RF transformer with the L13/L14174, 176 having a center tap connection point connected to voltage source Vdd 178. The windings L10/L11182, 180 have a center tap connection point connected to ground 132B.
The outer terminal of winding 184 and the outer terminals of winding 186 connect to the output matching network 124. In particular, the outer terminal of winding 184 and the outer terminals of winding 186 connect to interconnected capacitor 188. The outer terminal of winding 184 also connects to inductor 192, which in turn connects to the antenna port 128, or other type of output port. The outer terminal of winding 186 also connects to ground as shown. The output matching network provides broadband antenna impedance matching as well as additional voltage step up.
The output from the input matching network 208 connects to an input RF transformer 212. The input RF transformer 212 may comprise any combination of windings, transformers, or related elements and connections. One or more voltage may be provided to the input RF transformer 212 to effect amplifier biasing. It is contemplated that other elements may be part of the RF transformer 212 in addition to the one or more transformers.
The output of the RF transformer 212 connects to an amplifier 216. Any type of configuration of amplifier may be utilized. The amplifier 216 may be single ended or differentially configured. Although not shown additional elements and/or biasing may be provided.
The output of the amplifier 216 connects to an output RF transformer 220. The output RF transformer 220 may be configured the same or different than the input RF transformer 212. The output RF transformer 220 may comprise any combination of windings, transformers, or related elements and connections. One or more voltages may be provided to the output RF transformer 220 to effect amplifier biasing. It is contemplated that other elements may be part of the output RF transformer 220 in addition to the one or more transformers.
The output of the output RF transformer 220 connects to the output matching network 224. The output matching network 224 may comprise any combination of one or more resistors, capacitors, inductors, or active element to match the output terminal's 228 impedance to any downstream elements to avoid reflections and achieve maximum power transfer.
Several innovations are introduced to resolve the drawbacks of the prior art common gate class AB power amplifier topology:
Another improvement over the prior art is the introduction of an “anti-compression” step down current mode input stage RF transformer. The impedance of the secondary windings on the L5 & L6 connect to source terminals and are designed to the magnitude of jwL which is about the same as the impedance of the common gate amplifier M1, M2, M3, M4. The goal is to create low impedance. Looking into the source terminal of the transistors M1, M2, M3, M4 (166, 168, 170, 172) a low impedance is seen. As a result, the step-down transformer is connected on the input to this low impedance looking into the amplifier, and as the impedance of the amplifier becomes lower, such as at higher power the Gm goes up so impedance goes down. In this configuration though, the transformer has current gain beyond (in addition to) the normal gain of the step-down transformer which steps down voltage while stepping up voltage. Normally the transformer has a fixed gain, but when connected as shown, to a low impedance amplifier, there is additional current gain from the transformer, particularly when the amplifier is running at high power, which causes a lower amplifier input impedance. This ideally counteracts the typical compression (reduced gain from linear gain) at higher gain of the amplifier. This may be referred to as transformer current gain boosting. As Zin of the amplifier is lower, the transformer has more gain which counteracts the compression of the amplifier.
Thus, the anti-compression is achieved by targeting the secondary winding impedance (the magnitude of jwL) of the input stage RF transformer to be approximately equal to the input impedance of the Class AB push-pull back-to-back source connected NMOS/PMOS devices (the sources of M1-M4) when the amplifier is in the low to mid power operation (meaning while the transistors are still in the class A operation). As the transistors go into class B operation, the transistors would then increasingly go into compression due to the GmRo of the transistors getting lower with increasing power. However, because at the same time the transistor input impedance (which is proportional to 1/Gm) would go lower with increasing output power levels, the input RF current produced by the “anti-compression” input stage transformer would increase, thereby compensating for the well-known compressing behavior of the CMOS transistors at high output power. This is an important improvement over the prior art.
A further aspect of the disclosed amplifier is a lowering of the output stage transformer ratio. For example, prior art output transformers may be in the 2:1 or 4:1 ratio, while in one embodiment of the disclosed amplifier system the output stage transformer ratio is 1:1. In every CMOS amplifier produced in the market to date, to protect the CMOS transistors from being damaged, the transistors are operated at as low voltage as possible. At high output power however, the antenna needs to operate at high voltage levels. To compensate for this and avoid damage to the transistors, a step-up output transformer (such as a 2:1 or even 4:1 ratio (or 1:2 OR 1:4) or a voltage boosting power combiner architecture (4 series connected output stage combiner as shown in the prior art as found U.S. Pat. No. 7,256,573 for example) is used. U.S. Pat. No. 7,256,573 (assigned application Ser. No. 11/095,231), issued on Aug. 14, 2007, is incorporated by reference in its entirety herein. The prior art had aspects that could be improved.
The benefit of using a lower ratio, such as 1:1 is that the voltage is lower. The disclosed system may be equipped with an output transformer and impedance matching network as shown, such that there are two primary windings, one for the NMOS device and one for the PMOS device and a secondary winding and the matching network. This ratio is still 1:1.
It is known to use an output transformer having a high step-up ratio, such as 4:1 or 2:1, (as well as the series connected power combiner) but this harms efficiency. In contrast, the new topology disclosed herein uses a very low output transformer ratio (1:1) to achieve a high output stage transformer efficiency. To provide a high output voltage at the antenna port, an output matching network is introduced. In addition, to protecting the transistors, this innovation has the additional benefit of making the impedance appear at the drain connections, to be highly broadband, which is important to allow the common gate amplifier to function properly.
It is also proposed to apply a similar low transformer ratio consideration to the input stage. Currently, a low ratio input stage transformer is proposed (preferably no larger than a 2:1 ratio) and an input stage matching network to broadband. This input impedance will boost the overall passive input current gain of the 2:1 transformer close to or slightly above 3:1 to maximize the overall RF amplifier current gain. Together with item 2 above, the combination of an input stage matching network with a low ratio input stage transformer provides wide-bandwidth characteristics that are needed to make a truly wide band common gate amplifier.
A further feature of the disclosed design is introduction of a new 2nd harmonic trap capacitor (C3) connecting the gates of the common gate transistors to the center tap of the source coil. The addition of this capacitor forces the gates to track the common mode signals seen at the sources which mainly consists of the 2nd harmonic components, thus preventing the 2nd harmonic components from cross modulating with the main/fundamental signal components. This will provide additional common mode rejection. The gate signal is tracking the source signal. In
Also disclosed is an optional Gm boosting circuit on the PMOS transistors to overcome the low transconductance nature of the PMOS transistors. Gm boosting of the PMOS transistors solves the fundamental weakness of the prior art, as the weak PMOS transistors cause massive buildup of 2nd harmonic components at the transistor source terminals when the common gate amplifier goes into high output power levels. These 2nd harmonic components would inevitably cross modulate with the fundamental signals causing further amplitude compression and worsening the output phase shift as the output power level increases.
An additional feature of the amplifier disclosed herein is the proper matching (sizing) of the effective Gm of the NMOS and PMOS transistors. Because the PMOS Gm boosting is done using a secondary gate winding coil, the Gm boosting amount is achieved in integer increments. Using a 1:1 ratio for the gate/source coils, the PMOS Gm is therefore boosted by a factor of 2. This may result in the effective Gm of PMOS transistors to now be a little higher than that of the non-boosted NMOS counterpart. To overcome this reversed imbalance, the NMOS transistors may optionally be sized up (made slightly larger) relative to the PMOS transistors, to counteract this imbalance. In contrast, without Gm boosting it is the PMOS transistors that need be made larger. However, in practice the viability of increasing the PMOS transistor sizes is very limited, as it would further reduce the already low Ft (transit frequency) of the PMOS transistors, thereby negating the potential benefits of lowering the 2nd harmonic generation through increasing the size of the PMOS transistors. U.S. patent application Ser. No. 17/711,935 filed on Apr. 1, 2022, and published on Oct. 6, 2022 as Publication Number US-2022-0321067-A1 is incorporated in its entirety herein.
In one embodiment, symmetrical FinFet based PMOS and NMOS transistors may be used in certain implementations of this RF amplifier topology. FinFET devices are known in the art, and as such are not described in detail herein. Symmetrical NMOS and PMOS transistors drastically reduce the 2nd harmonic content at the sources of the common gate amplifier to an absolute minimum even without Gm boosting. Symmetrical transistors would also enable a simultaneous Gm boosting of NMOS and PMOS transistors for making the overall RF amplifier smaller in size, especially for the front-end gain stages. Gm boosting is also a fundamental solution to address lower frequency applications (such as the sub-2.5 GHz) by increasing the effective transistor input capacitances thus requiring smaller transformer sizes. Finally, simultaneous Gm boosting using FinFet transistors would result in lower overall power consumption.
Also proposed herein is the injecting of an extra current into the center tap of the source coil (which is equivalent to adding equal but half the current to each of the PMOS sources). This may be achieved using any type of current source 404, 408 as shown in
Also part of some embodiments is the addition of a pair of feedforward capacitors across the opposite source and gate terminals of the Gm boosted PMOS transistors. This is shown in
Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.
While various embodiments of the invention have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of this invention. In addition, the various features, elements, and embodiments described herein may be claimed or combined in any combination or arrangement.
| Number | Date | Country | |
|---|---|---|---|
| 63455333 | Mar 2023 | US |
