The present invention is related in general to a voltage reference generator for an integrated circuit (IC), and, in particular, to a voltage reference generator for a flash memory for a portable device such as a cellular telephone.
In many integrated circuits and particularly in flash memories such as for use in cellular telephones and the like, a voltage reference generator circuit is used. The output of the voltage reference is needed in many blocks of the IC for a variety of functions. Some important requirements for a voltage reference generator for flash memories for use in portable instruments such as cellular phones include:
One example of a design for a voltage reference circuit is the band gap voltage reference (BGVR) circuit. While this circuit has been successfully used in a number of applications, unfortunately it is not well suited for flash memory circuits in portable battery operated devices such as cellular telephones and the like, where low current consumption and low operating voltages are required for at least the following reasons:
Accordingly, what is needed is a simple band-gap voltage reference circuit for a portable flash memory device such as a cellular telephone that will work at acceptable voltages and currents over an extended temperature range and have adequate process stability, using a standard flash technology.
The above-mentioned problems with band-gap voltage reference circuits, as well as other problems, are addressed by the present invention and will be understood by reading and studying the following specification.
a and 3b are layout and cross-section views, respectively, of a vertical NPN transistor which may be utilized in embodiments of the present invention.
a and 5b are layout and cross-section views, respectively, of a lateral bipolar transistor which may be utilized in embodiments of the present invention.
A band-gap voltage reference circuit according to one aspect of the present invention includes a plurality of horizontal gate bipolar junction transistors that show improved gain at low collector currents. The horizontal gate bipolar transistors include an emitter formed by the NMOS memory device n+ source region, a base formed by the NMOS memory device p+ channel region(when the NMOS is off), and a drain formed by the NMOS memory device n+ collector region, in which the base/channel region is less than 0.4 μm in width. Advantageously, the circuit may be fabricated by standard flash memory manufacturing processes. Other advantages and aspects of the present invention will become apparent to those of ordinary skill in the art after examining the detailed description which appears below.
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.
A more detailed drawing of a basic band gap voltage reference (BGVR) 200 according to the present invention is shown in FIG. 2. BGVR 200, as constructed according to the present invention, is capable of working at low power supply voltages and of providing stable reference voltages needed to operate a flash memory circuit in a portable device such as cellular telephone. In this circuit, bipolar transistors Q2 and Q1 are respectively of area 1 and of area N (i.e., N times greater than area 1). Q1 and Q2 are symmetrical in layout. To simplify fabrication, Q1 may be constructed of a number N of individual transistors each having an area of 1. BVGR 200 also includes a pair of PMOS transistors, T1 and T2. The source/drain of T1 is connected between the collector of Q1 and Vcc and the source/drain of T2 is connected between Vcc and tapped resistor R2 which in turn is connected to the collectors of Q2 (the double collector feature of Q1 and Q2 shown in
The gate of T1 is tied to the gate of T2 and is also connected to the collector of Q1. The bases of Q1 and Q2 are tied together and also connected to collector of Q2. To a good approximation, the currents I1 and I2 are the same. In fact, I1 and I2 flow through T1 and T2, which have the same gate and source voltages. The drain voltage however is actually slightly different, but since the gate and the drain of T1 are shorted, this transistor is saturated. In such condition, because of the typical I-Vds characteristics of the MOS transistor with Vgs=constant, the variation of the current due to variations of Vds is negligible. Even if Vds2 is slightly different from Vds1, to a good approximation
I1=I2 (1)
In other words, I2, is the “mirrored” current of I1. The circuit formed by T1 and T2 is commonly referred to as a current mirror.
From the basic silicon junction diode equation, the forward current Ib of the base-emitter diode of bipolar transistors such as Q1 and Q2 is:
Ib=I0eV
Since the base-emitter area of Q1 is N times greater than the base-emitter area of Q2,
Ib1=NI0e(vbe−Ve)/Vt (3)
Ib2=I0eV
The collector currents Ic1 and Ic2 are:
Ic1=β1Ib1 (5)
Ic2=β2Ib2 (6)
Assuming β1 and β2 quite large, Ib1 and Ib2 can be ignored in a first approximation. Therefore:
Ic2=I2 (8)
Since
I1=Ic1 (9)
From Equations (8), (9) and (1),
Ic2=Ic1 (10)
If it is assumed that:
β1=β2 (11)
from Equations (3), (4) and (12):
NI0e(Vbe−Ve)/Vt=I0eVbe/V1 (13)
Rewriting Equation (13):
Ve=VtIn N=(kT In N)/q (14)
Now
Vbg=Vbe+R2I2 (15)
and
I1=Ve/R1+Ib1=Ve/R1+Ic1/β1 (15′)
Assuming β1 is quite large, the term Ic1/β1 may be neglected, thus
I1=Ve/R1 (16)
From Equations (1) and (16):
I2=Ve/R1 (17)
From Equations (14), (15) and (17):
Vbg=Vbe+R2kT In N/R1q (18)
It is well known that Vbe changes with temperature, typically reducing its value by −2 mV/Degree C. for a junction silicon diode. By proper selection of R2, N and R1 it is possible to have R2 kT In N/R1q change by +2 mV/deg C., therefore compensating for the temperature induced changes in Vbg.
Writing Equation (18) for two different temperatures T1 and T2 (T2>T1)
Vbg2=Vbe2+R2kT2 in N/R1q (19)
Vbg1=Vbe1+R2kT1 In N/R1q (20)
From Equations (19) and (20):
Vbg2−Vbg1=Vbe2−Vbe1+R2k(T2−T1) In N/R1q (21)
The values of R2, N, and R1 should be such that there is no variation of band gap voltage with changes in temperature. Thus, the left hand side of Equation (21) is set to 0.
0=Vbe2−Vbe1+R2k(T2−T1) In N/R1q (23)
Hence,
Vbe2−Vbe1=−R2k(T2−T1) In N/R1q (24)
Vbe2−Vbe1/(T2−T1)=−R2k In N/R1q
As noted, the Vbe variation with temperature for a junction silicon diode is −2 mV/ DegC.
Thus,
−2×10−3=−R2k In N/R1q (25)
For stability of BGVR circuit 200 over process variations, bipolar transistors Q1 and Q2 must be drawn exactly with the same layout. Since the emitter of Q1 is N times greater than the emitter of Q2, one simple approach for Q1 is to draw N transistors identical to Q2 and tie together their collectors, their bases and their emitters. This implies that N is an integer number. To minimize silicon area and because N must be greater than 1, N=2 is selected.
R2=2R1q/103k In 2 (27)
From Equation (27) there are numerous possible choices of values for R2 and R1. An additional condition can be used to set the value R2 and R1 setting the current consumption of the BGVR circuit at ambient temperature.
ie=Ve/R1 (28)
From Equation (14) and using N=2:
ie=kT In 2R1q (29)
Setting ie=1 μA:
R1=10−6kT In 2/q (30)
Substituting in Equation (27):
R2=2 103T (31)
For T=300° K
R2=600 K′Ω (32)
At the same T=300° K, using actual values of the Boltzmann constant k=1.38×10−23 and of the electron charge q=1.602×10−19:
R1=17.9 K′Ω (33)
The above values of R1 and R2 may thus be used for a temperature compensated BGVR.
The above calculations are all based on the assumption that hfe (the “gain” or β of the bipolar transistors) is quite high. Unfortunately, high gain bipolar transistors have not been available in standard flash memory fabrication processes. One configuration of bipolar transistor, in theory, available in standard flash memory technology, is the vertical NPN bipolar transistor, i.e., a transistor in which the emitter, base and collector are aligned along a line perpendicular to the wafer surface. With reference to
In an effort to overcome the foregoing problems, some variations have been introduced in the basic band gap reference circuit. For example, “Temperature Compensated Ultra-Low Voltage Band-Gap Reference” by Giulio Marotta and Agostino Macerola, Italian Patent Application Serial No. RM2002A000236, filed on Apr. 30, 2002 (U.S. Patent application Ser. No. 10/365,586, filed on Feb. 12, 2003), commonly assigned with the present invention and incorporated herein by reference as if fully set forth, represents one effort to improve the basic band gap reference circuit. Even with the variation shown in that application, standby current needs to be not less than about 10-12 μA for an acceptable compromise on temperature stability. As the foregoing calculations show, another solution to the problem would be to use bipolar transistors with high hfe. This solution has the advantage of avoiding implementing circuit variations to the basic band gap reference circuit. Unfortunately, as noted, the basic vertical NPN bipolar transistors found in standard flash memory technology do not provide high enough gain.
There is another bipolar transistor that can be found in standard flash memory technology. This transistor is “lateral” or “horizontal” since it has the emitter, base and collector junctions on a plane parallel to the silicon wafer surface. One such horizontal bipolar transistor is formed by the NMOS source region (n+ as emitter), the channel region when the NMOS is off (as the base), and the NMOS drain region (n+ as the collector). Unfortunately, the horizontal bipolar transistor in standard flash memory has demonstrated poor hfe. Because of the poor gain performance such transistors have been considered to be impractical and treated as gate parasitic transistors, i.e., devices that detract from the performance of other circuit elements and are shut off in any working mode of the chip. As MOS technology has improved over the years, the channel length of the standard MOS transistor has been reduced accordingly. As channel lengths have approached values as low as 0.18 mm or less for low voltage NMOS transistors (0.32 mm for high voltage NMOS transistors), the base width of the horizontal bipolar transistors has correspondingly been reduced. Because of these structural changes the performance of the horizontal bipolar transistor is now greatly improved. Such devices are referred to herein as Gate Bipolar Junction Transistors (GBJTs) because their characteristics are also a function of the gate voltage bias. In particular, for short channel lengths, GBJTs show a significantly higher and thus more useful hfe.
Referring to
One example of the hfe curves of the GBJT of structure 500, with the gate grounded, is plotted in
One example of a schematic of the BGVR circuit using Gate Bipolar Junction Transistors according to the present invention is shown in
A voltage reference generator has been described. The voltage reference generator includes a number of horizontal Gate Bipolar Junction Transistor (GBJT) that exhibit a higher and thus more useful hfe at collector currents that are 10 μA and below and can be used in a band-gap voltage reference circuit for integrated circuits and in particular for a portable flash memory device such as a cellular telephone working at acceptable voltages and currents with acceptable temperature and process stability, using a standard flash technology.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
Number | Date | Country | Kind |
---|---|---|---|
RM2002A0500 | Oct 2002 | IT | national |
This is a continuation application of U.S. patent application Ser. No. 10/365,675, filed Feb. 12, 2003, titled “Ultra-Low Current Band-Gap Reference,” which issued as U.S. Pat. No. 6,801,079 on Oct. 5, 2004 and claims priority to Italian Patent Application Serial No. RM2002A000500, filed Oct. 4, 2002, entitled “Ultra-Low Current Band-Gap Reference,” both of which are commonly assigned.
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Number | Date | Country | |
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20050017794 A1 | Jan 2005 | US |
Number | Date | Country | |
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Parent | 10365675 | Feb 2003 | US |
Child | 10924186 | US |