Patent Grant
10198022
This invention relates to improvements in bias current generation for use in analog and mixed signal integrated circuits (ICs), such as current and voltage references and others.
Bias current generation is a core requirement for any integrated circuits (IC), including for higher order functions such as references, regulators, amplifiers, filters, clocks, analog to digital converter (ADC), digital to analog converter (DAC) and other key building blocks in any analog, mixed mode electronic system, or system on a chip (SOC). The bias current should be relatively stable under varying power supply and temperature conditions. Ideally it may further have the capability to operate with low power consumption.
Aspects of the embodiments disclosed herein include that they can often be fabricated in standard digital complementary metal-oxide semiconductor (CMOS) (e.g., for low cost and high volume applications); they may be resistor less (for ultra low power battery powered and emerging batteryless applications, and small size applications); their performance is Mostly independent of metal-oxide-semiconductor field effect transistor's (MOSFET's) threshold voltage or VTH (e.g., for tight performance despite wide manufacturing variations of VTH); and the embodiments typically operate MOSFETs in subthreshold (e.g., for low current and low supply voltage consumption applications). Also, by scaling and operating MOSFET pairs in the subthreshold region a pseudo thermal voltage or VT may be generated which has proportional to absolute temperature (PTAT) voltage characteristics.
Other aspects of the embodiments disclosed herein may be a ‘current source’ comprising: a self cascode (SC) and an amplification function (in conjunction with PTAT voltage generation) whereby the PTAT signal is generated which is mostly dependent on thermal voltage (VT). Also, a complementary to absolute temperature (CTAT) signal is generated which is mostly dependent on MOSFET's mobility (μ) so that a relatively temperature and VTH independent bias current (IBIAS) source may be produced. This may be done in part by applying the PTAT voltage (VPTAT) and supplying the IBIAS) at the gate and not the source of the reference current mirror or loop amplifier. In this way, the active MOS resistor (and the generation of the VPTAT) is effectively placed in series with the gate terminals (instead of the source terminal) of the current mirror or loop amplifier. This topology provides the option and flexibility for employing differential source followers (or differential voltage followers) in unity gain before the amplification function. This option can help in generating a higher amplitude VPTAT so to improve performance and die yield. The temperature coefficient (TC) of the current source can receive adjustments (through program or predetermination by topology with different MOSFET's aspect ratios) to exhibit approximately flat or positive or negative TC depending on electronics system's requirements.
Other aspects of the embodiments disclosed herein are a method of creating a ‘current reference’: two bias current sources (with same functional topology as the first disclosure above) ITCa and ITCb with same polarity TCs that are set by W/L ratios to yield differing slopes, and subsequently be ratioed and subtracted from each other to form a stable TC current reference (IREF). Alternatively, depending on an application, the topology has the flexibility to deliver positive TC or negative TC IREF that can also receive adjustments by programming or setting different MOSFET W/Ls. In each of the two bias current sources, the amplifier's built-in offsets are forced across MOSFETs contained in self-cascodes (SC) to make the ITCa and ITCb. The magnitudes of ITCa and ITCb are set partially independently from their TCs via MOSFET's aspect ratios. To generate an IREF with stable TC, a current scalar and subtraction circuit then scales ITCa to Sa.ITCa whose value changes by the same amount as Sb. ITCb over an objective temperature span. This resultant Sa.ITCa current is then subtracted from Sb.ITCb to yield an IREF. Sa and Sb are abbreviated formulaic representations (as a function of MOSFET W/L ratios and CMOS device constants).
Other aspects of the embodiments disclosed herein are a ‘voltage reference’ (VREF) circuit comprising: resistor free voltage reference with an output voltage VREF, which can be a pseudo bandgap voltage, VBG. Here, CTAT signal voltage (VCTAT) is generated by VBE of a parasitic bipolar junction transistor (BJT) in CMOS, and its PTAT signal voltage VPTAT is generated by summing K of pseudo thermal voltage, VT×ln(g), terms generated via K series (or chain) of scaled p-channel MOSFET (PMOSFET) self-cascodes (SC), whose operating conditions are provided through a bias current generator with substantially similar functional block diagram as the first and second disclosures above. Similarly, the TC of this VREF can be set (by programming or predetermination by topology with different MOSFET's aspect ratios) to exhibit approximately flat or positive or negative TC, depending on electronics system's need.
Other aspects of the embodiments disclosed herein include a method of generating a bandgap voltage reference, VBG. In the general category of conventional bandgaps, a voltage reference is comprised of a VPTAT that is gained up by the ratios of two passive resistors and then added to a VCTAT (e.g., VBE) to produce VBG. Passive resistors are generally prohibitive, in size or cost, for ultra low power applications based in standard digital CMOS. This embodiments herein generally eliminate the need for passive resistors. Instead, this disclosure consists of a network of composite active MOS resistors whose operating conditions (e.g., current) are supplied via the substantially similar bias current functional topology. Here, the central bias current generation and the bandgap loop circuitries, independently apply VPTAT across functionally similar composite MOS resistors (i.e., RM802 and RM826r) to generate their respective operating currents (i.e., as a multiple or ratio of Ibias). The resultant VPTAT is subsequently added to a VCTAT (e.g., VEB) to generate a VBG. Again, the TC of this reference can be set (via programming or predetermination by topology with different MOSFET's aspect ratios) to exhibit approximately flat (for VBG) or positive or negative TC output VREF, depending on electronics system's requirement. Note that operations of: RBIAS and IBIAS in the SC of the bias generation circuit, the composite active MOS resistor circuit (i.e., RBS), the chain or series of the same composite active MOS resistor (i.e., p.RBG), and the bandgap's PTAT loop follow substantially similar operating mechanisms over process, temperature, and power supply variations. This embodiment which combines the bias current circuit, active resistor circuit, and bandgap PTAT loop circuit not only may avoid passive resistors (for ultra low current and low cost), but also it can enhance bandgap's overall performance by enabling tracking of operating conditions over process, temperature, and supply voltage variations.
Further aspects of the embodiments disclosed herein include: a method of generating a bias current by using a first active resistor metal-oxide-semiconductor field effect transistor (MOSFET) operating in the linear region that is in series with gate input terminals of a proportional to absolute temperature (PTAT) voltage generator.
Further aspects of the embodiments disclosed herein include: a system comprising: a means for generating a bias current is in series with gate input terminals of a proportional to absolute temperature (PTAT) voltage generator.
Further aspects of the embodiments disclosed herein include: a bias current generator system comprising: a first current generator comprising: a first amplifier having a built in offset voltage tracking a proportional to first absolute temperature (PTAT) voltage (VPTAT); a first bias resistor metal-oxide-semiconductor field effect transistor (MOSFET) operating in the linear region and forming a first bias resistor, wherein the gate input terminals of the amplifier carrying the VPTAT are in series with source-drain terminals of the first bias resistor MOSFET; and wherein a first bias current is generated as a ratio of the first VPTAT over the resistance of the first bias resistor MOSFET and where adjustments can be made to the amplitude and temperature coefficient (TC) of the first bias current.
Further aspects of the embodiments disclosed herein include: a bias current generator system comprising: a MOSFET resistor operating in the linear region which is in series with a VPTAT; and a means for generating said VPTAT voltage and a bias current by feeding back the bias current into the MOSFET resistor. The MOSFET resistor may be part of MOSFET self-cascode or a current mirror.
Further aspects of the embodiments disclosed herein include: a bias current generator system comprising: a first current generator comprising: a first amplifier having inputs connected to the output of a first differential voltage follower, wherein the first differential voltage follower has a built in offset voltage tracking a proportional to first absolute temperature (PTAT) voltage (VPTAT); a first bias resistor metal-oxide-semiconductor field effect transistor (MOSFET) operating in the linear region and forming a first bias resistor, wherein the gate input terminals of the first differential voltage follower carrying the VPTAT are in series with source-drain terminals of the first bias resistor MOSFET; wherein the first amplifier output generates the bias current which flows through the source-drain of the bias resistor MOSFET until the amplifier input voltages are substantially equalized; and wherein a first bias current is generated as a ratio of the first VPTAT over the resistance of the first bias resistor MOSFET and where adjustments can be made to the amplitude and temperature coefficient (TC) of the first bias current.
Further aspects of the embodiments disclosed herein include: a bias current generator system comprising: a MOSFET resistor operating in the linear region which is in series with a VPTAT; a means for generating a VPTAT; and a means for generating a bias current by feeding back the bias current into the MOSFET resistor. The MOSFET resistor may be part of MOSFET self-cascode or a current mirror.
Further aspects of the embodiments disclosed herein include: a method of generating a reference current comprising: generating first and second bias currents such that the first and second bias currents have the same polarity of temperature coefficient (TC) and different TC slopes; and wherein the first and second bias currents are then scaled and subtracted from one another to yield stable TC reference current over an objective temperature range.
Further aspects of the embodiments disclosed herein include: a system of generating a reference current comprising: a MOSFET resistor operating in the linear region; and a means for generating two bias currents with the same temperature coefficients (TC) polarity but different TC slope and different amplitudes which are subsequently subtracted from one another to form the reference current.
Further aspects of the embodiments disclosed herein include: a method of using a composite active metal-oxide-semiconductor field effect transistor (MOSFET) resistors in bandgap voltage reference comprising: developing a proportional to absolute temperature voltage (VPTAT) across a composite active MOSFET resistors and subsequently adding the VPTAT to a complementary to absolute temperature voltage (VCTAT) to generate the band gap voltage.
Further aspects of the embodiments disclosed herein include: a system comprising: an active MOSFET resistor which has a VPTAT placed across it to generate a bias current; and a means for generating a floating resistance.
The following description has been presented for purposes of illustration and description and is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Many modifications and variations are possible in light of the teachings disclosed herein. The embodiments were chosen and described to explain principles of operation and their practical applications. However, the scope of the invention is to be defined by the claims.
Battery operated or batteryless electronic systems benefit from integrated circuits and electronic components that consume minimal power, which can withstand and perform to specifications down to the lowest power supply levels over a wide span of temperatures, as well as ones that can provide stable Alternating Current (AC) and non-jittery transient power up and power down characteristics. For higher order analog functions (e.g., references, regulators, amplifiers, converters, voltage controlled oscillators, phased locked loops, clock chips, etc) and systems (e.g., mixed mode system on a chip (SOC)), higher performance of the bias generation function can facilitate a more rugged system topology and lower cost systems solutions when such functions can be fabricated in standard digital mainstream Complementary Metal-Oxide Semiconductor (CMOS) technologies. While battery operation would benefit from low current consuming electronics, however, for next generation batteryless electronics (e.g., batteryless Internet of Things, energy harvesting, biometrics electronics, etc.), ultra low power consuming electronics is a not a ‘nice to have’ but a ‘must have’.
Generally, ultra low power analog and mixed signal electronic systems require large value resistors that may occupy large die sizes. Otherwise, they would require special and additional fabrication layers (which are costly) to deposit high ohm per square resistive material on silicon wafers which makes the use of passive resistors very costly. In order for the new and emerging applications (e.g., energy harvesting, biometrics, consumer medical electronics) to realize their full market size and reach potential expediently, resistor free electronics in small die size are key, and being based in main stream digital CMOS fabrication process manufacturing (that is proven) would be required. Such proven manufacturing platforms help achieve low cost and reduce manufacturing risk so as to facilitate and expedite serving such emerging applications, especially those that require passing regulatory tests (that favor proven manufacturing platforms) such as bio-electronics and consumer bio-metrics applications.
The following terms, definitions, acronyms, term usages and abbreviations are explained below and used throughout this detailed description:
Here is a brief introduction of the bias current generator block diagram functions (
The majority of circuit implementations (in the prior art in this category of bias current generation) derail in their current regulation at high temperatures. When operating at ultra low currents, amongst other factors, the MOSFET's small leakage currents (e.g., MOSFET source, drain, body junction diode's leakage) may no longer be ignored, when compared to that of the (also very small) circuit's operating currents. Leakage current especially mounts at hot temperatures and as such they can interfere and derail performance. Although, operating at ultra low currents generally narrows the temperature span due, in part, to standard digital CMOS device leakages, but circuits may be more or less sensitive to leakage depending on topology. For example, in the prior art implementations, where the bias resistors are in series with the source of the current mirror or loop amplifier circuit, such implementations are accompanied with asymmetries induced by mismatched MOSFET W/Ls in order to generate the PTAT signal in current mirrors, loop amplifiers, and or self-cascode cells. Therefore, high temperature operation may, in part, be hindered due to MOSFET source drain body junction diode leakage imbalances. For example, in asymmetric junction diode areas in drain or source terminal's leakage currents pile on (which are hard to match and cancel) as they double every 10 degrees Celsius (10 C)—in a thin ice circuit environment so to speak—where each transistor is already operating in ultra low currents (approximately five to tens of nanoamperes (e.g., more than approximately 5 nA and less than approximately 100 nA).
In order for the leakage current imbalances present in ‘signal paths’ of current mirror's, or loop amplifier's, or self-cascode's to be contained for a majority of bias current circuit implementations in the prior art, MOSFET aspect ratios need to be somewhat restricted, which limits the magnitude of the VPTAT signal that can be generated. In the subthreshold region (for ultra low current operation), MOSFET's mismatches are dominated by VTH mismatches. The implementation of most of the prior art systems, generally limits the magnitude of the VPTAT signal (to contain leakage), which then makes the topology more sensitive to MOSFET's VTH mismatches. As such, the VTH mismatches become a large part of the intended VPTAT magnitude, which worsens the current source's die yield to specifications. Moreover, in the general cases of the prior art (e.g., when using a self-cascode structure to generate the PTAT signal) the positive TC of VT term and negative TC of VGS (VTH) can push the self-cascode stack off to the edge of the triode-saturation region and derail accuracy of the current reference at min-max temperatures. In the next sections, the proposed embodiments are described along with their benefits.
Suitable for ultra low power and high volume applications, the proposed ‘bias current generator’ IC belongs to a resistor-free category of CMOS circuits that combines a proportional to absolute temperature (PTAT) signal dependent mostly on pseudo thermal voltage (VT) and a complementary to absolute temperature (CTAT) signal dependent mostly on MOSFET's mobility (μ) to generate a relatively temperature and MOSFET threshold voltage (VTH) independent current source, although the embodiments disclosed here can be set to deliver positive or negative TC depending on application need.
First, a brief description of the general embodiments are provided where the ‘bias current generator’ block diagrams contain 2 basic functions: amplification function (in combination with some VPTAT as a built in offset voltage generation function) and self cascode (SC) function. A subset of variations of the bias current generator's functional block diagrams are depicted in
Functional block diagram of
The simplified block diagrams in
In
Node description of
Node description of
Node description of
In
In summary, the higher performance of the bias current generator shown in block diagrams of
Placing the MOSFET of self cascode that establishes the RBIAS (i.e., M202n, M402p, M802p) in ‘gate’ and not the ‘source’ terminal of the current mirror or loop amplifier, effectively places the RBIAS function into the feedback loop of the current mirror amplifier signal path. One benefit of this feature is that, in effect, the open loop amplification in effect reduces the impedance effect of the RBIAS (which is in the mega ohms level for ultra low currents) at output and input nodes of the current mirror or loop amplifier.
These implementations allows for the flexibility and having the option of employing differential source followers to generate a larger VPTAT (instead of prior art use of either asymmetric current mirror's or loop amplifier's source terminal connected to RBIAS or scaled self-cascode, which in part can limit optimal amplitude for the VPTAT signal). This method's flexibility allows for larger VPTAT which helps desensitize IBIAS from offsets (e.g., due to normal manufacturing VTH and W/L mismatches associated with transistors in current mirror and loop amplifier). Therefore the IBIAS could be more insensitive to standard digital CMOS process fabrication variations and mismatches.
Source drain junctions of MOSFETs have leakage current that double with every 10 C rise in temperature. The proposed bias current generator topology allows for reduction of the impact of asymmetric aspect ratios for MOSFETs, and the narrowing their undesirable impact of their associated source drain junction leakages, for example in the cascoded current mirrors, in the IBIAS current mirror or current loop amplifier.
This bias current generation scheme provides the option of utilizing NMOSFET or PMOSFET self cascodes where with respect to either the positive and negative power supply. For example, this is demonstrated in
Another benefit of this bias current generation scheme is that it allows for negative power or VSS and ground potential (GND) to be same, as well as allowing for decoupling of negative power or VSS from ground (GND), where technically VSS can run at a lower voltage than the ground potential. As a result, the bias current value may be set relative to either GND or VSS depending on electronics system requirement, which provides for more system topology flexibility.
In summary, the benefits of the bias current generation circuit may include: the proposed topology can deliver current consumption in the tens of nanoamperes (nA) range (i.e., more than approximately 10 nA and less than approximately 100 nA) operate with sub 1 volt supply voltage in a small die size that is 4 to 50 times smaller in size, compared to prior art current references in its category. Benefits of this current reference may include: low cost, higher temperature span, low voltage coefficient (VC), wider TC and VDD span. The impact of source-drain junction leakages is reduced and hot temperature span of the bias current generator is extended. Low power supply operation at ultra low current can be achieved in part because of the flexibility of the bias current generation scheme. Power supply rejection ratio (PSRR) and other AC performance are enhanced. The overall benefit of this class of bias current generators is retained, including for example, that it can operate in sub-threshold, which keeps current consumption low and enables lower VDD operation. Moreover, the impact of process fabrication variation on performance is contained and controlled given the significantly less sensitivity of the bias current generation to VTH and dependence on μ, which is more tightly controlled in fabrication process. Moreover, low cost is also achieved because in part the proposed topology does not require any passive resistors. Low cost is also achieved by proposed topology's small die size that may be based in standard digital CMOS, making the topology portable to multiple digital standard CMOS fabrication facilities. Also, basing the topology on standard digital CMOS fabrication process (without any custom or special devices) facilitates process portability which should help speeding up regulatory bodies qualification of new products (i.e., biometric ICs) who view standard manufacturing ICs much more favorably.
The first utilization of the functional block diagram of
Here is a brief summary of the description and benefits of the embodiment of
Suitable for ultra low power applications, including energy harvesting, the proposed ‘bias current source’ embodiment belongs to a resistor-free category of CMOS circuits that combines a PTAT signal dependent mostly on VT and CTAT signal dependent mostly on MOSFET's μ to generate a relatively temperature and VTH independent current source. The proposed topology consumes ultra lower currents (e.g., 50 nA to 500 nA) and can operate with sub-1V VDD. The simplicity of the topology, in part, enables its small size, compared to prior art current references in its category. It has the potential for wider temperature compared to its alternatives. Higher temperature span may be achieved by the following. First, sensing the PTAT voltage and forcing the IBIAS at the gate and not the source of the reference current mirror or loop amplifier. In effect this topology, places the RBIAS (and the development of VBIAS) in series with the gate as opposed to in series with the source of the current mirror or loop amplifier. Second, having the option of using differential source followers to generate a larger PTAT voltage instead of prior art use of either asymmetric MOSFETs in the current mirror or current loop amplifier and or scaled self-cascode. Third, using donut shaped equal W/L transistors in a circuit layout to minimize the drain size for less leakage current.
This embodiment allows for larger PTAT voltage, which helps desensitize IBIAS from error contributions of normal mismatches and offset and fabrication process variations (e.g., VTH and W/L mismatches associated with transistors in current mirror and loop amplifier). The proposed topology allows for minimization or elimination of the impact of asymmetric transistors and cascoded current mirrors in the current reference (IREF or IR or Ir) loop. As a result, compact die size is realized, the impact of source-drain junction leakages is reduced substantially, and hot temperature span is extended.
In
The connections of the elements in
In
VGSM202−VGSM200=VDSM202;
RBIAS=RM202≈[μ.COX.(W/L)M202(VGSM202−VTHn−VDSM202/2)]−1;
VGSM202≈[2IBIAS/μ.COX.(W/L)M200]1/2+VTHn;
VGSM206−VGSM204=[VT.ln(d×b)]=VDSM202;
VDSM202≈IBIAS(c+1)×RM202≈[VT.ln(d×b)];
μ.COX.(W/L)M202×[IBIAS/μ.COX.(W/L)M200]1/2≈IBIAS(c+1)×[VT.ln(d×b)]−1; and
IBIAS≈f(S202,μ,VT).
It can be noticed that VTH term is canceled out in both the first loop (M204, A200, M206) and the second loop (M200, M202). This trait can significantly reduce IBIAS'S sensitivity to VTH, where VTH has substantial variations in process fabrication and manufacturing (e.g., VTH nominal at 0.4V with +/−50% variation). As it is the case with this class of current sources, IBIAS is primarily a function of COX, VT, and u. Here COX is a function of gate oxide thickness which has a very low temperature coefficient, VT has a positive TC (PTAT like) and μ has a negative TC (CTAT like). Therefore, the TC of IBIAS can be positive or negative or approximately flat depending on the abbreviated formulaic constant (scalar), S202, which is function of MOSFET's aspect ratios a, b, and d as well as MOSFET device constants.
In this section some of the benefits of the utilization of the embodiment of
In both prior art examples depicted in
However, in this invention shown in
In the
For some of prior art implementations, it could be that in order for current mirror's, or loop amplifier's, or self-cascode's leakages to be contained (and ultimately its hot temperature performance less hindered), the W/L (or area) of pertinent MOSFETs had to be somewhat restricted, which limits the allowed amplitude of VPTAT that can be generated (e.g., approximately 50 mV versus 150 mV). Note again that Voltage Proportional to Absolute Temperature (VPTAT) is generally generated via the difference in VGS of two MOSFETs that operate in subthreshold, but whose W/L and or quiescent currents are scaled differently. A circuit topology for reliable manufacturing would benefit from a VPTAT whose amount is set by W/L ratios and VT (which are accurately controlled) as opposed to being dominated from example by VTH mismatch between the two pair of MOSFETS. The prior art is restricted to smaller amount of VPTAT (e.g., 50 mV) which is a disadvantage because it would increase the impact of normal process fabrication mismatches and offsets on controlling the value of IBIAS to specifications in manufacturing, and ultimately the yield of IBIAS to the target specifications. For example, a contribution of 5 mV of VOFS (mismatch between two MOSFETs) to a 50 mV of VPTAT is 10% offset error contribution to VPTAT which is the case with some of the prior art. However, 5 mV of VOFS over 150 mV VPTAT is 3% offset error contribution to VPTAT which can be the case with this embodiment's topology. In the embodiment of
Note also that in the general cases of prior art (where a self-cascode structure is employed to generate the PTAT term) the positive TC of VT.ln (bxd) and negative TC of VGS (or VTH) can push the self-cascode stack off to the edge of triode-saturation region and derail accuracy of current reference at min-max temperatures. Also, in the
Employing the functional block diagram of
The following is a description of the embodiment of
As noted earlier, the proposed topology allows for magnitude and TC of ITCa and ITCb be set with some independence from one another using device aspect ratios, while it employs substantially identical topology mechanisms to generate ITCa and ITCb—which improves performance over power supply, temperature, and fabrication process variations. Concurrently, ITCa and ITCb (whose TCs and amplitudes are set partially independently from one another by adjustments to their MOSFET's aspect ratios) are fed into a current scalar and subtraction circuit, which scales (K400a.ITCa) to S400. (K400a.ITCa) whose value changes by the same amount as K400b.ITCb over an objective temperature span. This resultant current or S400.(K400a.ITCa) and K400b.ITCb are subtracted from each other to yield an IREF. All generated currents are mostly independent of VTH and primarily a function of MOSFET's μ and VT, thus helping stable specifications of IREF over fabrication process variations. Note that IREF can also be programmed to have a negative or positive TC via wider flexibility in choosing different MOSFET's W/L ratios in the generation of ITCa, ITCb, and the scalar factor (e.g., S400, K400a and K400b, which is a formulaic representation of MOSFET W/L ratios as well as MOSFET's device parameter constants) in the current scalar subtraction circuit.
This second utilization of the embodiment of
As noted earlier, the same principles of this embodiments of the functional block diagram of
Firstly, here are more details describing how current generator ITCa yields a current with TCa. The signal loop that generates ITCa includes M402a, which makes the active CMOS resistor, RM402a (i.e. RBIASa). The active transistor M402a, operating in deep triode, makes the small size but high value resistor, RM402a, which helps in keeping the die size small while current at ultra low levels. The signal loop is also composed of amplifier A400a (consisting of M404b-M416a) with a built in offset determined by W/L ratios of M404a to M406a and M410a to M408a, which are c and d, respectively. Input stage of A400a helps generate the PTAT term of about VT.ln (cxd). The amplifier A400a, substantially equalizes the VDS of M402a to the PTAT term of about VT.ln (cxd). This is accomplished in part via forcing the gate voltages of transistors M418a, which operate as a voltage controlled current source (VCCS) to bias M402a and M400a which set RM402a and whose operating current scales in proportion with ITCa. The value of RM402a or RBIAS-400a is set in part by the SC400a composed of M400a and M402a scale factors and MOSFET's mobility which helps generate the CTAT term. The ITCa is made of VT.ln (cxd) divided by RM402a. Note that in
Secondly, and similar to the above description to ITCb generation, applying the same principle to the embodiment of
Thirdly and lastly, the current ITCb is scaled and mirrored via M418b and M420b (by 1/h.X) and fed into M422b which is scaled (by j.X) and mirrored onto M422a. Concurrently, the current ITCa is scaled and mirrored via M418a and M420a (by 1/e.X) and fed into drain of M422a. Here the final IREF is generated which is a function of K400b. ITCb-S400. (K400a. ITCa), where K400a, K400b, S400 are formulaic representations and approximately a function of MOSFET's W/L ratios and MOSFET's (device) fabrication process constants. Also note that other variations of this circuit topology knowable by those skilled in the art can include, but not limited to, for example generating ITCb using the prior art circuits such as the ones shown in
The connections of the elements in
Source and body of M400a are connected to drain of M402a and connected to node 402a, which is also connected to gate of M406a. Source and body of M402a are connected to drain of M418a and gate of M404a and connected to node 400a. Source and body of M404a, and source and body of M406a and drain of M416a are connected to node 406a. Drain of M404a and drain of M408a and gate of M412a are connected to node 408a. gate and drain of M410a and drain of M406a are connected to node 410a. Drain of M412a and gate and drain of M414a are connected to node 404a. Gate terminals of M416a, M418a, and M420a are connected to node 404a. Drain of M420a and gate and drain terminals of M422a are connected to node 412a, which is the IREF terminal. Note that M404a, M406a, M408a, M410a, M412a, and M414a form an amplifier (A400a) with M404a and M406a gates at nodes 400a and 402a as A400a's input terminal and gate and drain of M414a as its output terminal. Also, as is the case with the
Drain of M420a is connected to gate and drain of M422b as well as gate of M422a at node 412b. Drain of M422a and drain of M420a are connected to node 412a, as well as the IREF output terminal. Note that M420a, M422a, and M420b, M422b constitute one of many possible embodiments (a simple one used here for descriptive simplicity and clarity) for the current scalar and subtractor function, but there are other higher performance variations of current scalar and subtractor function available and covered in prior art (e.g., Ledesma, F. et al, “Comparison of new and conventional low voltage current mirrors,” Circuits and Systems, 2002. MWSCAS-2002, which is hereby incorporated by reference in its entirety).
In summary, current generator ITCa includes M400a-M418a, and current generator ITCb includes M400b-M418b, where ITCa and ITCb have differing TCs which are set by the circuit's MOSFET's scale factors (as well as a factor of MOSFET device parameter constants) so to generate an IREF with positive TC, or negative TC, or a near zero TC, which will be explained below.
Here is a more detailed explanation of the embodiment of
ITCa=IDSM418a=IDSM402a=IDSM400a=VDSM402a/RM402a;
VGSM406a−VGSM404a≈VT.ln(cxd)=VDSM402a;
RM402a≈[μ.COX.(W/L)M402a(VGSM402a-VTHp-VDSM402a/2)]−1;
VGSM402a≈[2ITCa/μ.COX.(W/L)M400a]1/2+VTHp,
μ.COX.(W/L)M402a×[ITCa/μ.COX.(W/L)M400a]1/2≈ITCa.[VT.ln(dxc)]−1.
ITCa≈f(K400a, μ, VT), where K400a is set approximately by MOSFET's device parameter constants and the W/L sizes of MOSFETs in the ITCa's current generator circuitry.
Similar operations hold for the A400b and SC400b loops that generate the ITCb. Amplifier A400b's input includes M404b, M406b, M408b, M410b that has a built-in offset voltage roughly equal to VT.ln(fxg) which is forced across M402b of SC400b (with its diode connected counterpart M400b) so to generate a current ITCa via M418a that has a temperature coefficient of TCb:
ITCb=IDSM418b=IDSM402b=IDSM400b=VDSM402b/RM402b;
VGSM406b−VGSM404b≈VT.ln(g×f)=VDSM402b;
RM402b≈[μ.COX.(W/L)M402b(VGSM402b−VTHp−VDSM402b/2)]−1;
VGSM402b≈[2ITCbμ.COX.(W/L)M400b]1/2+VTHp;
μ.COX.(W/L)M402b×[ITCb/μ.COX.(W/L)M400b]1/2≈ITCb.[VT.ln(g×f)]−1;
ITCb≈f(K400b,μ,VT),
where K400b is set approximately by the W/L sizes of MOSFETs in the ITCb's current generator circuitry;
In the current scalar and subtractor circuit there is: IREF=K400b. ITCb−S400. (K400a ITCa). As noted earlier, If a near zero TC current reference (IREF), then magnitude of ITCa can be scaled with MOSFET's W/L ratios such that a current S400. (K400a. ITCa) whose value changes near equally to that of K400b ITCb over an objective temperature range.
In the embodiment of
In this section some of the benefits of the embodiment depicted in
Also, while adhering to matching considerations by using the same exact narrow W and long L in the two independent self cascades (SC400a and SC400b), the TC and magnitude of ITCa and ITCb can be programmed differently via (mostly by) setting the ratio of W/Ls of MOSFETs aspect ratios, which can be made accurate with respect to topology targets because they are most independent of fabrication process variation.
In effect, the embodiment of
Similar to the embodiment of
As just noted for the embodiment of
Moreover, embodiment of
The embodiment shown in
The embodiment in
Here is a description of the embodiment of
Operating in subthreshold, the MOS bias current generator segment includes the SC's M602 and M600. In the bias current generator segment of
Note that in
The connections of the elements in
In the current bias generator section, which biases up the voltage reference, the source and body of M600 are connected to drain of M602 and connected to node 602, which is also connected to gate of M604. Source and body of M602 are connected to drain of M618 and gate of M606 and connected to node 600. Source and body of M604, and source and body of M606 and drain of M616 are connected to node 606. Drain of M606 and drain of M610 and gate of M612 are connected to node 608. Gate and drain of M608 and drain of M604 are connected to node 610. Drain of M612 and gate and drain of M614 are connected to node 604. Gate terminals of M616, M618, and M620 are connected to node 604. Note that M604, M606, M608, M610, M612, and M614 form a voltage amplifier (A602) with M604 and M606 gates at nodes 600 and 602 as A602's input terminal, and gate and drain of M614 as the amplifier output terminal. Also, similar to the embodiment of
The PTAT signal (with respect to VDD) is generated via a series of MOS SCs, whose node's connectivity is as follows: node 628 is connected to drain of M630 and to the body and source of M630t and to the source and body of M628. Node 624 is connected to drain of M628 and to the body and source of M628t and to the source and body of M626. Node 620 is connected to drain of M626 and to the body and source of M626t and to the source and body of M624. Node 616 is connected to drain of M624 and to the body and source of M624t and to the positive input terminal of output amplifier, A600. Node 630 is connected to gate of M630 and gate plus drain of M630t and drain of M630i; Node 626 is connected to gate of M628 and gate plus drain of M628t and drain of M628i; Node 622 is connected to gate of M626 and gate plus drain of M626t and drain of M626i; Node 618 is connected to gate of M624 and gate plus drain of M624t and drain of M624i. Gates of M630i, M628i, M626i, and M624i are connected to gate of M612 at note 608. In
The following is a more detailed description of
As noted earlier in this section, the embodiment in
VGSM602−VGSM600=VDSM602;
RBIAS=RM602≈[μ.COX.(W/L)M602(VGSM602−VTHp−VDSM602/2)]−1;
VGSM602≈[2IBIAS/μ.COX.(W/L)M600]1/2+VTHp;
VGSM604−VGSM606=[VT.ln(cxb)]=VDSM602; and
μ.COX.(W/L)M602×[IBIAS/μ.COX.(W/L)M600]1/2≈IBIAS.[VT.ln(cxb)]−1;
IBIAS≈f(S600,μ,VT).
As just noted above, this same IBIAS is applied to the SC series, where:
VDSM630=VGSM630−VGSM630t;
VDSM628=VGSM628−VGSM628t;
VDSM626=VGSM626−VGSM626t; and
VDSM624=VGSM24−VGSM624t.
Given that the bias circuit employs a similar mechanism (i.e., VGSM602−VGSM600=VDSM602) to generate both the bandgap's IBIAS and VPTAT sections, hence their operating conditions track over power supply, temperature, and supply variations, thereby aiding bandgap's specifications.
Before turning to more details about the benefits of the
Some of the benefits of the embodiment of
In addition to the synthesis of the aforementioned contributions of the embodiment of
This fourth embodiment shown in
The embodiment in
The goal here is for the functional block shown in
Here is a summary description and some of the benefits of the embodiment of
However, prior arts bandgaps of this category require passive resistors (e.g., R800 and R802), which makes their implementation in small form factor, low-cost, and ultra low power applications, such as energy harvesting impossible or impractical. Therefore, a resistorless CMOS bandgap embodied of
A new composite active MOS resistor is proposed, depicted in
The bias circuit of
Note also that in the SC loop in the IBIAS generator circuit of
The combination of the IBIAS generator of
Another advantage of combining IBIAS generator of
The connections of the elements in the embodiment of
The connections of the elements in
The connections of the elements in
The connections of the elements in the prior art
As noted earlier, the proposed circuit belongs to the general category of bandgap voltage references in standard digital CMOS that operate in subthreshold (see
In
VGSM802−VGSM800=VDSM802;
RBIAS=RM802≈[μ.COX.(W/L)M802(VGSM802−VTH−VDSM802/2)]−1;
VGSM802≈[2IBIAS/μ.COX.(W/L)M800]1/2+VTH;
VGSM806−VGSM804=[VT.ln(d×b)]=VDSM802;
VDSM802≈IBIAS(e+1)×RM802[VT.ln(cxb)];
μ.COX.(W/L)M202×[IBIAS/μ.COX.(W/L)M200]1/2≈IBIAS(e+1)×[VT.ln(cxb)]−1;
IBIAS≈f(S800,μ,VT).
This IBIAS, mostly a function of S800 (which is formulaic representation consisting of MOSFET W/L ratios and MOSFET's device constants) as well as μ, and VT.
The composite active MOS resistor of
The equivalent of RBG of
VDSM826r˜VT.ln(n1×g);
VGS826b−VGS826r˜VDS826r˜VT.ln(n1×g);
IDSM826r˜VT.ln(n1×g)/RM826r;
IDSM826i˜IDSM826b˜f(S.μ,VT).
As such, IDSM826r (and the composite MOS's resistance) is mostly a function of VT and μ and is independent of MOSFET's VTH. Here, the dependence of RBG's network (of active resistance and its operating current) on μ and VT and their approximate independence from VTH can help enhance manufacturability and enable performance optimization, including efficient trimming to attain higher accuracy in this bandgap. To simplify description of this circuit's operations and it benefits, the composite active MOS resistors are approximated as: RBG as a lump sum ‘resistor’ in series with a lump sum ‘voltage source’ (which encapsulates the offset mismatch due to VGS terms of MOSFETs as well as the amplifier in the composite active resistor circuit of
ΔVOFSR is configured as the random mismatch between VOFSM828r, VOFSM830r, VOFSM832r, VOFSM834r, VOFSM826r of each of the composite MOS resistors. Here ΔVOFSR should induce an additional offset error term (statistical contribution) to VBG output of roughly (G+1)1/2×ΔVOFSR where ‘G’ is set by the (number active MOS resistor in series in the feedback loop of the bandgap circuit) ratio of string of composite active MOS resistors in the PTAT loop to satisfy the functional equivalent R802/R800 ratio (in
To guard band for start-up and transient response A836'S output does not drive both the operating currents that feed Q804 and Q806 in order to eliminate the positive feedback in the PTAT loop. But accuracy of the VBG is not compromise. This is because the proposed embodiment of
Although other variations of this topology are possible, the embodiment in
In summary the benefits of the embodiment in
As noted above, for WLBL electronics market potential to materialize, it is imperative that circuits ought to operate with ultra low currents. Hence the use of passive resistors are nonviable for several reasons: higher resistance obviously means prohibitively large die area (e.g., VPTAT of 700 mV at 10 nA requires 70MΩ poly resistor). Mainstream digital CMOS foundries generally do not guarantee resistance specifications, including for higher Ω/square poly resistors. Compared to lower Ω/square layer 1 poly resistors, the layer 2 higher Ω/square ones typically exhibit higher mismatch, worst non-linearity, and inferior TCs, in part because of less fabrication process control for the less critical process layers (i.e., ploy 2 and higher layers, especially highly doped ones). High Ω/square diffusion resistors are also impractical here due to unfavorable leakage, VC, and TC characteristics. Therefore, predominant research on ultra low power configurations, based on digital standard CMOS, has produced (non-conventional) non-bandgap topologies to generate voltage references, that are generally not as rugged as bandgaps.
In order to guard band for long-term production continuity, utilizing the kind of circuit topologies that can be ported to multiple process nodes with minimal challenge are obviously favored. In this regards, conventional bandgap topologies could generally be viewed on a more positive light because of manufacturing's familiarity and experience with the more predictable and controllable BJT parameters such as VBE and VT that constitute VBG. This embodiment retains the benefit of the class of bandgap voltage references to which it belongs.
This embodiment provides a composite active CMOS resistor (
In summary, disclosed above are bias current topologies with embodiments in current source, current reference, (pseudo bandgap) voltage reference, and bandgap voltage reference that operate at ultra low currents and low power supply voltages which may use main stream standard digital Complementary Metal-Oxide-Semiconductor (CMOS) processes. The bias current topology uses chiefly a self cascode (SC) and PTAT offset generation with loop signal amplification to produce a bias current. The bias current circuit, senses and forces the PTAT signal (mostly as a function thermal voltage VT) at the gates of its loop amplification circuit, which in combination with a CTAT signal (mostly as a function of mobility of MOSFETS, μ) provides the flexibility of setting a negative, positive, or stable temperature coefficient (TC) bias current generator circuit, depending on an application's need. This circuit retains the benefits of the class of bias current circuits, whose current variations are approximately independent of threshold voltage (VTH) and mostly a function μ. Hence die yields and performance over process and temperature spans are improved. Embodiments of the bias current topology (
A number of embodiments are described in the present application, and are presented for illustrative purposes only. The described embodiments are not, and are not intended to be, limiting in any sense. One of ordinary skill in the art will recognize that the disclosed embodiment(s) may be practiced with various modifications and alterations, such as structural, logical, software, and electrical modifications. Although particular features of the disclosed invention(s) may be described with reference to one or more particular embodiments and/or drawings, it should be understood that such features are not limited to usage in the one or more particular embodiments or drawings with reference to which they are described, unless expressly specified otherwise.
Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. Therefore, any given numerical range shall include whole and fractions of numbers within the range. For example, the range “1 to 10” shall be interpreted to specifically include whole numbers between 1 and 10 (e.g., 1, 2, 3, . . . 9) and non-whole numbers (e.g., 1.1, 1.2, . . . 1.9).
The present disclosure is not a literal description of all embodiments of the invention(s). Also, the present disclosure is not a listing of features of the invention(s) which must be present in all embodiments. A description of an embodiment with several components or features does not imply that all or even any of such components/features are required. On the contrary, a variety of optional components are described to illustrate the wide variety of possible embodiments of the present invention(s).
Although process (or method) steps may be described or claimed in a particular sequential order, such processes may be configured to work in different orders. In other words, any sequence or order of steps that may be explicitly described or claimed does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order possible. Further, some steps may be performed simultaneously despite being described or implied as occurring non-simultaneously (e.g., because one step is described after the other step). Moreover, the illustration of a process by its depiction in a drawing does not imply that the illustrated process is exclusive of other variations and modifications thereto, does not imply that the illustrated process or any of its steps are necessary to the invention(s), and does not imply that the illustrated process is preferred. Although a process may be described as including a plurality of steps, that does not imply that all or any of the steps are preferred, essential or required. Various other embodiments within the scope of the described invention(s) include other processes that omit some or all of the described steps.
Although a product or system may be described as including a plurality of components, aspects, steps, qualities, characteristics and/or features, that does not indicate that any or all of the plurality are preferred, essential or required. Various other embodiments within the scope of the described invention(s) include other products that omit some or all of the described plurality.
This application claims the priority benefit of Ser. No. 15/375,170, filed on Dec. 12, 2016; which claims the priority benefit of U.S. patent application Ser. No. 14/795,862, filed on Jul. 9, 2015; which claims priority benefit of U.S. Provisional Patent Application Ser. No. 62/022,820, filed Jul. 10, 2014 and entitled “An Ultra Low Power CMOS Current Source”; U.S. Provisional Patent Application Ser. No. 62/060,193 filed Oct. 6, 2014 and entitled “A Very Low Power Resistorless CMOS Bandgap Voltage Reference”; U.S. Provisional Patent Application Ser. No. 62/126,588 filed Feb. 28, 2015 and entitled “A Very Low Power and Stable Current Reference”; and U.S. Provisional Patent Application Ser. No. 62/129,002 filed Mar. 5, 2015 and entitled “A CMOS Bandgap Reference With Improved PSRR and Voltage Coefficient”. Each of the above applications are herein specifically incorporated by reference in their entirety.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4593208 | Single | Jun 1986 | A |
| 4677369 | Bowers et al. | Jun 1987 | A |
| 5283579 | Tasdighi | Feb 1994 | A |
| 5294927 | Levinson et al. | Mar 1994 | A |
| 5640084 | Tero et al. | Jun 1997 | A |
| 5668710 | Caliboso et al. | Sep 1997 | A |
| 5734260 | Tasdighi et al. | Mar 1998 | A |
| 5734291 | Tasdighi et al. | Mar 1998 | A |
| 5734292 | Tasdighi et al. | Mar 1998 | A |
| 5783936 | Girard et al. | Jul 1998 | A |
| 5814995 | Tasdighi | Sep 1998 | A |
| 5923208 | Tasdighi et al. | Jul 1999 | A |
| 5949278 | Oguey | Sep 1999 | A |
| 6005374 | Tasdighi | Dec 1999 | A |
| 6054823 | Collings et al. | Apr 2000 | A |
| 6107868 | Diniz et al. | Aug 2000 | A |
| 6122284 | Tasdighi et al. | Sep 2000 | A |
| 6281743 | Doyle | Aug 2001 | B1 |
| 6366071 | Yu | Apr 2002 | B1 |
| 6489831 | Matranga et al. | Dec 2002 | B1 |
| 6657480 | Ochi | Dec 2003 | B2 |
| 6885178 | Marinca | Apr 2005 | B2 |
| 7211993 | Marinca | May 2007 | B2 |
| 7612606 | Marinca | Nov 2009 | B2 |
| 7994848 | Kothandaraman | Aug 2011 | B2 |
| 9519304 | Far | Dec 2016 | B1 |
| 9780652 | Far | Oct 2017 | B1 |
| 9921600 | Far | Mar 2018 | B1 |
| 20020093325 | Ju | Jul 2002 | A1 |
| 20040056708 | Bedarida et al. | Mar 2004 | A1 |
| 20040124822 | Marinca | Jul 2004 | A1 |
| 20050264345 | Ker et al. | Dec 2005 | A1 |
| 20050285666 | Garlapati et al. | Dec 2005 | A1 |
| 20070052473 | McLeod | Mar 2007 | A1 |
| 20070076483 | Colman | Apr 2007 | A1 |
| 20070132506 | Fujisawa et al. | Jun 2007 | A1 |
| 20080018316 | Chang et al. | Jan 2008 | A1 |
| 20080224682 | Haiplik | Sep 2008 | A1 |
| 20080278137 | Harvey | Nov 2008 | A1 |
| 20090243711 | Marinca | Oct 2009 | A1 |
| 20100068767 | Bishop et al. | Mar 2010 | A1 |
| 20100164467 | Jo | Jul 2010 | A1 |
| 20100225384 | Hirose et al. | Sep 2010 | A1 |
| 20100237926 | Kikuta et al. | Sep 2010 | A1 |
| 20110025666 | Baek et al. | Feb 2011 | A1 |
| 20110068767 | Carper | Mar 2011 | A1 |
| 20110102049 | Conte et al. | May 2011 | A1 |
| 20120176186 | Chen et al. | Jul 2012 | A1 |
| 20120323508 | Vilas Boas | Dec 2012 | A1 |
| 20150160680 | Marinca | Jun 2015 | A1 |
| Entry |
|---|
| Samsen, Willy M., “A CMOS Temperature-Compensation Current Reference”, IEEE Journal of Solid-State Circuits, Jun. 1988,p. 821, vol. 23. |
| De La Plaza, Alejandro, “Nanoamperer Supply Independent Low-Voltage Current Reference”, Faible Tension Faible Communication, May 2011, p. 9. |
| Fayomi, Christian, “Sub 1V CMOS bandage reference design techniques a survye”, Analog Integrated Cir Sig Process, Feb. 2010, p. 141. |
| Vittoz, Eric, “A low-Voltage CMOS Bandgap Reference”, IEEE Journal of Solid-State Cirucuits, Jun. 1979, vol. SC-14, No. 3, Feb. 2010, p. 141. |
| Galeano, Edgar, “A Very Low Power Area Efficient CMOS Only Bandgap Reference”, Integrated Circuits and Sys Design, Aug. 2012, p. 1. |
| Osaki, Yuji, “A 95-nA, 523 ppm/C, .6-uW CMOS Current Reference Circuits w/ Subthreshold MOS Resistor Ladder”, ASPDAC '11, Jan. 2011, p. 113. |
| Ueno, Ken, “A 1-uW 600-ppm/C Current Ref Circuits Consiting of Subthreshold CMOS Circuits”, IEEE Transactio on Circits, Sep. 2010, p. 681. |
| De Vita, “A 109 nW, 44 ppm/C CMOS Current Reference with Low Sensitivity to Process Variations”, Curcuits and Systems, Feb. 2007, p. 3804. |
| Ledesma, F., “Comparison of New and Conventional Low Voltage Current Mirrors”, Circuits and Systems, Aug. 2003, p. 49-52. |
| Hirose, Tetsuya, “A Nano-Ampere Current Regerence Circuits and Its Temperature Dependence,” Proceedings of the EECIRC,Oct. 2010, p. 114. |
| Camarcho-Galeano, Edgar, “A 2-nW 1.1V Self-Based Current Reference in CMOS Technology”, On Circuits and System, Feb. 2005,p. 62. |
| Camarcho-Galeano, Edgar, “Temperature Performance of Sub-1V Ultra-Low Power Current Sources”, Circuits and Systems,May 2008, p. 2230. |
| Osaki, “Nano-Ampere CMOS Current Reference with Little Temp. Dependence Using Small Offset Voltage”, Proc. at 53rd IEEE Intl, Aug. 2010, p. 668. |
| Gallegos, S., “A 128.7nW Neural Amplifier and Gm-C Filter for EEG, Using gm/ID Methodology . . . ”, Circuits and Systems, Aug. 2014, p. 876. |
| Cordova, David, “A Low-Voltage Current Reference with High Immunity to EMI”, Integrated Circuits and Systems Design, Sep. 2014, p. 1-6. |
| Annema, Anne-Johan, “Low-Power Bandgap References Featuring DTMOST's”, IEEE Journal of Solid-State Circuits, Jul. 1999, p. 949. |
| Buck, Ame, “A CMOS Bandgap Regerence without Resistors”, Solid-State Circuits Conference, Dec. 2000, p. 442-443. |
| Chouhan, Shailesh, “A modified CMOS Nano-Power Resistorless Current Reference Circuits”,Microelectronics and Electronics,Jun. 2014, p. 1. |
| Guiges, Fabrice, “Sub-1V Oguey's Current Reference Without Resistance”, Circuits and Systems, Dec. 2006, pp. 288-291. |
| Guistolisi,G., “Low-Voltage Low Power Voltage Reference Based on Subthreshold MOSFETS”, Journal of Solid-State Circuits,Jan. 2003, p. 151. |
| Hirose, T., “A CMOS Bandgap and Sub-Bandgap Voltage Reference Circuits for Nanowatt Power LSIs”, IEEE Asian Solid-State,Nov. 2010, p. 77. |
| Kussener, F, “50 nA, 1V Nanowatt Resistor-Free Compact CMOS Current Reference”, Electronics, Circuits and Systems,Dec. 2010, p. 1212. |
| Oguey, H., “CMOS Current Reference Without Reference”, IEEE Journal of Solid-State Circuits, Jul. 1997, p. 1132, vol. 32. |
| Serra-Graelis, F., “Sub-1V CMOS Porportional-to-Absolute Temp. References”Journal of Solid-State Circuits, Jan. 2003, p. 84. |
| Ueno,Ken,“A 300 nW,15 ppm/C,20 ppm/V CMOS Voltage Ref Circuit . . . ”, Journal of Solid-State Circuits, Jun. 2009, p. 2097. |
| VanPetegham, Peter, “On a New CMOS Resistor Implementation for Linear Anlog IC Signal Processing Application,” IEEE, Jun. 1998, p. 163-166. |
| Vittoz, Eric, “CMOS Analog ICs Based on Weak Inversion Operation”, Journal of Solid-State Circuits, Jun. 1977, p. 224. |
| Wilson,G., “Novel Voltage-Controlled Grounded Resistor”, Electronic Letters, Dec. 1989, pp. 1725-1726. |
| Huang, Zhangcai, “A CMOS Sub-1-V Nanopower Current and Voltage Ref with Leakage Compensation”, Circuits and Systems,Jul. 2010, p. 4069. |
| Colombo, Dalton, “A CMOS 25.3 ppm/C Bandgap Voltage Ref using Self-Cascode Composite Transistor”, Circuits and Systems,Apr. 2012, p. 1. |
| Colombo, Dalton. “A CMOS 25.3 ppm/C Bandgap voltage Reterence Using Self-Cascade Composite Transistor”, Circuits and Systems, 2012. |
| A. Far, “Small size class AB amplifier for energy harvesting with ultra low power, high gain, and high CMRR,” 2016 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC), Ixtapa, 2016. pp. 1-5. |
| A. Far, “Compact ultra low power class AB buffer amplifier,” 2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC), Ixtapa, 2017, pp. 1-6. |
| A. Far, “Subthreshold curent reference suitable for energy harvesting: 20ppm/C and 0.1%/V at 140nW,” 2015 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC), Ixtapa, 2015, pp. 1-4. |
| A. Far, “Amplifier for energy harvesting: Low voltage, ultra low current, rail-for-rail input-output, high speed,” 2016 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC), Ixtapa, 2016, pp. 1-6. |
| A. Far, “Class AB amplifier with noise reduction, speed boost, gain enhancement, and ultra low power,” 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), Puerto Vallarta, Mexico, 2018, pp. 1-4. |
| A. Far, “Low noise rail-to-rail amplifier runs fast at ultra low currents and targets energy harvesting,” 2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC), Ixtapa, 2017, pp. 1-6. |
| A. Far, “A 5μW fractional CMOS bandgap voltage and current reference,” 2013 IEEE Global High Tech Congress on Electroics, Shenzhen, 2013, pp. 7-11. |
| A. Far, “A 400nW CMOS bandgap voltage reference,” 2013 International Conference on Electrical, Electronics and System Engineering (ICEESE), Kuala Lumpur, 2013, pp. 15-20. |
| A. Far, “Enhanced gain, low voltage, rail-to-rail buffer amplifier suitable for energy harvesting,” 2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC), Ixpata, 2017, pp. 1-6. |
| A. Far. “Subthreshold bandgap voltage reference aiming for energy harvesting: 100na, 5 ppm/c, 40 ppm/v, psrr-88db,” 2015 IEEE 5th International Conference on Consumer Electronics—Berlin (ICCE—Berlin), Berlin, 2015, pp. 310-313. |
| A. Far, “A 220nA bandgap reference with 80dB PSRR targeting energy harvesting,” 2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), Vancouver, BC, 2016, pp. 1-4. |
| A. Far, “Sub-1 volt class AB amplifier with low noise, ultra low power, high-speed, using winner-take-all,” 2018 IEEE 9th Latin American Symposium on Circuites & Systems (LASCAS), Puerto Vallarta, Mexico, 2018, pp. 1-4. |
| A. Far, “A low supply voltage 2μW half bandgap reference in standared sub-μ CMOS,” 2014 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, 2014, pp. 1-5. |
| A. Far, “Current reference for energy havrvesting: 50um per side, At 70nW, regulating to 125C,” 2014 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC), Ixtapa, 2014, pp. 1-5. |
| J. Mu, L. Liu, Z. Zhu and Y. Yang, “A 58-ppm/° C. 40-nW BGR at Supply From 0.5 V from Energy Harvesting IoT Devices,” In IEEE Tranactions on Circuits and Systems II: Express Briefs, vol. 64, No. 7, pp. 752-756, Jul. 2017, doi: 10.1109/TCSII.2016.2602875. |
| Z. Zhou et al., “A Resistorless High-Precision Compensated CMOS Bandgap Voltage Regerence,” in IEEE Transactions on Circuits and Systems I: Regular Papers. doi: 10.1109/TCSI.2018.2857821. |
| J. Chen, X. Ni, B. Mo and Z. Wang, “A High Precision Curvature Compensated Bandgap Reference without Resistors,” 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, Shanghai, 2006, pp. 1748-1750, doi: 10.1109/ICSICT.2006.306414. |
| V. R. Campana, H. Klimach and S. Bampi, “Nano-watt 0.3 V supply resistorless voltage reference with Schottky diode,” 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), Florianopolis, 2016, pp. 175-178. doi: 10.1109/LASCAS.2016.7451038. |
| H. Klimach, M. F. C. Monteiro, A. L. T. Costa and S. Bampi, “A resistorless switched bandgap reference topology,” 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), Cusco, 2013, pp. 1-4. doi: 10.1109/LASCAS.2013.6519026. |
| V. R. Campana, H. Klimach and S. Bampi, “Nano-watt 0.3 V supply resistorless voltage reference with Schottky diode.” 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), Florianopoils, 2016, pp. 175-178. doi: 10.1109/LASCAS.2016.7451038. |
| V. R. Campana, H. Klimach and S. Bampi, “0.5 V supply resistorless voltage reference for low voltage applications,” 2015 28th Symposium on Integrated Circuits and Systems Design (SBCCI), Salvador, 2015, pp. 1-6. |
| W. Tam, K. Mok, O. Wong, C. Kok and H. Wong, “High-Performance Resistorless Sub-1V Bandgap Reference Circuit Based on Piecewise Compensation Technique,” 2007 IEEE Conference on Electron Devices and Solid-State Cirucuits, Tainan, 2007, pp. 373-376. doi: 10.1109/EDSSC.2007.4450140. |
| O. E. Mattia, H. Kilmach and S. Bampi, “0.9 V, 5nW. 9 ppm/oC resistorless sub-bandgap voltage reference in 0.18μm CMOS,” 2014 IEEE 5th Latin American Symposium on Circuits and Systems, Santiago, 2014, pp. 1-4. DOI: 10.1109/LASCAS.2014.6820273. |
| A. Tekin, E. Zencir, D. Huang, N. S. Dogan, M. Katel, and E. Arvas, “A bias circuit based on resistorless bandgap reference in 035 spl mu/m SOI CMOS,” 2003 46th Midwest Symposium on Circuits and Systems, Cairo, 2003, pp. 149-152 vol. 1. doi: 10.119/MWSCAS.2003.1562240. |
| O. E. Mattia, H. Klimach and S. Bampi, “Resistorless BJT bias and curvature compensation circuit at 3.4 nW for CMOS bandgap voltage reference,” in Electronics Letters, vol. 50, No. 12, pp. 863-864, Jun. 5, 2014. doi: 10.1049/el.2013.3417. |
| I. Fakharyan and M. Ehsanian, “A sub-1V nanowatt CMOS bandgap voltage reference with temperature coefficient of 13ppm/° C.,” 2015 23rd Iranian Conference on Electrical Engineering, Tehran, 2015, pp. 1129-1132. doi: 10.1109/IranianCEE.2015.7146382. |
| D. M. Colombo, T. M. de Brito and F. V. A. Coimbra, “An approach a new 1 V supply resistorless voltage reference using Schottky diode,” 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), Puerto Vallarta, 2018, pp. 1-4. doi: 10.1109/LASCAS.2018.8399955. |
| F. Dumitru, Ş. Mihalache and G. Brezeanu, “A CMOS resistorless bandgap reference with minimized current consumption,” 2015 International Semiconductor Conference (CAS), Sinata, 2015, pp. 289-292, doi: 10.1109/SMICND.2015.7355235. |
| K. Jaafar, N. Kamal, M. Bin Ibne Reaz and J. Sampe, “Resistorless self-biased curvature compensated sub-1V CMOS bandgap reference,” 2016 International Conference on Advances in Electrical Electronic and Systems Engineering (ICAEES), Putrajaya, 2016, pp. 309-312. doi: 10.1109/ICAEES.2016.7888059. |
| Z. Zhao, S. Huang and F. Zhou, “A novel CMOS current reference with low temperature coefficient over a large temperature range,” 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, 2010, pp. 415-417. doi: 10.1109/ICSICT.2010.5667695. |
| W. Yang, Z. Huang, C. Cheng and Y. Lo, “Temperature insensitive current reference for the 6.27 MHz oscillator,” 2011 International Symposium on Integrated Circuits, Singapore, 2011, pp. 559-562. doi: 10.1109/ISICir.2011.6131924. |
| B. Yang, Y. Shin, J. Lee, Y. Lee and K. Ryu, “An accurate current reference using temperature and process compensation current mirror,” 2009 IEEE Asian Solid-State Circuits Conference, Taipei, 2009, pp. 241-244. doi: 10.1109/ASSCC.2009.5357223. |
| S. Toofan and A. Tajari, “A temperature-compensated current source with high output impedance,” 20th Iranian Conference on Electrical Engineering (ICEE2012), Tehran, 2012, pp. 109-112. doi: 10.1109/IranianCEE.2012.6292334. |
| Y. Osaki, T. Hirose, N. Kuroki and M. Numa, “Nano-ampere CMOS current reference with little temperature dependence using small offset voltage,” 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, Seattle, WA, 2010, pp. 668-671. doi: 10.1109/MWSCAS.2010.5548916. |
| T. Nagayama, T. Hirose, Y. Osaki, N. Kuroki nand M. Numa, “A 105-nW CMOS thermal sensor for power-aware applications,” SENSORS, 2011 IEEE, Limerick, 2011, pp. 1265-1268. doi: 10.1109/ICSENS.2011.6127039. |
| C.-Lee adn H.-Park, “All-CMOS temperature independent current reference,” in Elecronics Letters, vol. 32, No. 14, pp. 1280-1281, Jul. 4, 1996, doi: 10.1049/el.19960827. |
| G. De Vita and G. Iannaccone, “A 109 nW, 44 ppm/° C CMOS Current Reference with Low Sensitivity to Process Variations,” 2007 IEEE International Symposium on Circuits and Systems, New Orleans, LA, 2007, pp. 3804-3807. doi: 10.1109/ISCAS.2007.378790. |
| U. Denier, “Analysis and Design of an Ultralow-Power CMOS Relaxation Oscillator,” in IEEE Tranactions on Circuits and Systems I: Regular Papers, vol. 57, No. 8, pp. 1973-1982. Aug. 2010, doi: 10.1109/TCSI.2010.2041504. |
| D. Cordova, P. Toledo and E. Fabris, “A low-voltage current reference with hgih immunity to EMI,” 2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI), Aracaju, 2014, pp. 1-6. doi: 10.1145/2660540.2660989. |
| G. Chen, B. Yang, S. Nakatake, Z. Huang and Y. Inoue, “A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model,” IEEE International Symposium on Circuits and Systems, Seoul, 2012, pp. 938-941. doi: 10.1109/ISCAS.2012.6272199. |
| S. S. Bethi, K. Lee, R. Veilletle, J. Carletta and M. Willett, “A temperature and process insensitive CMOS reference current generator,” 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, 2013, pp. 301-304. doi: 10.1109/MWSCAS.2013.6574645. |
| C. Aznona, B. Calvo, S. Celma, N. Medrano and M. T. Sanz, “Precision CMOS current reference with process and temperature compensation,” 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, 2014, pp. 910-913 doi: 10.1109/ISCAS.2014.8665284. |
| P. Vajpayee, A. Srivastava, S. S. Rajput and G. K. Sharma, “Low voltage regulated cascade current mirrors suitable for sub-1V operation,” 2010 IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, 2010, pp. 584-587. doi: 10.1109/APCCAS.2010.5774891. |
| D. Schmitt and T. S. Fiez, “A low voltage CMOS current source,” Proceedings of 1997 International Symposium on Low Power Electronics and Design, Monterey, CA, USA, 1997, pp. 110-113. doi: 10.1145/263272.263301. |
| Fayomi, C.J., “Sub 1 V CMOS bandgap reference design techniques: a survey.” Journal Analog Integrated Circuits and Signal Processing archive, vol. 82, Issue 2, pp. 141-157, Feb. 2010. DOI: 10.1007/s10470-009-9352-4. |
| Kussener, E. at al “50 nA, 1 V nanowatt resistor-free compact CMOS current references,” Electronics Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, vol., No., pp. 1212,1215, Dec. 12-15, 2010, DOI: 10.1109/ICECS.2010.5724736. |
| E. M. Camacho-Galeano, C. Galup-Montoro end M. C. Schneider, “A 2-nW 1.1-V self-biased current reference in CMOS technology,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 52, No. 2, pp. 61-65, Feb. 2005. doi: 10.1109/TCSII.2004.842059. |
| K. Ueno, T. Hirose, T. Asai and Y. Amemiya, “A Current Reference Circuit Consisting of Subthreshold CMOS Circuits,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, No. 9, pp. 681-685, Sep. 2010. doi: 10.1109/TCSII.2010.2056051. |
| H. J. Oguey and D. Aebischer, “CMOS current reference without resistance ” in IEEE Journal of Solld-Stale Circuits, vol. 32, No. 7, pp. 1132-1135, Jul. 1997. doi: 10.1109/4.597305. |
| Serra-Graells, F. et al, “Sub-1-V CMOS proportional-to-absolute temperature references,” Solid-State Circuits, IEEE Journal of , vol. 38, No. 1, pp. 84,88, Jan. 2003 doi: 10.1109/JSSC.2002.806258. |
| Number | Date | Country | |
|---|---|---|---|
| 62129002 | Mar 2015 | US | |
| 62126588 | Feb 2015 | US | |
| 62060193 | Oct 2014 | US | |
| 62022820 | Jul 2014 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15375170 | Dec 2016 | US |
| Child | 15925721 | US | |
| Parent | 14795862 | Jul 2015 | US |
| Child | 15375170 | US |
