Embodiments of the subject matter disclosed herein generally relate to an antenna-on-chip system, and more particularly, to an ultra-thin, artificial magnetic conductor for gain-enhancement of the antenna-on-chip.
Wireless System-on-Chip (SoC), where all functional modules are integrated on a single chip, has attracted considerable research interest with the advantages of high-level integration, low power consumption, and low cost. Typically, the antenna is the largest part of such a wireless system, and previously it was not feasible to integrate it on the chip due to its large size. Note that in order to integrate a given system on a chip, each component of the system needs to have a height lower than a certain threshold, where the threshold depends on the chosen manufacturing process and the machine that manufactures the system. However, due to the push towards millimeter-wave spectrum, antenna sizes have dropped to the order of millimeters and thus, they become compatible with the typical chip dimensions [1-3]. On the other hand, silicon (Si) based semiconductor technologies, such as the Complementary Metal Oxide Semiconductor (CMOS) process, has come a long way and thus high-frequency circuits and antennas can be realized on a single chip in a compact fashion [4].
Although the size of the mm-wave Antenna-on-Chip (AoC) has become compatible with the typical CMOS chip dimensions, the CMOS stack-up is still not favorable for AoC implementation. This is mainly because of the very conductive Si substrate, which also has a very high permittivity. Further, the embedded metal layers in a very thin silicon dioxide (SiO2) (˜10-15 μm) are not very suitable for AoC implementation, particularly for lower GHz frequencies. Around six to nine metal layers are available in the SiO2 with interconnected-vias in a typical CMOS stack-up. The high relative permittivity of Si (εr=11.9) attracts most of the antenna fields towards the substrate instead of being radiated in the air. Further, the low resistivity (˜10 Ω-cm) of the Si substrate causes the loss of power in the Si substrate as heat. The poor radiation performance of the AoC is due to both the high permittivity and conductivity of the Si substrate. In addition, the Si substrate thickness (300-700 μm) is also electrically large (particularly for mm-wave frequencies). Thus, surface wave modes get excited, which leads to the distortion of the radiation pattern, which is undesired.
To improve the AoC radiation performance, two approaches have been reported extensively in the literature [5-8]. The first one involves incorporating off-chip microwave lenses or superstrates. For instance, in [5], the gain of a 77 GHz on-chip dipole antenna has been boosted by 10 dB through the use of a hemispherical lens. In [6], a high-contrast superstrate has been placed above the AoC, which leads to a boresight gain improvement by 4.5 dB. In a second approach, either the lossy Si substrate is removed underneath the AoC or its properties are modified. For example, in [7], the Si beneath the AoC has been etched through micromachining and a gain of 4 dBi is achieved at 85 GHz. Similarly, in [8], the Si resistivity has been selectively enhanced by Helium-3 ion irradiation, resulting in an improvement in radiation efficiency by 43%.
However, these methods are incompatible with CMOS processes and require complex post-fabrication steps, which not only increases the overall cost, but also adds alignment uncertainty and mechanical stability issues.
Alternatively, the Artificial Magnetic Conductors (AMC) system, which is a metamaterial, can be employed to isolate the substrate and provide constructive reflection for the gain enhancement of the AoC. A conventional implementation of the AMC is to place a ground plane 120 underneath the silicon substrate 122 because of the thickness limitation of the SiO2 layer 124, as shown in
A better solution is to fully isolate the lossy Si substrate 122 by realizing the AMC ground plane 120 above the Si substrate, as shown in
Another issue that affects the efficiency of AoC is the presence of thin adhesion layers (10 nm titanium or chromium) that are employed to provide good adhesion to the main metal layers (copper or gold). The surface resistance of these adhesion layers is large because of the skin effect, and thus, the traditional AoC suffers from undesired ohmic losses.
These two issues related to the AoC, i.e., fitting the AMC in conventional SiO2 thickness to completely isolate lossy Si substrates, and avoiding the ohmic loss due to the adhesion layers, need to be overcome by a new AoC system, which is now discussed.
According to an embodiment, there is an antenna-on-chip, AoC, system that includes a substrate base, an artificial magnetic conductor, AMC, system with embedded guiding structures, EGS, the AMC system being located on the substrate base, and an antenna located onto the AMC system. The EGS are electrically floating within the AMC system.
According to another embodiment, there is an antenna-on-chip, AoC, system that includes a substrate base, an artificial magnetic conductor, AMC, system with embedded metallic poles, MPs, the AMC system being located on the substrate base, and an antenna located onto the AMC system. The MPs are electrically connected to a metallic ground plane of the AMC system.
For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The following description of the embodiments refers to the accompanying drawings. The same reference numbers in different drawings identify the same or similar elements. The following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims. The following embodiments are discussed, for simplicity, with regard to an AoC implemented with a SiO2 layer having a given thickness. However, the embodiments to be discussed next are not limited to a SiO2 layer or only to the given thickness, but may be applied to other layers having different thicknesses.
Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with an embodiment is included in at least one embodiment of the subject matter disclosed. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification is not necessarily referring to the same embodiment. Further, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.
According to an embodiment, a thickness of an AoC system fits the CMOS requirements by using either Metallic Posts (MPs) or Embedded Guiding Structures (EGS) in the SiO2 layer, to force the electromagnetic radiation to take a longer path before being emitted outside the device. An attempt to introduce MPs by employing the vias in the stack-up semiconductor device, thereby reducing the AMC thickness, has been tried by the present inventors in [10], without providing the working principle and comprehensive parametric analysis of the approach. The MPs behave as slow-wave structures, which affect the phase velocity and consequently helps in AMC thickness reduction. Furthermore, another novel thickness reduction structure (TRS), which works the available metal layers into the EGS, is discussed in another embodiment herein. The EGS modifies the path of electric fields inside the AMC, making the AMC look electrically thicker. In contrast, the EGS provides more thickness miniaturization as compared to the MP approach. A 16 μm ultra-thin AMC system is realized with a gain improvement of 9.15 dB as compared to a standalone antenna as discussed later in more detail. During the fabrication of these devices, adhesion layers have been completely omitted so ohmic losses due to them have been avoided, without losing the required adhesion for the main metal layers. The measured AoC gain is one of the highest in the literature that has been achieved without off-chip components or post-fabrication processes. More details about these two approaches are now provided.
On-chip antennas are mostly designed to be horizontally placed on the top metal layer of the stack-up (also called “chip,” or “semiconductor device” or “AoC system” herein). This is because the top metal layer allows larger metal thickness, which is beneficial for antenna's performance and also this arrangement enables the antenna to radiate directly into the air. The radiation performance of a horizontally placed antenna could be enhanced by a Perfect Magnetic Conductor (PMC) surface that can produce an image current in the same direction. Since the PMC surfaces do not exist in nature, AMC surfaces are developed to mimic the effect of the PMC for a certain frequency range. As discussed above with regard to
To isolate the silicon substrate 122 completely from the antenna, the ground plane 120 of the AMC system is located on the top of the silicon substrate 122, as shown in
To determine the reflection and isolation performance of the reference AMC system 200, a planar monopole antenna 220 is placed on top of the AMC 200, as shown in
For the AMC system to work properly at 94 GHz, a SiO2 layer thickness of 27 μm is required, as has been previously determined through EM simulations. This thickness requirement is too high for the stack-up of current CMOS processes as a thickness of only 18 μm is permitted. Therefore, thickness miniaturization techniques need to be introduced in the AMC system design to reach an acceptable oxide thickness, i.e., less than 18 μm. Two kinds of thickness reduction structures (TRS) are introduced now and investigated for a single AMC unit cell as well as the 4×4 finite AMC-backed AoC system.
The first TRS structure uses the MPs embedded into the SiO2 layer 124. For a conventional patch-based AMC system, the equivalent model includes a capacitance Co with a shunt inductance Lo, where the Co is the capacitance between adjacent patches, while Lo refers to the inductor due to the backside ground plane, as shown in
Through this additional reactance, the phase velocity is reduced, and equivalently, the electrical thickness of the AMC structure is increased. Considering the ohmic losses proportional to the metal volume in each AoC system, the loss resistance would be quite large if too many vias are introduced. Therefore, in an AoC system 900 design, two vias that originate from the ground plane, but are not connected with the patch, are used to form the MPs 910-1 and 910-2 shown in
The effect of the geometrical parameters of the metallic posts 910-1 and 910-2 on the AMC system's resonance frequency fAMC was conducted to achieve the best results. Typically, the via size (diameter if the via is cylindrical or a side if a square) lp is often a fixed value, but the degrees of freedom for its design are its height, hp, and its location, gp on the surface of the ground plane 120. Note that the MPs 910-1 and 910-2 are physically and electrically connected to the ground plane 120, but not to the patch 121, and they are shorter than a thickness of the SiO2 layer 124. Also note that the antenna 220 is placed directly on top of the SiO2 layer 124, but not to electrically connect to the MPs. To investigate the effect of these design parameters of the MPs on the AMC system's resonance frequency, the values of lp and tAMC are fixed as 6.7 and 13 μm respectively.
In
Next, the MP's height hp is varied from 1 to 10.5 μm while keeping the gp at 73 μm. The results shown in
From the results of the parametric sweep shown in
Next, the approach in which EGS structures are embedded in the SiO2 layer is discussed. The EGS structures, which can be plural planes made of metal, are electrically floating in the SiO2 film, i.e., they are not electrically connected to any element of the semiconductor device. A stack-up 1100 of a standard CMOS process provides about six to nine metal layers inside the oxide layer. These metal layers are embedded in the dielectric part of the AMC system 1102, and can be smartly used to reduce its resonance frequency. As
To determine the effect of the embedded guiding structure's parameters on the AMC system's thickness reduction, a parametric sweep of each geometrical parameter of the embedded structures is considered. The AMC system thickness tAMC is 13 μm in this embodiment. Considering fabrication limitations of the in-house CMOS-compatible process, the gap between the structures and the unit edge gg is varied from 5 to 45 μm, the height of the structures hg is selected from 1 to 10.5 μm, the length of the structures lg is tuned from 200 to 390 μm, and the width wg is varied from 50 to 250 μm.
According to
The fAMC in
The EGS 1110 may be introduced in a 4×4 finite patch-based AMC system 1100, as shown in
A monopole antenna 220 has been placed above the AMC with EGS system 1102, as shown in
Conventionally, the vias in the chip are used to connect multiple metal layers in the CMOS stack-up. However, in these embodiments, the vias and metal layers have been utilized to reduce the thickness of the AMC system and not to transfer data or signals among the various components of the semiconductor device. Two finite AMC structures implemented with different TRS (see AMC system 902 in
To compare the AMC systems discussed above, an identical monopole antenna 220 was placed 2.5 μm above the AMC systems with MP 902 and EGS 1102, respectively. Table II in
Compared to the reference AMC system (shown in
A method for fabricating the AMC system 1102 without any adhesive layers is now discussed. The on-chip monopole antenna backed by a 4×4 thin AMC with EGS system 1102 is selected for fabrication as it exhibits the highest gain for the thinnest oxide layer. During the deposition of the patterned metal layer, specialized adhesion layers, composed of chromium or titanium, are always used in a typical fabrication process. This is to improve the adhesion of the metals (copper or gold) to the oxide. The usage of the adhesion films helps the buildup of noble metal in device fabrication, but it reduces the average conductivity of metal layers and negatively affects the AMC and antenna radiation. It is noted that when an extremely thin AMC thickness is required, the resistance corresponding to the conductor loss plays a significant role that could affect the zero-degree reflection phase property by causing PEC-like effect in the AMC system. It is observed that a 10 nm chromium film modelled at the lower surface of each copper layer as the adhesion layer, causes the antenna gain to reduce to −24.6 dBi and radiation efficiency to less than 0.1%. To study the effect of the adhesion layer thickness on the AoC radiation, the copper layer is fixed as 500 nm, while the thickness of the chromium adhesion film is varied from 10 to 250 nm. According to the simulated results, the peak gain shows a direct proportionality to the thickness of the chromium film. This is because the surface resistance is inversely proportional to the chromium film thickness when it is much thinner than the skin depth of chromium (595 nm at 94 GHz). Therefore, the conduction loss caused by the adhesion films decreases while the chromium thickness increases. Nevertheless, the gain is still not ideal even if the chromium thickness reaches 250 nm. Therefore, to realize an AoC that exhibits the enhanced gain and radiation performance as proposed in simulations, the adhesion layers need to be omitted, but certain modifications to the fabrication process are required to help the copper layers still bond adequately to the oxide.
An AoC system 1902 including the monopole antenna 220 backed by ultra-thin AMC with EGS system 1102 is depicted in
To maintain the copper layer on SiO2 without the adhesion layer deposition, two objectives are considered. On one hand, it is desired to improve the adhesion of the copper to the oxide layer, while on the other hand, during the lift-off step of the lithography, the solvent needs to easily contact the residual photoresist, thereby preventing the patterned copper from exfoliation, which would be caused by conventional intensive ultrasonic lift-off. To achieve these objectives, prior to the lithography step, the bombardment of argon atoms can make the surface of SiO2 rough, thereby enhancing the friction force of the oxide layer to the copper and consequently improving their adhesion. After that, the wafer is coated with AZ 5214 image reversal photoresist whose ideal thickness is 1.6 μm, slightly larger than thrice of the thickness of the copper film. Then, the solidified photoresist is treated by dark-mask-covered exposure and the area, except for the intended pattern, is exposed. Next, the reversal baking with temperature condition (120° C. for two minutes) and flood exposure makes the unexposed intended pattern area developable. After development, such a slanting wall can be found that the lift-off step turns out to be gentle due to the accessibility of the residual photoresist to the solvent.
The input impedance and radiation performance of the system 1902 has been analyzed with a vector network analyzer (VNA). The simulated and measured reflection coefficients of the antenna were found to be in fair agreement for in-band response. It was also found that the on-chip monopole antenna is well matched from 92 to 98 GHz with a return loss of 16 dB at 94 GHz. The radiation performance has been characterized. Due to the physical constraints of the measuring chamber, the E-plane measurement of the antenna ranges from θ=−20° to 230° while φ=−90°, and H-plane is θ=0° to 360° while φ is zero. Generally, the measured curves follow the same trends as the simulated curves. The H-plane pattern is almost matched to the simulated curve except a backside radiated lobe, while there are several additional side lobes measured in the E-plane. The measured peak gain is also in fair agreement with the simulated results, showing an initial rise followed by a drop, in the impedance-matched frequency band (92 to 98 GHz). The highest value of the realized gain occurs at 94 GHz as 5.85 dBi, which is close to the gain value of 5.08 dBi in simulations. The 3 dB gain bandwidth is 5.4%. Furthermore, to characterize the directivity D and radiation efficiency η of the system 1902, the spherical radiation pattern, with the exception of the probe part (φ=−30° to +30°, θ=20° to 130°), has been measured with an azimuth step of 5° and the inclination step of 2°. The directivity has been found to be 8.22 dB and the radiation efficiency is 57%.
Table IV in
The disclosed embodiments provide an AoC system that uses AMC with EGS for reducing the thickness of the AMC such that the AoC is compatible and fits CMOS standards. It should be understood that this description is not intended to limit the invention. On the contrary, the embodiments are intended to cover alternatives, modifications and equivalents, which are included in the spirit and scope of the invention as defined by the appended claims. Further, in the detailed description of the embodiments, numerous specific details are set forth in order to provide a comprehensive understanding of the claimed invention. However, one skilled in the art would understand that various embodiments may be practiced without such specific details.
Although the features and elements of the present embodiments are described in the embodiments in particular combinations, each feature or element can be used alone without the other features and elements of the embodiments or in various combinations with or without other features and elements disclosed herein.
This written description uses examples of the subject matter disclosed to enable any person skilled in the art to practice the same, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the subject matter is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims.
The entire content of all the publications listed herein is incorporated by reference in this patent application.
This application claims priority to U.S. Provisional Patent Application No. 63/216,136, filed on Jun. 29, 2021, entitled “NOVEL TECHNIQUE FOR ON-CHIP ARTIFICIAL MAGNETIC CONDUCTOR THICKNESS REDUCTION,” the disclosure of which is incorporated herein by reference in its entirety.
Entry |
---|
Q. Liu, A. J. van den Biggelaar, U. Johannsen, M. C. van Beurden and A. B. Smolders, “On-Chip Metal Tiling for Improving Grounded mm-Wave Antenna-on-Chip Performance in Standard Low-Cost Packaging,” in IEEE Transactions on Antennas and Propagation, vol. 68, No. 4, pp. 2638-2645, Apr. 2020 (Year: 2020). |
Babakhani, A., et al., “A 77-GHz Phased-Array Transceiver with On-Chip Antennas in Silicon: Receiver and Antennas,” IEEE Journal of Solid-State Circuits, Dec. 2006, vol. 41, No. 12, pp. 2795-2806. |
Cheema, H., et al., “The Last Barrier: On-Chip Antennas,” IEEE Microwave Magazine, Jan./Feb. 2013, vol. 14, No. 1, pp. 79-91, 2013. |
Cook, B.S., et al., “Utilizing Wideband AMC Structures for High-Gain Inkjet-Printed Antennas on Lossy Paper Substrate,” IEEE Antennas and Wireless Propagation Letters, Jan. 15, 2013, vol. 12, pp. 76-79. |
Hirano, T., et al., “Design of 60 GHz CMOS On-Chip Dipole Antenna with 50 % Radiation Efficiency by Helium-3 Ion Irradiation,” in 2015 IEEE Conference on Antenna Measurements & Applications (CAMA), Nov. 30-Dec. 2, 2015, pp. 1-2. |
Johannsen, U., et al., “Antenna-on-Chip Integration in Mainstream Silicon Semiconductor Technologies,” 12th European Conference on Antennas and Propagation (EuCAP 2018), Apr. 9-13, 2018, pp. 1-5. |
Karim, R., et al., “Performance-Issues-Mitigation-Techniques for On-Chip-Antennas—Recent Developments in RF, MM-Wave, and Thz Bands With Future Directions,” IEEE Access, Dec. 7, 2020, vol. 8, pp. 219577-219610. |
Karim, R., et al., “The Potentials, Challenges, and Future Directions of On-Chip-Antennas for Emerging Wireless Applications—A Comprehensive Survey,” IEEE Access, Dec. 2, 2019, vol. 7, pp. 173897-173934. |
Nafe, M., et al., “Gain-Enhanced On-Chip Folded Dipole Antenna Utilizing Artificial Magnetic Conductor at 94 Ghz,” IEEE Antennas and Wireless Propagation Letters, Sep. 5, 2017, vol. 16, pp. 2844-2847. |
Seyyed-Esfahlan, M., et al., , “SiGe Process Integrated On-Chip Dipole Antenna on Finite-Size Ground Plane,” IEEE Antennas and Wireless Propagation Letters, Sep. 20, 2013, vol. 12, pp. 1260-1263. |
Yu, Y., et al., “Ultra-Thin Artificial Magnetic Conductor with Metallic Posts for a 94 GHz On-chip Antenna,” in 2021 International Applied Computational Electromagnetics Society Symposium (ACES), Aug. 1-5, 2021, pp. 1-3. |
Zhang, H., et al., “Gain Enhancement of Millimeter-Wave On-Chip Antenna Through an Additively Manufactured Functional Package,” IEEE Transactions on Antennas and Propagation, Jun. 2020, vol. 68, No. 6, pp. 4344-4353. |
Number | Date | Country | |
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20220416441 A1 | Dec 2022 | US |
Number | Date | Country | |
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63216136 | Jun 2021 | US |