Clevenger et al., A Novel Low Temperature CVD/PVD A1 Filling Process for Producing Highly Reliable 0.175/spl mu/m Wiring/0.35 spl mu/m Pitch Dual Damascene Interconnections in Gigabit Scale Drams, Jun. 1-3, 1998, pp. 137-139, Interconnect Technology Conference, 1998, Proceedings of the IEEE 1998 International. |
Lakshminarayanan et al., Contact and Via Structures With Copper Interconnects Fabricated Using Dual Damascene Technology, Aug. 1994, pp. 306-309, IEEE Electron Device Letters, vol. 15, Issue 8. |
Liu et al., Single Mask Metal—Insulator—Metal (MIM) Capacitor With Copper Damascene Metallization For sub-0.18/spl mu/m Mixed Mode Signal and System-on-a-Chip (SoC) Applications, Jun. 5-7, 2000, pp. 110-113, Interconnect Technology Conference, 2000, Proceedings of the IEEE 2000 International. |
Mahnkopf et al., System on a Chip Technology Platform For 0.18/spl mu/m Digital, Mixed Signal and eDRAM Applications, Dec. 5-8, 1999, pp. 848-852, Electron Devices Meeting, 1999, IEDM Technical Digest International. |