The bandgap of III-nitride materials, including (Al, Ga, In)—N and their alloys, extends from the very narrow gap of InN (0.7 eV) to the very wide gap of AlN (6.2 eV), making III-nitride materials highly suitable for optoelectronic applications such as light emitting diodes (LEDs), laser diodes, optical modulators, and detectors over a wide spectral range extending from the near infrared to the deep ultraviolet. Visible light LEDs and lasers can be obtained using InGaN in the active layers, while ultraviolet LEDs (UVLEDs) and lasers require the larger bandgap of AlGaN.
UVLEDs with emission wavelengths in the range of 230-350 nm are expected to find a wide range of applications, most of which are based on the interaction between UV radiation and biological material. Typical applications include surface sterilization, air disinfection, water disinfection, medical devices and biochemistry, light sources for ultra-high density optical recording, white lighting, fluorescence analysis, sensing, and zero-emission automobiles.
The extraction efficiency from such UVLEDs is often undesirably low.
Though the devices described herein are III-nitride devices, devices formed from other materials such as other III-V materials, II-VI materials, Si are within the scope of embodiments of the invention. The devices described herein may be configured to emit visible, UV A (peak wavelength between 340 and 400 nm), UV B (peak wavelength between 290 and 340 nm), or UV C (peak wavelength between 210 and 290 nm) radiation. The radiative power emitted by the UVLEDs described herein may be described as “light” for economy of language.
Embodiments of the invention are directed to structures and techniques for increasing the extraction efficiency from UVLEDs.
Mount 40 may be any suitable material that is highly thermally conductive (for example, with a thermal conductivity of at least 170 W/mK in some embodiments), highly electrically insulating, and mechanically rigid (for example, with a coefficient of thermal expansion that matches or is close to that of UVLED 1). Examples of suitable materials for mount 40 include but are not limited to ceramic, diamond, AN, beryllium oxide, silicon or electrically conductive material such as silicon, metal, alloy, Al, or Cu, provided the electrically conductive material is appropriately coated with an insulating layer such as silicon oxide, silicon nitride or aluminum oxide, or any other suitable material. In some embodiments, circuitry and/or other structures such as transient voltage suppression circuitry, driver circuitry, or any other suitable circuitry may be disposed within mount 40, or mounted on a surface of mount 40, such that the circuitry or other structures are electrically connected to UVLED 1, if necessary.
Conductive pads 42 are formed on the top surface of the mount. UVLED 1 is electrically and physically connected to mount 40 through pads 42. At least two electrically isolated pads 42 are provided per UVLED 1, one coupled to the n-type region of the UVLED 1 and one coupled to the p-type region of the UVLED 1. Pads 42 may be, for example, any material that is suitable for bonding UVLED 1 including, for example, gold, silver, tin-silver-copper (SAC), or gold-tin (AuSn). Pads 42 may be formed on the surface of mount 40 by any suitable technique including, for example, plating.
The contacts of UVLED 1 (described below) are connected to pads 42 by an interconnect 46, which may be any suitable material such as, for example, solder or gold. UVLED 1 may be connected to pads 42 by any suitable technique including, for example, gold-gold interconnection, soldering, or flux-assisted eutectic reflow techniques.
The area on the mount 40 surrounding UVLED 1 is coated with a reflective layer 44. Reflective layer 44 is a material that is highly reflective to the radiative power emitted by UVLED 1. Reflective layer 44 may be any suitable material including, for example, a metal, aluminum, multi-layer metal stacks, alloys, or reflective particles such as Polytetrafluoroethylene (PTFE, which may be known by the trade name Teflon®) or aluminum oxide disposed in a transparent material, such as UV-resistant silicone. Reflective layer 44 is at least 70% reflective of radiative power with wavelengths between 250 and 350 nm in some embodiments, and at least 85% reflective of radiative power with wavelengths between 250 and 350 nm in some embodiments.
A metal reflective layer 44 such as aluminum may be formed by, for example, plating, electron beam deposition, or evaporation. Reflective layer 44 may be a metal stack. For example, one or more layers that facilitate adhesion of the metal reflective layer 44 to the underlying surface (for example, a surface of mount 40 and/or a surface of pads 42) may be formed prior to metal reflective layer 44. Examples of such adhesion layers include nickel, titanium, or alloys thereof. One example of a suitable metal stack is 100 nm Ti disposed in direct contact with the underlying surface, followed by 500 nm Al. The metal stack may be formed by any suitable technique. In one embodiment, the metal stack can be formed by e-beam deposition, and the pattern can be formed by a photoresist lift-off process as is known in the art.
A reflective layer 44 that is reflective particles disposed in a transparent material may be formed by, for example, dispensing, molding, stencil printing, screen printing, or any other suitable technique. Reflective particles may be Al2O3, polytetrafluoroethylene (PTFE), or Al, disposed in silicone or any other suitable material that is low index, UV-resistant, and transparent to light between for example 250 nm and 350 nm. In some embodiments, the transparent material is electrically insulating. In some embodiments, the difference in refractive index between the particles and the transparent material causes scattering of light incident on the reflective layer 44. For example, commercially available UV-suitable silicone (such as, for example, Schott UV-200) may have a refractive index of no more than 1.42. Al2O3 particles may have a refractive index of 1.8. The difference between 1.42 and 1.8 may cause suitable scattering. The particles may be micron sized or nanometer sized.
Reflective layer 44 may improve extraction from the device illustrated in
An optical element such as a lens 46 is disposed over the UVLED 1. Though a dome lens is illustrated in
In some embodiments, the height of lens 46 at the tallest point is kept small to maintain transparency. The height of the tallest point of lens 46 relative to the top surface of reflective layer 44 may be at least 50 μm in some embodiments, no more than 1 mm in some embodiments, no more than 750 μm in some embodiments, and no more than 500 μm in some embodiments. In some embodiments, rather than a lens designed to alter the beam of extracted light, optical element 46 may be a clear sheet of material, such as a quartz plate, that protects UVLED 1 without significantly altering the beam of extracted light.
Bond pads 47 may be formed on the top surface of the mount, to facilitate electrical connection between UVLED 1 and another structure. Bond pads 47 must be electrically connected to pads 42. If reflective layer 44 is conductive (such as, for example, aluminum), bond pads may be formed on reflective layer 44.
Commercially available UVA, UVB, and UVC LEDs may be used in the various embodiments.
The UVLEDs are typically III-nitride, and commonly GaN, AlGaN, and InGaN. The array of UV emitting pixels 12 is formed on a single substrate 14, such as a transparent sapphire substrate. Other substrates are possible. Although the example shows the pixels 12 being round, they may have any shape, such as square. The light escapes through the transparent substrate, as shown in
Semiconductor layers are epitaxially grown over the substrate 14. (The device may include one or more semiconductor layers, such as conductive oxides such as indium tin oxide, that are not epitaxially grown, but are deposited or otherwise formed.) An AlN or other suitable buffer layer (not shown) is grown, followed by an n-type region 16. The n-type region 16 may include multiple layers of different compositions, dopant concentrations, and thicknesses. The n-type region 16 may include at least one AlaGa1-aN film doped n-type with Si, Ge and/or other suitable n-type dopants. The n-type region 16 may have a thickness from about 100 nm to about 10 microns and is grown directly on the buffer layer(s). The doping level of Si in the n-type region 16 may range from 1×1016 cm−3 to 1×1021 cm−3. Depending on the intended emission wavelength, the AlN mole fraction “a” in the formula may vary from 0% for devices emitting at 360 nm to 100% for devices designed to emit at 200 nm.
An active region 18 is grown over the n-type region 16. The active region 18 may include either a single quantum well or multiple quantum wells (MQWs) separated by barrier layers. The quantum well and barrier layers contain AlxGa1-xN/AlyGa1-yN, wherein 0<x<y<1, x represents the AlN mole fraction of a quantum well layer, and y represents the AlN mole fraction of a barrier layer. The peak wavelength emitted by a UV LED is generally dependent upon the relative content of Al in the AlGaN quantum well active layer.
A p-type region 22 is grown over the active region 18. Like the n-type region 16, the p-type region 22 may include multiple layers of different compositions, dopant concentrations, and thicknesses. The p-type region 22 includes one or more p-type doped (e.g. Mg-doped) AlGaN layers. The AlN mole fraction can range from 0 to 100%, and the thickness of this layer or multilayer can range from about 2 nm to about 100 nm (single layer) or to about 500 nm (multilayer). A multilayer used in this region can improve lateral conductivity. The Mg doping level may vary from 1×1016 cm−3 to 1×1021 cm−3. A Mg-doped GaN contact layer may be grown last in the p-type region 22.
All or some of the semiconductor layers described above may be grown under excess Ga conditions, as described in more detail in US 2014/0103289, which is incorporated herein by reference.
The semiconductor structure 15 is etched to form trenches between the pixels 12 that reveal a surface of the n-type region 16. The sidewalls 12a of the pixels 12 may be vertical or sloped with an acute angle 12b relative to a normal to a major surface of the growth substrate. The height 138 of each pixel 12 may be between 0.1-5 microns. The widths 131 and 139 at the bottom and top of each pixel 12 may be at least 5 microns. Other dimensions may also be used.
Before or after etching the semiconductor structure 15 to form the trenches, a metal p-contact 24 is deposited and patterned on the top of each pixel 12. The p-contact 24 may include one or more metal layers that form an ohmic contact, and one or more metal layers that form a reflector. One example of a suitable p-contact 24 includes a Ni/Ag/Ti multi-layer contact.
An n-contact 28 is deposited and patterned, such that n-contact 28 is disposed on the substantially flat surface of the n-type region 16 between the pixels 12. The n-contact 28 may include a single or multiple metal layers. The n-contact 28 may include, for example, an ohmic n-contact 130 in direct contact with the n-type region 16, and an n-trace metal layer 132 formed over the ohmic n-contact 130. The ohmic n-contact 130 may be, for example, a V/Al/Ti multi-layer contact. The n-trace metal 132 may be, for example, a Ti/Au/Ti multi-layer contact.
The n-contact 28 and the p-contact 24 are electrically isolated by a dielectric layer 134. Dielectric layer 134 may be any suitable material such as, for example, one or more oxides of silicon, and/or one or more nitrides of silicon, formed by any suitable method. Dielectric layer 134 covers n-contact 28. Openings formed in dielectric layer 134 expose p-contact 24.
A p-trace metal 136 is formed over the top surface of the device, and substantially conformally covers the entire top surface. The p-trace metal 136 electrically connects to the p-contact 24 in the openings formed in dielectric layer 134. The p-trace metal 136 is electrically isolated from n-contact 28 by dielectric layer 134.
Robust metal pads electrically connected to the p-trace metal 136 and n-contact 28 are provided outside of the drawing for connection to the mount. Multiple pixels 12 are included in a single UVLED. The pixels are electrically connected by large area p-trace metal 136 and the large area n-trace metal 132. The number of pixels may be selected based on the application and/or desired radiation output. A single UVLED, which includes multiple pixels, is illustrated in the following figures as UVLED 1.
In some embodiments, substrate 14 is sapphire. Substrate 14 may be, for example, on the order of a hundred of microns thick. Substrate 14 may remain part of the device in some embodiments, and may be removed from the semiconductor structure in some embodiments.
The UVLED may be square, rectangular, or any other suitable shape when viewed from the top surface of substrate 14, when the device is flipped relative to the orientation illustrated in
In some embodiments, UVLED 1 is kept small to improve light extraction.
The length of the UVLED of
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Lenses 46 may be disposed over individual UVLEDs 1 as illustrated in
In some embodiments, the panel of packaged devices is diced into individual devices. In that case, the spacing 54 between neighboring devices may be the clearance needed to singulate mount 40 without causing damage, or the clearance needed plus the width of the mount desired for particular optical characteristics.
In some embodiments, multiple, packaged UVLEDs form a final product. In that case, the spacing 54 between neighboring UVLEDs may be selected to be large enough that neighboring UVLEDs absorb little or no light from each other. In some embodiments, the spacing 54 is at least three times the height of UVLED 1 relative to the top surface of mount 40 or to the top surface of the layers 42, 44 formed on mount 40. In some embodiments, the spacing 54 is at least 100 μm in some embodiments, no more than 1 mm in some embodiments, no more than 800 μm in some embodiments, and no more than 600 μm in some embodiments.
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Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concept described herein. In particular, different features and components of the different devices described herein may be used in any of the other devices, or features and components may be omitted from any of the devices. A characteristic of a structure described in the context of one embodiment, may be applicable to any embodiment. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.