This disclosure relates generally to cell site modems. More particularly, the disclosure relates to timing alignment and RF control using a cell site modem.
Wireless communication systems are widely deployed to provide various types of communication content such as voice, data, and so on. These systems may be multiple-access systems capable of supporting communication with multiple users by sharing the available system resources (e.g., bandwidth and transmit power). Examples of such multiple-access systems include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, 3GPP LTE systems, and orthogonal frequency division multiple access (OFDMA) systems.
Generally, a wireless multiple-access communication system can simultaneously support communication for multiple wireless terminals. Each terminal communicates with one or more base stations via transmissions on the forward and reverse (a.k.a. return or uplink) links. The forward link (or downlink) refers to the communication link from the base stations to the terminals, and the reverse link (a.k.a. return link or uplink) refers to the communication link from the terminals to the base stations. This communication link may be established via a single-in-single-out, multiple-in-signal-out or a multiple-in-multiple-out (MIMO) system.
A MIMO system employs multiple (NT) transmit antennas and multiple (NR) receive antennas for data transmission. A MIMO channel formed by the NT transmit and NR receive antennas may be decomposed into Ns independent channels, which are also referred to as spatial channels, where NS≦min {NT, NR}. Each of the NS independent channels corresponds to a dimension. The MIMO system can provide improved performance (e.g., higher throughput and/or greater reliability) if the additional dimensionalities created by the multiple transmit and receive antennas are utilized. For example, a MIMO system can support time division duplex (TDD) and frequency division duplex (FDD) systems. In a TDD system, the forward and reverse link transmissions are on the same frequency region so that the reciprocity principle allows the estimation of the forward link channel from the reverse link channel. This enables the access point to extract transmit beamforming gain on the forward link when multiple antennas are available at the access point.
Today's broadband wireless systems require efficient and powerful hardware, for example, application specific integrated circuits (ASIC), to support high rate data communications and also require highly flexible apparatus to support varied control channels. Data channels usually employ standard modulation techniques, such as quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM) etc. However the control channels, including different pilot channels, require special treatment. Control channels are low throughput in nature but require high reliability. As a result, control channels often use special modulation schemes, irregular and varied tones/orthogonal frequency division multiplex (OFDM) symbols resource allocation, channel specific hopping, and the reuse of tone resources among different channels. Moreover, as part of wireless standard evolution, the control channels are often modified over time. Also the control channel formats between different standards, such as Ultra Mobile Broadband (UMB) and Long Term Evolution (LTE), are very different and flexibility in a system to adapt to one or the other is needed for versatility.
Disclosed is an apparatus and method for timing alignment and/or RF control. According to one aspect, a method for sample synchronization comprises receiving a return link (RL) timestamp from a radio frequency front end (RFFE); receiving a system time second from a navigation and timing system; generating a forward link (FL) timestamp based on the RL timestamp and the system time second; and including the FL timestamp and the system time second in a time data.
According to another aspect, a method for RF control comprises storing gain information and gating control information in a memory; and performing one or more of the following: sending a first desired timestamp and the gain information to a radio frequency front end (RFFE); sending a second desired timestamp and a txEnable command to a transmit gating control; or sending a third desired timestamp and a rxEnable command to a receive gating control.
According to another aspect, a cell site modem (CSM) for sample synchronization comprising a processor and circuitry configured to: receive a return link (RL) timestamp from a radio frequency front end (RFFE); receive a system time second from a navigation and timing system; generate a forward link (FL) timestamp based on the RL timestamp and the system time second; and include the FL timestamp and the system time second in a time data.
According to another aspect, a cell site modem (CSM) for RF control comprising a processor and circuitry configured to: store gain information and gating control information in a memory; and perform one or more of the following: send a first desired timestamp and the gain information to a radio frequency front end (RFFE); send a second desired timestamp and a txEnable command to a transmit gating control; or send a third desired timestamp and a rxEnable command to a receive gating control.
According to another aspect, a device for sample synchronization comprises means for receiving a return link (RL) timestamp from a radio frequency front end (RFFE); means for receiving a system time second from a navigation and timing system; means for generating a forward link (FL) timestamp based on the RL timestamp and the system time second; and means for including the FL timestamp and the system time second in a time data.
According to another aspect, a device for RF control comprises means for storing gain information and gating control information in a memory; and means for performing one or more of the following: sending a first desired timestamp and the gain information to a radio frequency front end (RFFE); sending a second desired timestamp and a txEnable command to a transmit gating control; or sending a third desired timestamp and a rxEnable command to a receive gating control.
According to another aspect, a computer-readable medium including program code stored thereon, comprising program code for receiving a return link (RL) timestamp from a radio frequency front end (RFFE); program code for receiving a system time second from a navigation and timing system; program code for generating a forward link (FL) timestamp based on the RL timestamp and the system time second; and program code for including the FL timestamp and the system time second in a time data.
According to another aspect, a computer-readable medium including program code stored thereon, comprising program code for storing gain information and gating control information in a memory; and program code for performing one or more of the following: sending a first desired timestamp and the gain information to a radio frequency front end (RFFE); sending a second desired timestamp and a txEnable command to a transmit gating control; or sending a third desired timestamp and a rxEnable command to a receive gating control.
Advantages of the present disclosure include the ability to align timing references between the forward link and reverse link (a.k.a. return link) using a common serial interface and the ability to provide RF control functions using a same common serial interface.
It is understood that other aspects will become readily apparent to those skilled in the art from the following detailed description, wherein it is shown and described various aspects by way of illustration. The drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.
The detailed description set forth below in connection with the appended drawings is intended as a description of various aspects of the present disclosure and is not intended to represent the only aspects in which the present disclosure may be practiced. Each aspect described in this disclosure is provided merely as an example or illustration of the present disclosure, and should not necessarily be construed as preferred or advantageous over other aspects. The detailed description includes specific details for the purpose of providing a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the present disclosure. Acronyms and other descriptive terminology may be used merely for convenience and clarity and are not intended to limit the scope of the disclosure.
While for purposes of simplicity of explanation, the methodologies are shown and described as a series of acts, it is to be understood and appreciated that the methodologies are not limited by the order of acts, as some acts may, in accordance with one or more aspects, occur in different orders and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement a methodology in accordance with one or more aspects.
The techniques described herein may be used for various wireless communication systems such as Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, Orthogonal FDMA (OFDMA) systems, Single-Carrier FDMA (SC-FDMA) systems, etc. The terms “systems” and “networks” are often used interchangeably. A CDMA system may implement a radio technology such as Universal Terrestrial Radio Access (UTRA), cdma2000, etc. UTRA includes Wideband-CDMA (W-CDMA) and Low Chip Rate (LCR). Cdma2000 covers IS-2000, IS-95 and IS-856 standards. A TDMA system may implement a radio technology such as Global System for Mobile Communications (GSM). An OFDMA system may implement a radio technology such as Evolved UTRA (E-UTRA), IEEE 802.11, IEEE 802.16, IEEE 802.20, Flash-OFDM®, etc. UTRA, E-UTRA, and GSM are part of Universal Mobile Telecommunication System (UMTS). Long Term Evolution (LTE) is an upcoming release of UMTS that uses E-UTRA. UTRA, E-UTRA, GSM, UMTS and LTE are described in documents from an organization named “3rd Generation Partnership Project” (3GPP). Cdma2000 is described in documents from an organization named “3rd Generation Partnership Project 2” (3GPP2). These various radio technologies and standards are known in the art.
Additionally, single carrier frequency division multiple access (SC-FDMA), which utilizes single carrier modulation and frequency domain equalization is another wireless communication technique. A SC-FDMA system can have similar performance and the same overall complexity as those of an OFDMA system. SC-FDMA signal has lower peak-to-average power ratio (PAPR) because of its inherent single carrier structure. SC-FDMA has drawn great attention, especially in uplink communications where lower PAPR greatly benefits the mobile terminal in terms of transmit power efficiency. Using SC-FDMA technique is currently a working assumption for uplink multiple access scheme in 3GPP Long Term Evolution (LTE), or Evolved UTRA. All of the above wireless communication techniques and standards may be used with the data centric multiplexing algorithms described herein.
In communication over forward links 120 and 126, the transmitting antennas of access point 100 utilize beamforming in order to improve the signal-to-noise ratio of forward links for the different access terminals 116 and 124. Also, an access point using beamforming to transmit to access terminals scattered randomly through its coverage causes less interference to access terminals in neighboring cells than an access point transmitting through a single antenna to all its access terminals. An access point may be a fixed station. An access point may also be referred to as an access node, a base station or some other similar terminology known in the art. An access terminal may also be called a mobile station, a user equipment (UE), a wireless communication device or some other similar terminology known in the art.
The coded data for each data stream may be multiplexed with pilot data using OFDM techniques. The pilot data is typically a known data pattern that is processed in a known manner and may be used at the receiver system to estimate the channel response. The multiplexed pilot and coded data for each data stream is then modulated (i.e., symbol mapped) based on a particular modulation scheme (e.g., BPSK, QSPK, M-PSK, or M-QAM) selected for that data stream to provide modulation symbols. The data rate, coding, and modulation for each data stream may be determined by instructions performed by processor 230.
The modulation symbols for all data streams are then provided to a TX MIMO processor 220, which may further process the modulation symbols (e.g., for OFDM). TX MIMO processor 220 then provides NT modulation symbol streams to NT transmitters (TMTR) 222a through 222t. In one example, the TX MIMO processor 220 applies beamforming weights to the symbols of the data streams and to the antenna from which the symbol is being transmitted. Each transmitter 222a through 222t receives and processes a respective symbol stream to provide one or more analog signals, and further conditions (e.g., amplifies, filters, and upconverts) the analog signals to provide a modulated signal suitable for transmission over the MIMO channel. NT modulated signals from transmitters 222a through 222t are then transmitted from NT antennas 224a through 224t, respectively.
At access terminal 250, the transmitted modulated signals are received by NR antennas 252a through 252r and the received signal from each antenna 252a through 252r is provided to a respective receiver (RCVR) 254a through 254r. Each receiver 254a through 254r conditions (e.g., filters, amplifies, and downconverts) a respective received signal, digitizes the conditioned signal to provide samples, and further processes the samples to provide a corresponding “received” symbol stream.
A RX data processor 260 then receives and processes the NR received symbol streams from NR receivers 254a through 254r based on a particular receiver processing technique to provide NT “detected” symbol streams. The RX data processor 260 then demodulates, deinterleaves, and decodes each detected symbol stream to recover the traffic data for the data stream. The processing by RX data processor 260 is complementary to that performed by TX MIMO processor 220 and TX data processor 214 at access point 210. A processor 270 periodically determines which pre-coding matrix to use (discussed below). Processor 270 formulates a reverse link message comprising a matrix index portion and a rank value portion.
The reverse link message may comprise various types of information regarding the communication link and/or the received data stream. The reverse link message is then processed by a TX data processor 238, which also receives traffic data for a number of data streams from a data source 236, modulated by a modulator 280, conditioned by transmitters 254a through 254r, and transmitted back to access point 210.
At access point 210, the modulated signals from access terminal 250 are received by antennas 224a through 224t, conditioned by receivers 222a through 222t, demodulated by a demodulator 240, and processed by a RX data processor 242 to extract the reserve link message transmitted by the access terminal 250. Processor 230 then determines which pre-coding matrix to use for determining the beamforming weights, then the processor 230 processes the extracted message. One skilled in the art would understand that the transceivers 222a through 222t are called transmitters in the forward link and receivers in the reverse link. Similarly, one skilled in the art would understand that the transceivers 254a through 254r are called receivers in the forward link and transmitters in the reverse link.
In one aspect, a cell site modem (CSM) implements the modulation and demodulation functions of the access point 210. In particular, the modulator of the TX data processor 214 and the demodulator 240 of the access point 210 may be implemented in an integrated CSM.
The MAC interface is used to exchange MAC and PHY information between the CSM and the MAC host. On the Forward Link (FL), the MAC interface allows the MAC host to indicate to the CSM the information bits to be sent over the airlink, for example, for one or more of the following channels:
On the Reverse Link (RL), the CSM provides the MAC host the bits received over the airlink, for example, for one or more of the following channels:
In addition to bits sent over the channels, the MAC host uses the messaging interface to control the behavior of various algorithms in the CSM for power control, timing control, and multiple antenna techniques. The details of how this information is carried are described in the section on the RF control interface below.
The CSM radio frequency (RF) interface provides a protocol for carrying time-domain inphase-quadrature (IQ) baseband samples and control messages between the CSM and RF front end. This protocol also provides for synchronization of the CSM with the network timing reference.
In one aspect, the access point may consist of multiple transmit/receive antennas, CSMs, MAC hosts, and management hosts. In one example, the CSM may support up to four transmit and four receive antennas. The CSM needs to be provisioned with the subset of antennas with which it should associate. A single MAC host can interface with multiple CSMs to allow support for multiple sector carriers on a particular MAC channel. The CSM is provisioned with the associated MAC and management host.
In one example, the access point reference design architecture incorporates a CSM. In the reference design, the Layer 2 Module (L2M) is the MAC host and the control plane module (CPM) is the management host.
The MAC host software is responsible, for example, for one or more of the following functionalities:
In one example, encryption and decryption are done by a hardware accelerator in the CSM. The engine is controlled by the MAC host over the sRIO interface.
On receiving a MAC packet on the RL data channel, the CSM processes the MAC packet and forwards all the PCP (packet consolidation protocol), route, stream, and RLP headers in the MAC packet to the MAC host. Based on the headers, the MAC host instructs the encryption engine to decrypt each SAR (segmentation and reassembly) payload in the MAC packet and write the results into the appropriate MAC host memory location. The RLP processing in the MAC host reassembles packets from the SAR segments.
In one example, the CSM API (application programming interface) consists of the protocols and associated messages between the CSM and the MAC and management hosts flowing over the sRIO interface. Appendix A, herein incorporated by reference, describes the API. Information is exchanged over the sRIO interface through direct memory reads and writes, sRIO messages, and doorbells. For example, for direct memory access, standard RapidIO input/output transactions NREAD, WRITE, NWRITE, and NWRITE_R are used.
In one aspect, the CSM incorporates a management interface with, for example, one or more of the following features:
In one aspect the CSM incorporates a MAC interface with, for example, one or more of the following features:
In one aspect, the CSM sample interface provides a protocol for carrying time domain IQ baseband samples between the CSM and a radio frequency front end (RFFE). This protocol also provides for synchronization of the CSM with the network timing reference as well as robust error/loss detection. Global synchronization of the system is maintained by the RFFE via the Global Positioning Satellite (GPS) or some other mechanism, or the system may operate in asynchronous mode with system time being local to a single base station. For UMB synchronous operation, the airlink framing structure is universally aligned and referenced back to the start of GPS time, for example. The RFFE must provide a system time reference to the CSM so that the CSM may generate an underlying framing structure with the correct synchronization. This system time reference is a count of samples since the last system time second. The sample count timestamp represents the absolute time of the sample immediately following the timestamp referenced at the antenna.
To maintain error robustness, the sample counter timestamp is multiplexed with the sample stream to and from the RFFE at fixed intervals. For example, the sample segment size between timestamps is 1024 samples for the 10-MHz bandwidth UMB frequency division duplex (FDD) mode and 512 samples for the 5-MHz bandwidth UMB FDD mode. In one aspect the CSM and the RFFE pass the sample information for the forward and reverse links using a Serial RapidIO (sRIO) interface. The RFFE sends the reverse link (RL) data to the CSM via sRIO SWRITEs initiated by the RFFE. The CSM sends forward link (FL) data to the RFFE via sRIO SWRITEs initiated by the CSM. In one example, the sRIO interface has the following minimum performance requirements:
In one aspect, latency in both the FL and RL paths between the CSM and the antennas is quantified. This information is required to adjust the RL timestamp sent to the CSM. This adjustment allows the CSM to synchronously align the FL data. Meaningful FL data cannot be delivered before this synchronization has been established.
The timestamp values represent the time of a sample at the antenna. The RFFE must account for any latency between the antenna and its digital sampling by offsetting the timestamps appropriately. The CSM supports a programmable advance of the FL timestamp to account for transport latency, maximum jitter bounds, and latency within the RFFE. In one example, this advance is less than 200 μsec.
In one aspect, when the CSM receives a timestamp from the RL, it adds the advance timing programmed for the timestamps on the FL. This allows the correct synchronization of the FL samples at the transmit antenna.
In one aspect, the sample stream format has, for example, one or more of the following features:
In one aspect, Table 2 illustrates the sample count timestamp format. Table 3 illustrates the sample data format for the RL. Table 4 illustrates the sample data format for the FL. And, Table 5 illustrates the register addressing.
In one aspect the RF control interface provides real time control for the receiver gain and for transmit and receive gating for TDD mode. The control interface is called real-time since it provides a mechanism for synchronizing commands with the data. In one aspect, the real-time control interface is not intended for static configuration, such as synthesizer and filtering settings or transmit power control. In one aspect, the real-time interface is also not intended for alarms, which must be processed elsewhere. Both the gain and gating control are performed by SWRITE operations to the memory addresses shown in Table 6. Table 7 illustrates an example format for the gain control stream.
The timestamp field reflects the desired time at which the gain change is to take effect. In one example, the actual time at which the RFFE changes the gain (based on a gain information rxGain) is within +/−2 μs of the desired time. If the most significant bit (MSB) of the timestamp is set, the RFFE implements the gain change as soon as possible. The CSM submits gain changes within at least 100 μs of the desired time. If a gain control command is submitted before a previous gain control command has taken effect, the RFFE may ignore the previous command. Consequently, no buffering is required for the gain control commands. At the desired time, the RFFE adjusts its total receive gain so that input and output power are related by:
rxGain=round((Pout−Pin)*2) (1)
where Pin is the RFFE's estimate of the receive power at the antenna port in dBm, and Pout is given by:
Pout=10 log(σ2) (2)
and σ2 is the mean squared digital value of the IQ samples. Therefore, rxGain represents the desired gain, in 0.5 dB steps, between the antenna and the digital RFFE output to the CSM. In one aspect, the calibration is done with an additive white Gaussian noise (AWGN) signal whose bandwidth covers the system input bandwidth. This ensures that the gain reflects the average gain over the passband. Since the input power is measured at the antenna port and not at the RFFE input, the RFFE must account for all external gains in the LNA and cable losses.
If the RFFE implements the gain in multiple stages, then it is up to the RFFE to decide the gain decomposition. Moreover, the RFFE may implement various automatic gain controls (AGCs) internally. For example, an AGC may operate on some RF gain stage prior to filtering to prevent overloading due to out-of-channel interference. However, in one aspect, if the RFFE changes the gain in one stage, it attempts to keep the total gain from the antenna to the CSM constant. If the RFFE cannot maintain a constant gain, it reports the condition and any other relevant information to the CSM.
In one example, for error tolerances, the RFFE matches the average gain with a relative accuracy of +/−0.5 dB between different gain settings. The error tolerance refers to the average gain across the passband. This interface does not stipulate any absolute accuracy of the rxGain value. Other parameters, for example, such as the nominal absolute gain value and range of valid gain settings, are not specified in this interface either, and would need to be communicated to the CSM via some other static configuration. In another aspect, the format for the Tx and Rx gating commands are shown in Table 8 and Table 9, respectively.
As with the Rx gain control command, the timestamp field reflects the desired time at which the command is to take effect. In one example, the actual time at which the RFFE implements the command is within +/−1 μs of the desired time. If the most significant bit (MSB) of the timestamp is set, the RFFE implements the command as soon as possible. In one example, the CSM submits commands within at least 100 μs, and at most 10 ms, of the desired time. Also, the timestamps on any two Rx gating control commands correspond to times separated by at least 100 μs. Therefore, since the commands can be submitted at most 10 ms in advance, the RFFE needs to buffer, at most, 100 commands.
In the Tx gating command, a value of “1” on the txEnable bit indicates that the Tx is enabled. That is, data corresponding to samples after the desired time stamp is transmitted from the antenna. Conversely, a value of “0” indicates that the samples is not transmitted. If the Tx path is implemented in multiple stages, the order and timing of control of those stages is established. Similarly, in the Rx gating command, the rxEnable bit is set or not set to enable or disable the Rx path. If the Rx path is implemented in multiple stages, the order and timing of control of those stages is established. The timestamp and data packets are sent independently of whether the Tx or Rx data path is enabled.
Following block 1420, in block 1430, generate a forward link (FL) timestamp based on the RL timestamp and the system time second. In one aspect, a FL timestamp is adjusted based on the RL timestamp and the system time second. Following block 1430, in block 1440, include the FL timestamp and the system time second in a time data. Following block 1440, in block 1450, multiplex the time data into a sample stream. In one aspect, the entity receiving the RL timestamp and the system time second is a cell site modem (CSM). In one example, the CSM is part of the access point block diagram illustrated in
Following block 1630, in block 1640, send a second desired timestamp and a txEnable command to a transmit gating control. The second desired timestamp reflects the desired time at which the txEnable command is to take effect. When executed, the txEnable command enables the transmit (tx) path. In one example, the parameters shown in Table 8 are used in the step of block 1640. In one example, the transmit gating control is a component of the RFFE.
Following block 1640, in block 1650, send a third desired timestamp and a rxEnable command to a receive gating control. The third desired timestamp reflects the desired time at which the rxEnable command is to take effect. When executed, the rxEnable command enables the receive (rx) path. In one example, the parameters shown in Table 9 are used in the step of block 1650. In one example, the receive gating control is a component of the RFFE.
In one aspect, the entity executing the steps of the example flow diagram of
One skilled in the art would understand that the steps disclosed in the example flow diagrams in
Those of skill would further appreciate that the various illustrative components, logical blocks, modules, circuits, and/or algorithm steps described in connection with the examples disclosed herein may be implemented as electronic hardware, firmware, computer software, or combinations thereof. To clearly illustrate this interchangeability of hardware, firmware and software, various illustrative components, blocks, modules, circuits, and/or algorithm steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware, firmware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope or spirit of the present disclosure.
For example, for a hardware implementation, the processing units may be implemented within one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described therein, or a combination thereof. With software, the implementation may be through modules (e.g., procedures, functions, etc.) that performs the functions described therein. The software codes may be stored in memory units and executed by a processor unit. Additionally, the various illustrative flow diagrams, logical blocks, modules and/or algorithm steps described herein may also be coded as computer-readable instructions carried on any computer-readable medium known in the art or implemented in any computer program product known in the art.
In one example, the illustrative components, flow diagrams, logical blocks, modules and/or algorithm steps described herein are implemented or performed with one or more processors. In one aspect, a processor is coupled with a memory which stores data, metadata, program instructions, etc. to be executed by the processor for implementing or performing the various flow diagrams, logical blocks and/or modules described herein.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the spirit or scope of the disclosure.
The present Application for patent claims priority to Provisional Application No. 61/015,642 entitled “UMB CSM Architecture” filed Dec. 20, 2007, and assigned to the assignee hereof and hereby expressly incorporated by reference herein.
Number | Date | Country | |
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61015642 | Dec 2007 | US |