This patent document is directed generally to image and video coding technologies.
Motion compensation is a technique in video processing to predict a frame in a video, given the previous and/or future frames by accounting for motion of the camera and/or objects in the video. Motion compensation can be used in the encoding and decoding of video data for video compression.
Devices, systems and methods related to sub-block based prediction for image and video coding are described.
In a representative aspect, the disclosed technology may be used to provide a method for video processing. This method includes determining a block size constrain, making a determination, based on the block size constrain, about whether or not a merge affine mode and a non-merge affine mode are allowed for a video block in a video frame, and generating a bitstream representation of the video block based on the making the determination.
In a representative aspect, the disclosed technology may be used to provide another method for video processing. This method includes determining a block size constrain, making a determination, based on the block size constrain, about whether or not a merge affine mode and a non-merge affine mode are allowed for a video block in a video frame, and generating the video block from a bitstream representation of the video block based on the making the determination.
In yet another representative aspect, the above-described method is embodied in the form of processor-executable code and stored in a computer-readable program medium.
In yet another representative aspect, a device that is configured or operable to perform the above-described method is disclosed. The device may include a processor that is programmed to implement this method.
In yet another representative aspect, a video decoder apparatus may implement a method as described herein.
The above and other aspects and features of the disclosed technology are described in greater detail in the drawings, the description and the claims.
Due to the increasing demand of higher resolution video, video coding methods and techniques are ubiquitous in modern technology. Video codecs typically include an electronic circuit or software that compresses or decompresses digital video, and are continually being improved to provide higher coding efficiency. A video codec converts uncompressed video to a compressed format or vice versa. There are complex relationships between the video quality, the amount of data used to represent the video (determined by the bit rate), the complexity of the encoding and decoding algorithms, sensitivity to data losses and errors, ease of editing, random access, and end-to-end delay (latency). The compressed format usually conforms to a standard video compression specification, e.g., the High Efficiency Video Coding (HEVC) standard (also known as H.265 or MPEG-H Part 2), the Versatile Video Coding standard to be finalized, or other current and/or future video coding standards.
Sub-block based prediction is first introduced into the video coding standard by the High Efficiency Video Coding (HEVC) standard. With sub-block based prediction, a block, such as a Coding Unit (CU) or a Prediction Unit (PU), is divided into several non-overlapped sub-blocks. Different sub-blocks may be assigned different motion information, such as reference index or motion vector (MV), and motion compensation (MC) is performed individually for each sub-block.
Embodiments of the disclosed technology may be applied to existing video coding standards (e.g., HEVC, H.265) and future standards to improve runtime performance. Section headings are used in the present document to improve readability of the description and do not in any way limit the discussion or the embodiments (and/or implementations) to the respective sections only.
In some embodiments, future video coding technologies are explored using a reference software known as the Joint Exploration Model (JEM). In JEM, sub-block based prediction is adopted in several coding tools, such as affine prediction, alternative temporal motion vector prediction (ATMVP), spatial-temporal motion vector prediction (STMVP), bi-directional optical flow (BIO), Frame-Rate Up Conversion (FRUC), Locally Adaptive Motion Vector Resolution (LAMVR), Overlapped Block Motion Compensation (OBMC), Local Illumination Compensation (LIC), and Decoder-side Motion Vector Refinement (DMVR).
In HEVC, only a translation motion model is applied for motion compensation prediction (MCP). However, the camera and objects may have many kinds of motion, e.g. zoom in/out, rotation, perspective motions, and/or other irregular motions. JEM, on the other hand, applies a simplified affine transform motion compensation prediction.
As shown in
Here, MvPre is the motion vector fraction accuracy (e.g., 1/16 in JEM). (v2x, v2y) is motion vector of the bottom-left control point, calculated according to Eq. (1). M and N can be adjusted downward if necessary to make it a divisor of w and h, respectively.
In the JEM, there are two affine motion modes: AF_INTER mode and AF_MERGE mode. For CUs with both width and height larger than 8, AF_INTER mode can be applied. An affine flag in CU level is signaled in the bitstream to indicate whether AF_INTER mode is used. In the AF_INTER mode, a candidate list with motion vector pair {(v0, v1)|v0={VA, VB, VC}, v1={vD, vE}} is constructed using the neighboring blocks.
When a CU is applied in AF_MERGE mode, it gets the first block coded with an affine mode from the valid neighboring reconstructed blocks.
After the CPMV of the current CU v0 and v1 are computed according to the affine motion model in Eq. (1), the MVF of the current CU can be generated. In order to identify whether the current CU is coded with AF_MERGE mode, an affine flag can be signaled in the bitstream when there is at least one neighboring block is coded in affine mode.
In JEM, the non-merge affine mode can be used only when the width and the height of the current block are both larger than 8; the merge affine mode can be used only when the area (i.e. width×height) of the current block is not smaller than 64.
In some existing implementations, the size of sub-blocks (such as 4×4 in JEM) is primarily designed for the luma component. For example, in JEM, the size of sub-blocks is for the 2×2 chroma components with the 4:2:0 format, and for the 2×4 chroma components with the 4:2:2 format. The small size of sub-blocks imposes a higher band-width requirement.
In other existing implementations, in some sub-block based tools such as the affine prediction in JEM, MVs of each sub-block are calculated with the affine model as shown in Eq. (1) independently for each component, which may result in misalignment of motion vectors between luma and chroma components.
In yet other existing implementations, in some sub-block based tools such as affine prediction, the usage constrains are different for the merge mode and the non-merge inter mode (a.k.a. AMVP mode, or normal inter-mode), which need to be unified.
Sub-block based prediction methods include unifying the constraints for the merge affine mode and the non-merge affine mode. The use of sub-block based prediction to improve video coding efficiency and enhance both existing and future video coding standards is elucidated in the following examples described for various implementations.
Example 1. The merge affine mode and the non-merge affine mode are allowed or disallowed with the same block size constraint.
The examples described above may be incorporated in the context of the methods described below, e.g., methods 700 and 750, which may be implemented at a video encoder and video decoder, respectively.
In some embodiments, the generating the bitstream representation includes coding the video block using the merge affine mode by including an indication of the merge affine mode in the bitstream representation. In some embodiments, the generating the bitstream representation includes coding the video block using the non-merge affine mode by including an indication of the non-merge affine mode in the bitstream representation. In some embodiments, the generating the bitstream representation includes coding the video block using the merge affine mode by omitting an indication of the merge affine mode in the bitstream representation, thereby implicitly indicating the merge affine mode. In some embodiments, the generating the bitstream representation includes coding the video block using the non-merge affine mode by omitting an indication of the non-merge affine mode in the bitstream representation, thereby implicitly indicating the non-merge affine mode.
In some embodiments, the generating the bitstream representation includes generating the bitstream representation from the video block such that the bitstream omits an explicit indication of the merge affine mode due to the determination that the block size constrain disallowed the merge affine mode. In some embodiments, the generating the bitstream representation includes generating the bitstream representation from the video block such that the bitstream omits an explicit indication of the non-merge affine mode due to the determination that the block size constrain disallowed the non-merge affine mode. In some embodiments, the block size constrain of the video block includes a height of the video block and a width of the video block that are each greater than a common threshold. In some embodiments, the common threshold is eight, and the merge affine mode and the non-merge affine mode are allowed in response to the height of the video block and the width of the video block being greater than the common threshold. In some embodiments, the common threshold is sixteen, and the merge affine mode and the non-merge affine mode are allowed in response to the height of the video block and the width of the video block being greater than the common threshold.
In some embodiments, the block size constrain of the video block includes a height of the video block greater than a first threshold and a width of the video block greater than a second threshold, and the first threshold and the second threshold are different. In some embodiments, the block size constrain of the video block includes a height of the video block and a width of the video block, and a product of the height and the width is greater than a threshold.
In some embodiments, the bitstream representation includes an indication of the merge affine mode, and the video block is generated using the merge affine mode by parsing the bitstream representation according to the indication. In some embodiments, the bitstream representation includes an indication of the non-merge affine mode, and the video block is generated using the non-merge affine mode by parsing the bitstream representation according to the indication. In some embodiments, the bitstream representation omits an indication of the merge affine mode, and wherein the video block is generated using the merge affine mode by parsing the bitstream representation in absence of the indication of the merge affine mode. In some embodiments, the bitstream representation omits an indication of the non-merge affine mode, and the video block is generated using the non-merge affine mode by parsing the bitstream representation in absence of the indication of the non-merge affine mode.
In some embodiments, the block size constrain of the video block includes a height of the video block and a width of the video block that are each greater than a common threshold. In some embodiments, the block size constrain of the video block includes a height of the video block greater than a first threshold and a width of the video block greater than a second threshold, and the first threshold and the second threshold are different. In some embodiments, the block size constrain of the video block includes a height of the video block and a width of the video block, and a product of the height and the width is greater than a threshold.
The methods 700 and 750, described respectively in the context of
In a representative aspect, the above-described methods 700 and/or 750 are embodied in the form of processor-executable code and stored in a computer-readable program medium. In yet another representative aspect, a device that is configured or operable to perform the above-described methods are disclosed. The device may include a processor that is programmed to implement the above described methods 700 and/or 750. In yet another representative aspect, a video encoder apparatus may implement method 700. In yet another representative aspect, a video decoder apparatus may implement method 750.
The processor(s) 805 may include central processing units (CPUs) to control the overall operation of, for example, the host computer. In certain embodiments, the processor(s) 805 accomplish this by executing software or firmware stored in memory 810. The processor(s) 805 may be, or may include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.
The memory 810 can be or include the main memory of the computer system. The memory 810 represents any suitable form of random access memory (RAM), read-only memory (ROM), flash memory, or the like, or a combination of such devices. In use, the memory 810 may contain, among other things, a set of machine instructions which, when executed by processor 805, causes the processor 805 to perform operations to implement embodiments of the presently disclosed technology.
Also connected to the processor(s) 805 through the interconnect 825 is a (optional) network adapter 815. The network adapter 815 provides the computer system 800 with the ability to communicate with remote devices, such as the storage clients, and/or other storage servers, and may be, for example, an Ethernet adapter or Fiber Channel adapter.
To support various functions of the mobile device 900, the memory 902 can store information and data, such as instructions, software, values, images, and other data processed or referenced by the processor 901. For example, various types of Random Access Memory (RAM) devices, Read Only Memory (ROM) devices, Flash Memory devices, and other suitable storage media can be used to implement storage functions of the memory 902. In some implementations, the mobile device 900 includes an input/output (I/O) unit 903 to interface the processor 901 and/or memory 902 to other modules, units or devices. For example, the I/O unit 903 can interface the processor 901 and memory 902 with to utilize various types of wireless interfaces compatible with typical data communication standards, e.g., such as between the one or more computers in the cloud and the user device. In some implementations, the mobile device 900 can interface with other devices using a wired connection via the I/O unit 903. The mobile device 900 can also interface with other external interfaces, such as data storage, and/or visual or audio display devices 904, to retrieve and transfer data and information that can be processed by the processor, stored in the memory, or exhibited on an output unit of a display device 904 or an external device. For example, the display device 904 can display a video frame that includes a block (a CU, PU or TU) that applies the intra-block copy based on whether the block is encoded using a motion compensation algorithm, and in accordance with the disclosed technology.
In some embodiments, a video encoder apparatus or decoder apparatus may implement a method of sub-block based prediction as described herein is used for video encoding or decoding. The various features of the method may be similar to the above-described methods 700 or 750.
In some embodiments, the video encoding and/or decoding methods may be implemented using a decoding apparatus that is implemented on a hardware platform as described with respect to
From the foregoing, it will be appreciated that specific embodiments of the presently disclosed technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Accordingly, the presently disclosed technology is not limited except as by the appended claims.
Implementations of the subject matter and the functional operations described in this patent document can be implemented in various systems, digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Implementations of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term “data processing unit” or “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.
A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).
Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
It is intended that the specification, together with the drawings, be considered exemplary only, where exemplary means an example. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, the use of “or” is intended to include “and/or”, unless the context clearly indicates otherwise.
While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.
Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.
Number | Date | Country | Kind |
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PCT/CN2018/092118 | Jun 2018 | WO | international |
This application is a continuation of U.S. application Ser. No. 17/099,042, filed on Nov. 16, 2020, which is a continuation of International Application No. PCT/IB2019/055244, filed on Jun. 21, 2019, which claims the priority to and benefits of International Patent Application No. PCT/CN2018/092118, filed on Jun. 21, 2018. All the aforementioned patent applications are hereby incorporated by reference in their entireties.
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Number | Date | Country | |
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20210352302 A1 | Nov 2021 | US |
Number | Date | Country | |
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Parent | 17099042 | Nov 2020 | US |
Child | 17380278 | US | |
Parent | PCT/IB2019/055244 | Jun 2019 | US |
Child | 17099042 | US |