Patent Application
20190058082
The present disclosure relates to semiconductor structures and, more particularly, to uniform semiconductor nanowire and nanosheet light emitting diodes and methods of manufacture.
Light emitting diodes (LEDs) require optically transparent and highly conducting electrodes. In LEDs, a material is in contact with a charge collector in addition to a medium, such as an electrolyte that is inductive of electrochemical activity. When a suitable voltage is applied to leads of the LED device, electrons are able to recombine with electron holes within the LED device, releasing energy in the form of photons.
Two-dimensional (2D) LEDs are planar devices that emit light from a thin layer of material at or near their flat surface. On the other hand, in three-dimensional (3D) LEDs, light is capable of being emitted from all sides of a device. Manufacturing of 3D LEDs pose many issues including micro-loading of nanowires and nanosheets and spectral spread and yield loss due to non-uniform diameter nanowire or nanosheet LED leads.
In an aspect of the disclosure, a structure comprises: a buffer layer; at least one dielectric layer on the buffer layer, the at least one dielectric layer having a plurality of openings exposing the buffer layer; and a plurality of uniformly sized and shaped nanowires or nanosheets formed in the openings and extending above the at least one dielectric layer.
In an aspect of the disclosure, a method comprises: forming a first dielectric material on a buffer layer; forming a second dielectric on the first dielectric; etching a plurality of openings through the first dielectric and the second dielectric of the structure, stopping on the buffer layer; filling the plurality of openings with seed material; and removing the second dielectric of the structure to expose a plurality of nanowire or nanosheet seeds, which comport to a shape of the plurality of openings.
In an aspect of the disclosure, a method comprises: forming a first dielectric material directly on a buffer layer; forming a second dielectric material directly on the first dielectric material; etching a plurality of openings through the first dielectric material and the second dielectric material, exposing the buffer layer; growing nanowire or nanosheet seeds in the plurality of openings, from the exposed buffer layer; removing the second dielectric material to partially expose a plurality of uniformly shaped nanowires or nanosheets that comport with a shape of the plurality of openings; forming a plurality of quantum wells on sidewalls of the uniformly shaped nanowires or nanosheets; and forming at least one material on sidewalls of each of the plurality of quantum wells.
The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure.
The present disclosure relates to semiconductor structures and, more particularly, to uniform semiconductor nanowire and nanosheet light emitting diodes and methods of manufacture. More specifically, the present disclosure is directed to 3D LEDs with uniform nanowire or nanosheets. Advantageously, the present disclosure reduces the manufacturing cost in comparison to two-dimensional (2D) LEDs. In particular, the present disclose can reduce the manufacturing cost approximately three-fold over 2D LEDs. Further, the present disclosure provides for a same size nanowire or nanosheet and a same band gap, which results in tighter optical spectra distribution and manufacturing yield.
In the present disclosure, nanowires or nanosheets can be grown in uniform shapes, e.g., same circular or rectangular shapes. This is accomplished by growing nanowires or nanosheets in uniformly shaped openings in dielectric material. In embodiments, the openings are made by conventional patterning and etching processes, e.g., CMOS processes, which results in precise control of the nanowire or nanosheet seed diameter from pixel to pixel and from wafer to wafer. Thus, in the present disclosure, the manufacturing process obtains a uniform size for the nanowire or nanosheet LEDs.
The nanowire or nanosheet LED structures of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the semiconductor structure of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the nanowire or nanosheet LED structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the nanowire or nanosheet LED structures uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask.
Still referring to
In
In embodiments, the openings 55 are uniform, e.g., with the same size. In embodiments, the openings 55 can be changed to different dimensions to control and tune a color of the LEDs. For example, the dimensions of the openings 55 can be in a range of about 50 nm to 1 micron, with 70 nm being one preferred embodiment. In further embodiments, the openings 55 can be about 150 nm to 500 nm, and preferably between 150 nm to about 200 nm etc., to emit different colors in the LEDs. In embodiments, the openings 55 can be circular, rectangular or other shapes, all of which are of a same uniform shape to contain the growth of LED material, e.g., seed material for the nanowire, etc.
In
The method(s) as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
