The disclosure relates to a removable electronic device and an adapter device of the removable electronic device; and in particular to an USB SSIC removable electronic device and an adapter device of the removable electronic device which are compatible with USB SSIC interface.
Recently, with vigorous development of computers and the communications industry, various peripheral devices can easily be connected to a host device such as a personal computer (PC), a notebook PC, and so on, including Internet and external storage devices, and so on. Usually, users need to transmit data from the peripheral device to the host, or transmit data from the host to the peripheral device, but the transmission speed and power requirement of the peripheral device during the transmission are limited by the interface. example, the power requirement of the USB interface is too high for the mobile devices. Therefore a memory or functional card with a USB interface is not the best option for mobile devices.
An exemplary embodiment provides an USB SSIC removable electronic device with a first surface. The removable electronic device includes a first receiving terminal pair, a first transmitting terminal pair, an MIPI/SSIC-PHY/Link layer, a function module, at least one power terminal and a ground terminal. The first receiving terminal pair is arranged to receive data compatible with a transmission protocol of an USB SSIC interface. The first transmitting terminal pair is arranged to transmit data compatible with the transmission protocol of the USB SSIC interface. The MIPI/SSIC-PHY/Link layer is arranged to be coupled to the first receiving terminal pair and the first transmitting terminal pair, receive data compatible with the transmission protocol of USB SSIC interface from the first receiving terminal pair, and transmit data compatible with the transmission protocol of USB SSIC interface to the first transmitting terminal pair. The function module is arranged to be coupled to the MIPI/SSIC-PHY/Link layer, and transmit data with the MIPI/SSIC-PHY/Link layer by the transmission protocol of USB SSIC interface. The at least one power terminal is arranged to provide at least one source voltage for the MIPI/SSIC-PHY/Link layer and the function module for operating. The first receiving terminal pair, the first transmitting terminal pair, the power terminal and the ground terminal are arranged along a first axis on the first surface.
Another exemplary embodiment provides an adapter device. The adapter device includes a slot, an SSIC pin set, a first interface pin set, an interface converting device and a power regulator. The slot is arranged to contain an USB SSIC removable electronic device compatible with an USB SSIC interface, and the removable electronic device comprises a plurality of terminals. The SSIC pin set is arranged in the slot, and coupled to the plurality of terminals. The first interface pin set is compatible with a first interface. The interface converting device is coupled to the SSIC pin set and the first interface pin set, and arranged to convert data of the first face into data compatible with a transmission protocol of the USB SSIC interface and convert data compatible with the transmission protocol of USB SSIC interface into data compatible with a transmission protocol of the first interface. The power regulator is arranged to receive at least one input voltage compatible with the transmission protocol of first interface, and convert the input voltage into at least one source voltage compatible with transmission protocol of the USB SSIC interface.
The present disclosure can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.
The first receiving terminal pair is arranged to receive the data RXD1+ and RXD1− which are compatible with the transmission protocol of the USB SSIC interface. The first transmitting terminal pair is arranged to transmit the data TXD1+ and TXD1− which are compatible with the transmission protocol of the USB SSIC interface. The power terminal is arranged to receive at least one source voltage which is arranged to provide to the MIPI/SSIC-PHY/Link layer 104 and the function module 106 for regular operating. In one of the embodiments, the pin set 102 has two power terminals including a first power terminal and a second power terminal, the first power terminal and the second power terminal are arranged to receive a first voltage VCC1 and a second voltage VCC2, respectively, and the first voltage VCC1 and the second voltage VCC2 are arranged to provide the operating voltage for the different elements of the MIPI/SSIC-PHY/Link layer 104 and the function module 106. Furthermore, the mechanism of using two different voltages (VCC1 and VCC2) in different operating elements can improve work efficiency. In this embodiment, the first voltage terminal is arranged to receive a core voltage (Vcore), and the second voltage terminal is arranged to receive an I/O voltage (Vio). In other words, the first voltage VCC1 is the core voltage (Vcore), and the second voltage VCC2 is the I/O voltage (Vio), but it is not limited thereto. In other embodiments, the pin set 102 may have one power terminal. For example, the core voltage (Vcore) can be 2 volts, 3.9 volts, or any rational number between 2-3.9 can be regarded as the core voltage. The I/O voltage (Vio) can be 0.6 volts, 1.9 volts, or any rational number between 0.6-1.9 can be regarded as the I/O voltage. The clock terminal is arranged to receive a clock signal CLK arranged to be provided to the MIPI/SSIC-PHY/Link layer 104 and the function module 106. It should be noted that, in one of the embodiments, the pin set 102 may not include the clock terminal. The ground terminal is arranged to be connected to a ground GND.
The MIPI/SSIC-PHY/Link layer 104 is coupled to the first receiving terminal pair and the first transmitting terminal pair of the pin set 102. The MIPI/SSIC-PHY/Link layer 104 is arranged to receive the data RXD1+ and RXD1− which are compatible with the transmission protocol of the USB SSIC interface through the first receiving terminal pair, and transmit the data RXD1+ and RXD1− which are compatible with the transmission protocol of the USB SSIC interface to the function module 106. Moreover, the MIPI/SSIC-PHY/Link layer 104 is arranged to receive the data TXD1+ and TXD1− which are compatible with the transmission protocol of the USB SSIC interface from the function module 106, and transmit the data TXD1+ and TXD1− which are compatible with the transmission protocol of the USB SSIC interface to the first transmitting terminal pair. It should be noted that the MIPI/SSIC-PHY/Link layer 104 includes an MIPI PHY Layer 1042 and a SSIC Link layer 1044, wherein the power requirement of the MIPI PHY Layer 1042 of SSIC is lower than the PHY layer of USB.
The function module 106 is coupled to the MIPI/SSIC-PHY/Link layer 104, and the function module 106 is arranged to transmit data with the MIPI/SSIC-PHY/Link layer 104 by transmission protocol compatible with the USB SSIC interface. It should be noted that the specification of the protocol Layer of the USB SSIC interface is same as the protocol layer of the USB interface, the specification of the PHY layer (Physical Layer) of USB interface is different from the specification of the PHY layer of the USB SSIC interface, and the specification of the Link layer of the USB interface is different from the specification of the Link layer of the USB SSIC interface. In one embodiment, the function module 106 can be a memory module. The memory module includes a memory controller and a memory, but it is not limited thereto. The function module 106 can also be a wireless module, a bluetooth module, a near field communication module (NFC), a mobile communication module (3G/4G, LTE) and an I/O module.
The second receiving terminal pair is similar to the first receiving terminal pair and the second transmitting terminal pair is similar to the first transmitting terminal pair, wherein the second receiving terminal pair is arranged to receive the data RXD2+˜RXDN+ and RXD2−˜RXDN− which are compatible with the transmission protocol of the USB SSIC interface, and the second transmitting terminal pair is arranged to transmit the data TXD2+˜TXDN+ and TXD2−˜TXDN− which are compatible with the transmission protocol of the USB SSIC interface. Moreover, the details of the power terminal, the clock terminal and the ground terminal can be referred to in
The MIPI/SSIC-PHY/Link layer 104 is coupled to the first receiving terminal pair, the second receiving terminal pair, the first transmitting terminal pair and the second transmitting terminal pair of the pin set 102. The MIPI/SSIC-PHY/Link layer 104 is arranged to receive the data RXD1+˜RXDN+ and RXD1−˜RXDN− which are compatible with the transmission protocol of the USB SSIC interface through the first receiving pair and the second receiving terminal pair, and transmit the data RXD1+˜RXDN+ and RXD1−˜RXDN− which are compatible with the transmission protocol of the USB SSIC interface to the function module 106. Moreover, the MIPI/SSIC-PHY/Link layer 104 is further arranged to receive the data TXD1+˜TXDN+ and TXD1−˜TXDN− which are compatible with the transmission protocol of the USB SSIC interface from the function module 106, and transmit the data TXD1+˜TXDN+ and TXD1−˜TXDN− which are compatible with the transmission protocol of the USB SSIC interface to the first transmitting terminal pair and the second transmitting terminal pair. It should be noted that the MIPI/SSIC-PHY/Link layer 104 includes an MIPI PHY Layer 1042 and a SSIC Link layer 1044, wherein the power requirement of the MIPI PHY Layer 1042 of the USB SSIC interface is lower than that of the PHY layer of the USB interface. Moreover, the details of the function module 106 can be referred to in
The slot 402 is arranged to contain the removable electronic device 100 compatible with the USB SSIC interface, as shown in
The SSIC pin set 404 is arranged inside of the slot 402, wherein the SSIC pin set 404 is arranged to couple to the pin set 102 of the removable electronic device 100. In this embodiment, the SSIC pin set 404 includes a first receiving pin pair, a first transmitting pin pair, at least one power pin and a clock pin, but it is not limited thereto. The first receiving pin pair is arranged to be coupled to the first receiving terminal pair PRXD1+ and PRXD1− of the removable electronic device 100 for receiving the data RXD1+ and RXD1− which are compatible with the transmission protocol of the USB SSIC interface from the interface converting device 408 and transmitting the data RXD1+ and RXD1− which are compatible with the transmission protocol of the USB SSIC interface to the removable electronic device 100. The first transmitting pin pair is arranged to be coupled to the first transmitting terminal pair PTXD1+ and PTXD1− of the removable electronic device 100 for transmitting the data TXD1+ and TXD1− received from the removable electronic device 100 to the interface converting device 408. At least one power pin(s) is(s) arranged to contact the power terminal PVCC1 and PVCC2 of the removable electronic device 100 for providing at least one source voltage produced by the power regulator 410 to the removable electronic device 100. In one of the embodiments, the SSIC pin set 404 includes two power pins, such as the first power pin and the second power pin, but it is not limited thereto. The clock pin is arranged to electronically contact with the clock terminal PCLK of the removable electronic device 100 for providing a clock signal CLK to the removable electronic device 100. It should be noted that, in one embodiment, the SSIC pin set 404 may not include the clock pin, but it is not limited thereto. The ground pin is arranged to be connected to a ground GND. Moreover, those skilled in the art will recognize the design rule of the position of the SSIC pin set 404 of the slot 402 by the descriptions of
The first interface pin set 406 is arranged to be electronically connected with the host. Those skilled in the art can design the layout of the first interface pin set 406 to the specification of the first interface, but it is not limited thereto. For example, when the first interface is a USB 2.0 interface, the first interface pin set 406 has four pins with predetermined positions. When the first interface is the USB 3.0 interface, the first interface pin set 406 has nine pins with predetermined positions, but it is not limited thereto.
The interface converting device 408 is coupled between the SSIC pin set 404 and the first interface pin set 406, wherein the interface converting device 408 is arranged to convert the data compatible with a transmission protocol of the first interface and received from the host into data RXD1+ and RXD1− compatible with the transmission protocol of the USB SSIC interface for providing the converted data to the removable electronic device 100, and the interface converting device 408 is further arranged to convert the data TXD1+ and TXD1− which are compatible with the transmission protocol of the USB SSIC interface and received from the removable electronic device 100 into data compatible with a transmission protocol of the first interface for providing the converted data to the host. It should be noted that, in some embodiments, the interface converting device 408 is further arranged to produce the clock signal CLK compatible with the transmission protocol of the USB SSIC interface.
The power regulator 410 is arranged to receive at least one input voltage compatible with the first interface, and convert the input voltage into at least one source voltage compatible with the USB SSIC interface for providing the source voltage to the removable electronic device 100 through the SSIC pin set 404. In one embodiment, the power regulator 410 is arranged to convert the input voltage into a first voltage VCC1 and a second voltage VCC2 to provide the first voltage VCC1 and the second voltage VCC2 to the removable electronic device 100 through the first power pin and the second power pin of the at least one power pin. For example, the first voltage VCC1 is a core voltage (Vcore), and the second voltage VCC2 is the I/O voltage (Vio), but it is not limited thereto. In other the pin set 102 may have only one power terminal. For example, the core voltage (Vcore) can be 2 volts, 3.9 volts, or any rational number between 2-3.9 can be regarded as the value of the core voltage. The I/O voltage (Vio) can be 0.6 volt, 1.9 volt, or any rational number between 0.6-1.9 can be used for the volt number of the I/O voltage.
The SSIC pin set 404 not only includes the first receiving pin pair, the first transmitting pin pair, the at least one power pin and the clock pin, but also includes at least one second receiving pin pair and at least one second transmitting pin pair. The at least one second receiving pin pair is similar to the at least one first receiving pin pair, the second receiving pin pair is arranged to electronically contact with the at least one second receiving terminal pair PRXD2+˜PRXDN+ and PRXD2−˜PRXDN− of the removable electronic device 100 for receiving the data RXD2+˜RXDN+ and RXD2−˜RXDN− which are compatible with the transmission protocol of the USB SSIC interface from the interface converting device 408 and transmitting the data RXD2+˜RXDN+ and RXD2−˜RXDN− which are compatible with the transmission protocol of the USB SSIC interface to the removable electronic device 100. The at least one second transmitting pin pair is similar to the at least one first transmitting pin pair, the at least one second transmitting pin pair is arranged to electronically contact with the at least one second transmitting terminal pair PTXD2+˜PTXDN+ and PTXD2−˜PTXDN− of the removable electronic device 100 for transmitting the data TXD2+˜TXDN+ and TXD2−˜TXDN− which are compatible with the transmission protocol of the USB SSIC interface and received from the removable electronic device 100 to the interface converting device 408.
The interface converting device 408 is coupled between the SSIC pin set 404 and the first interface pin set 406, and arranged to conver the data which is compatible with the protocol of the first interface and received from the host into data RXD1+˜RXDN+ and RXD1−˜RXDN− which are compatible with the transmission protocol of the USB SSIC interface for providing the converted data to the removable electronic device 100, and convert the data TXD1+˜TXDN+ and TXD1−˜TXDN− which are compatible with the transmission protocol of the USB SSIC interface and received from the removable electronic device 100 into data which is compatible with the protocol of the first interface for providing the host. It should be noted that the interface converting device 408 is further arranged to produce a clock signal CLK compatible with the USB SSIC interface. The other details can be referred to in
The USB SSIC removable electronic device 100 of the embodiments may access data with higher speed (a single lane may reach 5 Gbps, and the speed of a multi-lane is a few times faster than the single lane according to the number of lane) by the USB SSIC interface. Furthermore, the layout of the removable electronic device 100 is compatible with the slot of Micro SD card, and the adapter device 400 can convert the data from the USB SSIC interface into data compatible with other interfaces.
Any data transmission methods, portions thereof, may take the form of a program code (i.e., executable instructions) embodied in tangible media, such as floppy diskettes, CD-ROMS, hard drives, or any other machine-readable storage medium, wherein, when the program code is loaded into and executed by a machine such as a computer, the machine thereby becomes an apparatus for practicing the methods. The methods may also be embodied in the form of a program code transmitted over some transmission medium, such as electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the program code is received and loaded into and executed by a machine such as a computer, the machine becomes an apparatus for practicing the disclosed methods. When implemented on a general-purpose processor, the program code combines with the processor to provide a unique apparatus that operates analogously to application-specific logic circuits.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.
Number | Date | Country | Kind |
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102144178 | Dec 2013 | TW | national |
This application claims the benefit of U.S. Provisional Application No. 61/760,782, filed Feb. 5, 2013, the entirety of which is incorporated by reference herein. Furthermore, this Application also claims priority of Taiwan Patent Application No. 102144178, filed on Dec. 3, 2013, the entirety of which is incorporated by reference herein.
Number | Date | Country | |
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61760782 | Feb 2013 | US |