Use of set-by-read and set-by-write registers as semaphores

Abstract

In response to a requester's execution of a first operation on a storage area containing a first indicator allowing at least one requester to access the component, the storage area changes the first indicator to a second indicator reducing by one a number of requesters that can access the component. Upon completion of access, the requester executes a second operation to replace the second indicator with a third indicator allowing access to an additional requester.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to coordinating access to shared resources in a computer system. More particularly, the present invention relates to using registers to coordinate access to the shared resources.

BACKGROUND OF THE INVENTION

[0002] A semaphore is a variable in a location in system memory, and indicates the availability of a resource shared by multiple processes in a computer system. Typically, each shared resource has its own semaphore. There are two main types of semaphores: counting semaphores and binary semaphores. A counting semaphore, the value of which can vary between zero and a predetermined positive number that represents the number of processes that can access the shared resource at the same time, is used when more than one process can access the shared resource at the same time. A binary semaphore, however, is used when only one process at a time can access the shared resource. Accordingly, a binary semaphore has only two values, one to show that a process is using the shared resource, and the other to show that no process is using the shared resource.

[0003] In order to access a shared resource using a binary semaphore, a process first reads the binary semaphore. If the current value of the binary semaphore indicates that the shared resource is not available, the process can do one of two things. The process can either abandon attempts to access the shared resource, or begin “spinning,” i.e., periodically re-reading the binary semaphore until the shared resource becomes available. Conversely, if the process reads the binary semaphore and the current value indicates that the shared resource is available, the process writes to the binary semaphore a value indicating to other processes that the shared resource is not available, and accesses the shared resource. When finished using the shared resource, the process releases it by writing to the binary semaphore a value indicating that the shared resource is available. If another process has been spinning, the read executed after the shared resource becomes available will reveal to the spinning process that the shared resource is available. The spinning process can then write to the binary semaphore a value indicating to other processes that the shared resource is not available and access the shared resource, as explained previously.

[0004] The sequence of reading a binary semaphore, determining that a shared resource is available, writing to the binary semaphore a value indicating to other processes that the shared resource is not available, and accessing the shared resource, is known as “read modify write” (RMW) access. RMW access must be “atomic,” i.e., continuous without interference, during the period between reading the binary semaphore when the shared resource is available, and writing to the binary semaphore a value indicating to other processes that the shared resource is not available. If an RMW by a first process is not atomic, then a second process can execute a separate read on the binary semaphore after the first process' read but prior to the first process' write. That is, if the first process does not write to the binary semaphore prior to the second process' read a value indicating that the shared resource is not available, the second process determines that the shared resource is available. Consequently, both the first process and the second process can write to the binary semaphore values indicating to other processes that the shared resource is not available. Each process will therefore believe it has exclusive access to the shared resource, thus resulting in a collision of accesses.

[0005] A process can use a “bus lock” to restrict access to a binary semaphore, thereby preventing another process from executing a read during an in-progress RMW, and eliminating the possibility of a collision of accesses to the shared resource. With a bus lock, a process, prior to reading the binary semaphore, locks the bus that provides access to the binary semaphore. The process then attempts RMW access, after which the bus is automatically unlocked. Finally, the process determines whether it was able to write to the binary semaphore a value indicating to other processes that the shared resource is not available. If so, then the shared resource was available at the time of the read, and thus the process can access the shared resource. If not, then the shared resource was not available at the time of the read, and the process cannot access the shared resource.

[0006] Though preventing an intervening read during an in-progress RMW, a bus lock can be implemented to restrict access to all semaphores, not just the semaphore subject to the RMW, until the RMW is complete. Furthermore, because semaphores are located in system memory, in some implementations a bus lock might prevent all processes, including those not attempting to read a semaphore, from accessing system memory. In addition, some computer systems do not have bus lock capability. These systems therefore use highly complex algorithms to provide atomic access to semaphores, which reduces system performance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

[0008] FIG. 1 is a block diagram of one embodiment of a computer system.

[0009] FIG. 2 is a flow chart of a method of one embodiment of a set-by-read register as a semaphore.

[0010] FIG. 3 is a flow chart of a method of one embodiment of a set-by-write register as a semaphore.

[0011] FIG. 4 is a block diagram of a computer system that contains one embodiment of a set-by-read register as a semaphore.

[0012] FIG. 5 is a block diagram of a computer system that contains one embodiment of a set-by-write register as a semaphore.

DETAILED DESCRIPTION

[0013] The use of a set-by-read register and a set-by-write register as semaphores is described. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention.

[0014] Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.

[0015] When a set-by-read register is used as a semaphore, a process reads the set-by-read register to determine whether a shared resource is available. As a result, the set-by-read register determines whether the shared resource is available. If the set-by-read register determines (e.g., by reading its value) that the shared resource is not available at the time of the process' read, then the set-by-read register maintains a value indicating that the shared resource is not available, and returns that value to the process. The process then determines that it has received from the set-by-read register the value indicating that the shared resource is not available, meaning that the process cannot access the shared resource. Consequently, the process either can periodically re-read the set-by-read register until the shared resource becomes available, or abandon attempts to access the shared resource.

[0016] Conversely, if the set-by-read register determines that the shared resource is available at the time of the process' read, then the set-by-read register sets itself to a value indicating to other processes and to itself that the shared resource is not available. The set-by-read register then returns to the process a value indicating that the shared resource is available, and the process determines that it has received that value from the set-by-read register. Therefore, the process accesses the shared resource, and when finished using the shared resource, writes to the set-by-read register a value indicating that the shared resource is available.

[0017] With a set-by-write register used as a semaphore, a process writes its identifier to the set-by-write register. As a result, the set-by-write register determines whether the shared resource is available. If the set-by-write register determines that it contains a value indicating that the shared resource is not available, then the set-by-write register maintains its current value, and does not set itself to the process' identifier as a result of the write. Conversely, if the set-by-write register determines that it contains a value indicating that the shared resource is available at the time of the process' write, then execution of the write causes the set-by-write register to set itself to the process' identifier.

[0018] Once the set-by-write register has either maintained its current value or set itself to the process' identifier, the process executes a read on the set-by-write register. If the set-by-write register does not contain the process' identifier, the process cannot access the shared resource. The process then either can periodically re-write its identifier to the set-by-write register, followed by execution of a read, until the shared resource becomes available, or abandon attempts to access the shared resource. Conversely, if the process executes the read and the set-by-write register contains the process' identifier, the process accesses the shared resource. As a result, if another process attempts to access the shared resource, the set-by-write register determines that it contains an identifier, which indicates to the set-by-write register that the shared resource is not available. The set-by-write register then can indicate the identifier to the other process, not only to show that the shared resource is unavailable, but also to identify the process that is using the shared resource. When the process has finished using the shared resource, the process writes to the set-by-write register a value indicating that the shared resource is available.

[0019] FIG. 1 is a block diagram of one embodiment of a computer system. The computer system is intended to represent a range of computer systems, including, for example, a personal digital assistant (PDA), a laptop or palmtop computer, a cellular phone, etc. Other computer systems can include more, fewer and/or different components.

[0020] Computer system 100 includes a bus 110 or other communication device to communicate information, and processor 120 coupled to bus 110 to process information. While computer system 100 is illustrated with a single processor, computer system 100 can include multiple processors and/or co-processors. Bus 110 encompasses all buses that may be present in a computer system, e.g., a Peripheral Component Interconnect (PCI) bus; a Personal Computer Memory Card International Association (PCMCIA) bus; a Universal Serial Bus (USB), etc. See, e.g., PCI Local Bus Specification Revision 2.2, released Dec. 18, 1998; PC Card Standard, March 1997 Release, First Printing; Universal Serial Bus Specification Revision 2.0, issued Apr. 27, 2000.

[0021] Computer system 100 further includes random access memory (RAM) or other dynamic storage device 130 (referred to as main memory), coupled to bus 110 to store information and instructions to be executed by processor 120. Main memory 130 also can be used to store temporary variables or other intermediate information while processor 120 is executing instructions. Computer system 100 also includes read-only memory (ROM) and/or other static storage device 140 coupled to bus 110 to store static information and instructions for processor 120. In addition, data storage device 150 is coupled to bus 110 to store information and instructions. Data storage device 150 may comprise a magnetic disk (e.g., a hard disk) or optical disc (e.g., a CD-ROM) and corresponding drive.

[0022] Computer system 100 may further comprise a flat-panel display device 160, such as a cathode ray tube (CRT) or liquid crystal display (LCD), to display information to a user. Alphanumeric input device 170, including alphanumeric and other keys, is typically coupled to bus 110 to communicate information and command selections to processor 120. Another type of user input device is cursor control 175, such as a mouse, a trackball, or cursor direction keys to communicate direction information and command selections to processor 120 and to control cursor movement on flat-panel display device 160. Computer system 100 further includes network interface 180 to provide access to a network, such as a local area network.

[0023] Instructions are provided to memory from a machine-accessible medium, or an external storage device accessible via a remote connection (e.g., over a network via network interface 180). A machine-accessible medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine (e.g., a computer). For example, a machine-accessible medium includes RAM; ROM; magnetic or optical storage medium; flash memory devices; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals); etc.

[0024] In alternative embodiments, hard-wired circuitry can be used in place of or in combination with software instructions to implement the present invention. Thus, the present invention is not limited to any specific combination of hardware circuitry and software instructions.

[0025] FIG. 2 is a flow chart of the operation of a set-by-read register as a semaphore. At 200, a process needing access to a shared resource reads a set-by-read register controlling access to the shared resource. A process is an instance of a program running in a computer. A process is well-known to those of ordinary skill in the art, and thus will not be discussed further except as it pertains to the present invention. In one embodiment, the process is running in the central processing unit (CPU) of the computer system. However, the process can be running in another location of the computer system, e.g., main memory. A shared resource can be a peripheral device (such as a printer or disk drive) or memory, etc. A register is a data storage area. A register is well-known to those of ordinary skill in the art, and thus will not be discussed further except as it pertains to the present invention. A set-by-read register can change the content of its data whenever a read operation is performed on the set-by-read register. In one embodiment, the set-by-read register is located at the shared resource. However, the set-by-read register also can be located at another location in the computer system, e.g., the CPU. At 210, the set-by-read register determines whether the shared resource is available, so that the set-by-read register can determine whether to change its value as a result of the process' read. In one embodiment, the set-by-read register reads its value to determine whether the shared resource is available. However, the set-by-read register, either in lieu of or in addition to reading its value, could read an indicator that is available to the set-by-read register only and not to a process, to determine whether the shared resource is available. For example, the set-by-read register could read a flag (i.e., a software or hardware indicator which is like a switch that can be either on or off to signal a particular condition or status) to determine whether the shared resource is available.

[0026] If at 210 the set-by-read register determines the shared resource is not available at the time the process' read, then at 211 the set-by-read register maintains a value indicating that the shared resource is not available, and at 212 returns that value to the process. Conversely, if at 210 the set-by-read register determines that the shared resource is available, then at 215 as a result of the process' read, the set-by-read register sets itself to a value indicating to other processes and to itself that the shared resource is not available. At 216, the set-by-read register returns to the process the value indicating that the shared resource is available. Consequently, if another process executes a subsequent read on the set-by-read register, the set-by-read register determines that the shared resource is not available, and thus does not change its value as a result of the subsequent read.

[0027] At 220, the process determines whether as a result of its read it received from the set-by-read register a value indicating that the shared resource is available, meaning that the process has access to the shared resource. If the process received from the set-by-read register a value indicating that the shared resource is not available, then the process cannot access the shared resource, and at 225 determines whether to wait for the shared resource to become available. In one embodiment, the process can re-read the set-by-read register periodically until the shared resource becomes available, or abandon its current attempt to access the shared resource.

[0028] Conversely, if at 220 the process determines that it received from the set-by-read register a value indicating that the shared resource is available, then at 230, the process accesses the shared resource. When the process has finished using the shared resource, at 240 the process writes to the set-by-read register a value indicating that the shared resource is available.

[0029] In one embodiment, each process attempting to access a shared resource reads one set-by-read register in a specific location (e.g., at the shared resource) known to all processes. In another embodiment, a main set-by-read register that is not accessible to any process is linked to other set-by-read registers at several locations. Each linked set-by-read register is associated with only one process, and is in a specific location known only to its process. When a first process reads its associated set-by-read register, the linked set-by-read register associated with the first process reads the main set-by-read register. The main set-by-read register determines whether the shared resource is available, and thus whether to change its value as a result of the first process' read, as explained previously. While the main set-by-read register is determining whether the shared resource is available, linked set-by-read registers associated with processes other than the first process cannot read the main set-by-read register.

[0030] If the main set-by-read register determines that the shared resource is available, it sets itself to a value indicating that the shared resource is not available. Having read the main set-by-read register when it contained the value indicating that the shared resource is available, the linked set-by-read register associated with the first process returns to the first process the value indicating that the shared resource is available. As a result, the first process determines that it received from its associated set-by-read register a value indicating that the shared resource is available, meaning that the first process can access the shared resource. Finally, once the linked set-by-read register associated with the first process has completed its read of the main set-by-read register, the other linked set-by-read registers, if read by their associated processes, can read the main set-by-read register. Any of these other linked set-by-read registers that reads the main set-by-read register will read the value indicating that the shared resource is not available, and return to its associated process the value indicating that the shared resource is not available.

[0031] When the first process has finished using the shared resource, it writes to its associated set-by-read register a value indicating that the shared resource is available. The set-by-read register associated with the first process sends to the main set-by-read register the value indicating that the shared resource is available. The main set-by-read register determines that the shared resource has become available, and thus sets itself to the value indicating that the shared resource is available. As a result, the next set-by-read register that reads the main set-by-read register will read the value indicating that the shared resource is available, and return to its associated process the value indicating that the shared resource is available. The coordination of the linked set-by-read registers indicating to their associated processes the value contained in the main set-by-read register may be accomplished by any means in the art, e.g., hardware circuitry, software instructions, etc.

[0032] If a set-by-read register contains a value indicating that a shared resource is available, then execution of a single action, i.e., a read, causes the set-by-read register to set itself to a value indicating to other processes and to itself that the shared resource is not available. Consequently, there is no opportunity, between a process' read and the set-by-read register setting itself to a value indicating that the shared resource is not available, for another process to execute a read and determine that the shared resource is available. The sequence of events providing access to the shared resource is therefore atomic. Thus, there is no need for a bus lock to prevent a collision of accesses to the shared resource due to execution of an intervening read between the process' read and the set-by-read register setting itself to a value indicating that the shared resource is not available.

[0033] FIG. 2 describes the invention in terms of a method. However, one should also understand it to represent a machine-accessible medium having recorded, encoded or otherwise represented thereon instructions, routines, operations, control codes, or the like, that when executed by or otherwise utilized by the machine, cause the machine to perform the method as described above or other embodiments thereof that are within the scope of this disclosure.

[0034] FIG. 3 is a flow chart of the operation of a set-by-write register as a semaphore. At 300, a process needing access to a shared resource writes its identifier to a set-by-write register controlling access to the shared resource. A set-by-write register can change the content of its data whenever a write operation is performed on the set-by-write register. In one embodiment, the set-by-write register is located at the shared resource. However, the set-by-write register also can be located at another location in the computer system, e.g., the CPU.

[0035] At 310, the set-by-write register determines whether the shared resource is available, so that the set-by-write register can determine whether to set itself to the process' identifier as a result of the process' write. In one embodiment, the set-by-write register reads its value to determine whether the shared resource is available. However, the set-by-write register, either in lieu of or in addition to reading its value, could read an indicator that is available to the set-by-write register only and not to a process, to determine whether the shared resource is available. For example, the set-by-write register could read a flag to determine whether the shared resource is available.

[0036] If the set-by-write register determines that the shared resource is not available at the time the process writes its identifier, then at 315 the set-by-write register maintains a value indicating that the shared resource is not available. Conversely, if the process writes its identifier to the set-by-write register and the set-by-write register determines that the shared resource is available, then at 320 the set-by-write register sets itself to the process' identifier. By setting itself to the process' identifier, the set-by-write register indicates to other processes and to itself that the shared resource is not available. Thus, if another process attempts to write a new identifier to the set-by-write register, the set-by-write register determines that it already contains an identifier and does not change its value to the new identifier as a result of the other process' write, because the shared resource is not available. In one embodiment, if a process attempts to access a shared resource via a set-by-write register when the set-by-write register contains another process' identifier, the set-by-write register will indicate the identifier as the value in the set-by-write register. As a result, the set-by-write register can indicate not only that the shared resource is unavailable, but also provide the identity of the process using the shared resource.

[0037] Once the set-by-write register has either maintained a value indicating that the shared resource is not available or set itself to the process' identifier, at 330 the process reads the set-by-write register. At 340, the process determines whether the set-by-write register contains the process' identifier. If the set-by-write register has maintained a value indicating that the shared resource is not available, then the process cannot access the shared resource, and at 345 determines whether to wait for the shared resource to become available. In one embodiment, the process can re-write its identifier to the set-by-write register periodically, followed by execution of a read, until the shared resource becomes available, or abandon its current attempt to access the shared resource.

[0038] Conversely, if at 340 the process determines that the set-by-write register has set itself to the process' identifier as a result of the process writing its identifier to the set-by-write register, then at 350 the process accesses the shared resource. At 360, having finished using the shared resource, the process writes to the set-by-write register a value indicating that the shared resource is available.

[0039] In one embodiment, each process attempting to access the shared resource writes its identifier to one set-by-write register in a specific location (e.g., at the shared resource) known to all processes. In another embodiment, a main set-by-write register in a specific location is linked to other set-by-write registers at several locations. Each linked set-by-write register is associated with only one process, and is in a specific location known only to its process. When a first process writes its identifier to its associated set-by-write register, the linked set-by-write register associated with the first process sends the first process' identifier to the main set-by-write register and reads the main set-by-write register. The main set-by-write register determines whether the shared resource is available, and thus whether to change its value as a result of the process' write, as explained previously. While the main set-by-write register is determining whether the shared resource is available, linked set-by-write registers associated with other processes other than the first process cannot send their process' identifiers to the main set-by-write register.

[0040] If the main set-by-write register determines that the shared resource is available, it sets itself to the first process' identifier. Thereafter, when any process (including the first process) reads its linked set-by-write register, the linked set-by-write register associated with the process reads the main set-by-write register. Because the main set-by-write register contains as its value the first process' identifier, the linked set-by-write register returns to its associated process the first process' identifier.

[0041] The process then compares its own identifier to the value (i.e., the first process' identifier) returned by the process' associated set-by-write register from the main-set-write register. As a result, only the first process will determine a match between its identifier and the value returned by its associated set-by-write register from the main-set-write register. Thus, the first process has access to the shared resource. Conversely, every other process will determine that its identifier does not match the value returned by the process' associated set-by-write register from the main-set-write register. Accordingly, no other process can access the shared resource.

[0042] When the first process has finished using the shared resource, it writes to its associated set-by-write register a value indicating that the shared resource is available. The set-by-write register associated with the first process sends to the main set-by-write register the value indicating that the shared resource is available. The main set-by-write register determines that the shared resource has become available, and thus sets itself to the value indicating that the shared resource is available. As a result, the next set-by-write register that reads the main set-by-write register will read the value indicating that the shared resource is available, and return to its associated process the value indicating that the shared resource is available. The coordination of the linked set-by-read registers indicating to their associated processes the value contained in the main set-by-read register may be accomplished by any means in the art, e.g., hardware circuitry, software instructions, etc.

[0043] If a set-by-write register contains a value indicating that a shared resource is available, execution of a single action, i.e., a write, causes the set-by-write register to set itself to a value, e.g., a process' identifier, indicating that the shared resource is not available. Consequently, there is no opportunity between a process writing the identifier to the set-by-write register and the set-by-write register setting itself to the identifier to indicate that the shared resource is not available for another process to execute a write and obtain access to the shared resource. The sequence of events providing access to the shared resource is therefore atomic. Thus, there is no need for a bus lock to prevent a collision of accesses to the shared resource due to execution of an intervening write to the set-by-write register between the process' write and the set-by-write register setting itself to indicate that the shared resource is not available.

[0044] FIG. 3 describes the invention in terms of an identifier written to the set-by-write register in an attempt to access the shared resource. However, one should understand that a value other than an identifier could be written to the set-by-write register to attempt to access the shared resource. In addition, FIG. 3 describes the invention in terms of an identifier as the value indicating that the shared resource is not available. However, one should understand that the set-by-write register can, as a result of a process executing a write to the set-by-write register when the shared resource is available, set itself to a value other than an identifier in order to indicate that the shared resource is not available.

[0045] FIG. 3 describes the invention in terms of a method. However, one should also understand it to represent a machine-accessible medium having recorded, encoded or otherwise represented thereon instructions, routines, operations, control codes, or the like, that when executed by or otherwise utilized by the machine, cause the machine to perform the method as described above or other embodiments thereof that are within the scope of this disclosure.

[0046] FIG. 4 is computer system 100 modified to include one embodiment of a set-by-read register as a semaphore. Shared resource 190 (e.g., a peripheral device) of computer system 100 contains a set-by-read register 400, which controls access to shared resource 190. Value 401 of set-by-read register 400 is set to shared resource available value 403. Requester one 420 in processor 120 contains a register reader 421 that reads set-by-read register 400. Set-by-read register 400 determines that value 401 contains shared resource available value 403, which indicates that shared resource 190 is available. Thus, the read by register reader 421 causes value changer 402 to set value 401 from shared resource available value 403 to shared resource unavailable value 404 to indicate to other requesters and to set-by-read register 400 that shared resource 190 is not available. Set-by-read register 400 then returns to requester one 420 shared resource available value 403.

[0047] Requester one 420 determines that it has received from set-by-read register 400 shared resource available value 403, meaning that it has access to shared resource 190. Thus, resource user 422 accesses shared resource 190. If register reader 431 of requester two 430 reads set-by-read register 400 to determine the availability of shared resource 190 while requester one 420 has access to shared resource 190, set-by-read register 400 determines based on shared resource unavailable value 404 that shared resource 190 is not available. As a result, value changer 402 does not change value 401, which maintains shared resource unavailable value 404. When requester one 420 has finished using shared resource 190, resource use completion indicator 423 of resource user 422 notifies resource use completion writer 424. Resource use completion writer 424 then writes to value 401 shared resource available value 425 indicating that shared resource 190 is available, which replaces shared resource unavailable value 404.

[0048] FIG. 5 is computer system 100 modified to include one embodiment of a set-by-write register as a semaphore. Shared resource 190 (e.g., a peripheral device) of computer system 100 contains a set-by-write register 500, which controls access to shared resource 190. Value 501 of set-by-write register 500 is set to shared resource available value 503. Requester one 520 in processor 120 contains identifier writer 521, which writes identifier 522 of requester one 520 to set-by-write register 500. Set-by-write register 500 determines based on shared resource available value 503 that shared resource 190 is available. Consequently, the write of identifier 522 to set-by-write register 500 causes value changer 502 of set-by-write register 500 to set value 501 to identifier of requester using shared resource 504. Value changer 502 then writes identifier 522 to identifier of requester using shared resource 504, to indicate to other requesters and to set-by-write register 500 that shared resource 190 is not available.

[0049] Register reader 523 of requester one 520 then reads set-by-write register 500 to determine whether set-by-write register 500 contains identifier 522. Once requester one 520 determines that value 501 contains identifier 522, resource user 524 of requester one 520 accesses shared resource 190. If requester two 530 attempts to access shared resource 190 by identifier writer 531 executing a write, followed by register reader 533 executing a read, set-by-write register 500 determines that value 501 contains identifier 522. Thus, set-by-write register indicates identifier 522 to indicate to requester two 530 that requester one 520 is using shared resource 190, which is therefore unavailable.

[0050] When requester one 520 has finished using shared resource 190, resource use completion indicator 525 of resource user 524 notifies resource use completion writer 526. Resource use completion writer 526 then writes to value 501 shared resource available value 527 indicating that shared resource 190 is available, which replaces identifier of requester using shared resource 504 containing identifier 522.

[0051] FIGS. 4 and 5 show processor 120 and shared resource 190 communicating directly. However, one should understand that processor 120 and shared resource 190 communicate via bus 110. FIGS. 4 and 5 show direct communication between processor 120 and shared resource 190 merely for convenience.

[0052] FIGS. 2 through 5 describe the invention in terms of a binary semaphore for purposes of illustration and ease of explanation. However, use of a set-by-read register or a set-by-write register as a semaphore is not limited to a binary semaphore. Furthermore, FIGS. 2 through 5 describe the invention in terms of a process attempting to access a shared resource. However, one should understand that the invention is not limited to use of a set-by-read or set-by-write register by a process (i.e., a requester can be other than a process), and that the requester can access a component other than a shared resource.

[0053] In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method, comprising: determining, in response to being accessed by a first requester, whether a component is available; and replacing, if the component is available, a first indicator indicating that the shared resource is available, with a second indicator reducing access to the component, to permit access to the component by the first requester.

2. The method of claim 1, further comprising: indicating, if the component is unavailable, the second indicator to the first requester to prohibit access to the component by the first requester.

3. The method of claim 2, wherein being accessed by the first requester comprises the first requester executing a read.

4. The method of claim 3, further comprising indicating the first indicator to the first requester to indicate that the first requester can access the component.

5. The method of claim 2, wherein being accessed comprises the first requester executing a write of the second indicator.

6. The method of claim 5, wherein the second indicator comprises an identifier of the first requester.

7. The method of claim 2, wherein determining, in response to being accessed by the first requester, whether the component is available comprises determining a presence of the first indicator.

8. The method of claim 2, wherein determining, in response to being accessed by the first requester, whether the component is available comprises determining based on an external indicator that the component is available.

9. The method of claim 8, wherein the external indicator comprises a flag.

10. The method of claim 2, further comprising receiving, by execution of an operation by a second requester upon completion of access to the component by the second requester, a third indicator increasing access to the component to replace the second indicator.

11. The method of claim 10, wherein the operation comprises a write of the third indicator.

12. The method of claim 11, wherein the first requester and the second requester comprise processes.

13. The method of claim 11, wherein the first requester and the second requester comprise one requester.

14. The method of claim 11, wherein the first indicator and the third indicator comprise a same indicator.

15. A method, comprising: determining, in response to being accessed by a first requester, whether a component is available; prohibiting accesses by one or more additional requesters; replacing, because the component is available, a first indicator indicating that the component is available, with a second indicator reducing access to the component; and allowing the first requester to indicate that the component is available.

16. The method of claim 15, wherein being accessed comprises the first requester executing a read.

17. The method of claim 16, wherein the first requester and the one or more additional requesters comprise registers.

18. The method of claim 17, wherein the registers comprise set-by-read registers read by processes attempting to access the component.

19. The method of claim 17, wherein the registers comprise set-by-write registers written to by processes attempting to access the component.

20. The method of claim 17, wherein the accesses by the one or more requesters comprise reads.

21. The method of claim 17, wherein the accesses by the one or more requesters comprise writes of indicators of processes attempting to access the component.

22. The method of claim 17, wherein determining, in response to being accessed by the first requester, whether the component is available comprises determining a presence of the first indicator indicating that a component is available.

23. The method of claim 17, wherein determining, in response to being accessed by the first requester, whether the component is available comprises determining based on an external indicator that the component is available.

24. The method of claim 23, wherein the external indicator comprises a flag.

25. The method of claim 17, further comprising: receiving from a second requester a third indicator increasing access to the component; determining, because of receiving the third indicator, that access to the component has been increased; and replacing the second indicator with the third indicator increasing access to the component.

26. The method of claim 25, wherein the first requester and the second requester comprise one requester.

27. A method of obtaining access to a shared resource, comprising: accessing a register; and changing, as a result of accessing the register if the register detects a first value; indicating that the shared resource is available, the first value to a second value; and limiting access to the shared resource.

28. The method of claim 27, wherein accessing the register comprises reading the register.

29. The method of claim 27, wherein accessing the register comprises writing the second value to the register.

30. The method of claim 29, wherein the second value comprises an identifier of a process.

31. The method of claim 30, further comprising reading the register to determine that the register contains the identifier.

32. The method of claim 27, wherein the shared resource comprises a peripheral device in a computer system.

33. The method of claim 27, further comprising: receiving from the register the first value indicating that the shared resource is available; accessing the shared resource; and changing upon completion of access to the shared resource, the second value to a third value increasing access to the shared resource.

34. The method of claim 33, wherein changing the second value to the third value comprises writing the third value to the register.

35. The method of claim 34, wherein the first value, the second value and the third value comprise variables.

36. The method of claim 35, wherein the first value and the third value comprise a same variable.

37. A method, comprising: executing by a process an operation; determining by a register, in response to the operation, whether a first indicator allowing access to a shared resource is present in the register; changing by the register if the first indicator is present, the first indicator to a second indicator reducing access the shared resource; sending by the register the first indicator to the process; determining by the process receipt of the first indicator; using by the process the shared resource; and replacing by the process the second indicator with a third indicator increasing access to the shared resource.

38. The method of claim 37, wherein the operation comprises a read of the register.

39. The method of claim 38, wherein the register comprises a set-by-read register.

40. The method of claim 37, wherein the operation comprises a write of the second indicator to the register.

41. The method of claim 40, wherein the register comprises a set-by-write register.

42. The method of claim 41, wherein the second indicator comprises an identifier of the user.

43. The method of claim 42, further comprising reading the register to determine that the register contains the identifier.

44. The method of claim 43, wherein replacing the second indicator with the third indicator comprises writing the third indicator to the register.

45. The method of claim 44, wherein the first indicator and the third indicator comprise the same indicator.

46. An article of manufacture comprising a machine-accessible medium including thereon sequences of instructions that, when executed, cause a machine to: determine, in response to being accessed by a first requester, whether a component is available; and replace, if the component is available, a first indicator indicating that the shared resource is available, with a second indicator reducing access to the component, to permit access to the component by the first requester.

47. The article of claim 46, further comprising sequences of instructions that, when executed, cause a machine to indicate, if the component is unavailable, the second indicator to the first requester to prohibit access to the component by the first requester.

48. The article of claim 47, wherein the sequences of instructions that cause the machine to determine, in response to being accessed by the first requester, whether the component is available comprise sequences of instructions that, when executed, cause the machine to determine, in response to the first requester executing a read, whether the component is available.

49. The article of claim 48, further comprising sequences of instructions that, when executed, cause the machine to indicate the first indicator to the first requester to indicate that the first requester can access the component.

50. The article of claim 47, wherein the sequences of instructions that cause the machine to determine, in response to being accessed by the first requester, whether the component is available comprise sequences of instructions that, when executed, cause the machine to determine, in response to the first requester executing a write of the second indicator, whether the component is available.

51. The article of claim 50, wherein the sequences of instructions that cause the machine to determine, in response to the first requester executing a write of the second indicator, whether the component is available comprise sequences of instructions that, when executed, cause the machine to determine, in response to the first requester executing the write of an identifier of the first requester, the presence of the indicator.

52. The article of claim 47, wherein the sequences of instructions that cause the machine to determine, in response to being accessed by the first requester, whether the component is available comprise sequences of instructions that, when executed, cause the machine to determine, in response to being accessed by the first requester, a presence of the first indicator.

53. The article of claim 47, wherein the sequences of instructions that cause the machine to determine, in response to being accessed by the first requester, whether the component is available comprise sequences of instructions that, when executed, cause the machine to determine, in response to being accessed by the first requester, that the component is available based on an external indicator.

54. The article of claim 53, wherein the sequences of instructions that cause the machine to determine, in response to being accessed by the first requester, based on an external indicator that the component is available comprise sequences of instructions that, when executed, cause the machine to determine, in response to being accessed by the first requester, that the component is available based on a flag.

55. The article of claim 47, further comprising sequences of instructions that, when executed, cause the machine to receive, by execution of an operation by a second requester upon completion of access to the component by the second requester, a third indicator increasing access to the component to replace the second indicator.

56. The article of claim 55, wherein the sequences of instructions that cause the machine to receive, by execution of the operation by the second requester upon completion of access to the component by the second requester, the third indicator increasing access to the component to replace the second indicator comprise sequences of instructions that, when executed, cause the machine to receive, by execution of a write of the third indicator by the second requester upon completion of access to the component by the second requester, the third indicator increasing access to the component to replace the second indicator.

57. The article of claim 56, wherein the first requester and the second requester comprise processes.

58. The article of claim 56, wherein the first requester and the second requester comprise one requester.

59. The article of claim 56, wherein the first indicator and the third indicator comprise a same indicator.

60. An article of manufacture comprising a machine-accessible medium including thereon sequences of instructions that, when executed, cause a machine to: determine, in response to being accessed by a first requester, whether a component is available; prohibit accesses by one or more additional requesters; replace, because the component is available, a first indicator indicating that the component is available, with a second indicator reducing access to the component; and allow the first requester to indicate that the component is available.

61. The article of claim 60, wherein the sequences of instructions that cause the machine to determine, in response to being accessed by the first requester, whether the component is available comprise sequences of instructions that, when executed, cause the machine to determine, in response to the first requester executing a read, whether the component is available.

62. The article of claim 61, wherein the first requester and the one or more additional requesters comprise registers.

63. The article of claim 62, wherein the registers comprise set-by-read registers read by processes attempting to access the component.

64. The article of claim 62, wherein the registers comprises a set-by-write registers written to by processes attempting to access the component.

65. The article of claim 62, wherein the sequences of instructions that cause the machine to prohibit accesses by one or more additional requesters comprise sequences of instructions that, when executed, cause the machine to prohibit reads by one or more additional requesters.

66. The article of claim 62, wherein the sequences of instructions that cause the machine to prohibit accesses by one or more additional requesters comprise sequences of instructions that, when executed, cause the machine to prohibit writes of identifiers of processes attempting to access the component by one or more additional requesters.

67. The article of claim 62, wherein the sequences of instructions that cause the machine to determine, in response to being accessed by the first requester, whether the component is available comprise sequences of instructions that, when executed, cause the machine to determine, in response to being accessed by the first requester, a presence of the first indicator.

68. The article of claim 62, wherein the sequences of instructions that cause the machine to determine, in response to being accessed by the first requester, whether the component is available comprise sequences of instructions that, when executed, cause the machine to determine, in response to being accessed by the first requester, that the component is available based on an external indicator.

69. The article of claim 68, wherein the sequences of instructions that cause the machine to determine, in response to being accessed by the first requester, based on an external indicator that the component is available comprise sequences of instructions that, when executed, cause the machine to determine, in response to being accessed by the first requester, that the component is available based on a flag.

70. The article of claim 62, further comprising sequences of instructions that, when executed, cause a machine to: receive from a second requester a third indicator increasing access to the component; determine, because of receiving third indicator, that access to the component has been increased; and replace the second indicator with the third indicator increasing access to the component.

71. The article of claim 70, wherein the first requester and the second requester comprise one requester.

72. An apparatus comprising: a resource; a storage area in the resource; a first value in the storage area, which the storage area changes to a second value in response to access to the storage area; and the second value in the storage area.

73. The apparatus of claim 72, wherein the resource comprises a peripheral device in a computer system.

74. The apparatus of claim 72, wherein the storage area comprises a register.

75. The apparatus of claim 72, wherein the access to the storage area comprises a read of the storage area.

76. The apparatus of claim 72, wherein the access to the storage area comprises a write to the storage area.

77. The apparatus of claim 72, wherein the first value indicates that the resource is available.

78. The apparatus of claim 72, wherein the second value reduces access to the resource.

79. The apparatus of claim 72, wherein the storage area is linked to other storage areas containing the first value.

80. The apparatus of claim 79, wherein the other storage areas change the first value to the second value when the storage area changes the first value to the second value.