Claims
- 1. A method for growing an InGaAs expitaxial layer on a lattice mismated InP substrate, comprising the steps of:providing an InP substrate; depositing one or more InAsyP1−y buffer layers on the InP substrate by an epitaxial growth process, each InAsyP1−y layer having a lattice-mismatch greater than 0.26% but less than 1.3% relative to the previous layers; stepping a level of y by an increment of at least 0.13 between successive layers; and depositing an InxGa1−xAs epitaxial over the InAsyP1−y buffer wherein 0.53≦x≦0.76 and the InGaAs is lattice matched to the uppermost InAsP buffer layer.
- 2. The method of claim 1 wherein the InxGa1−xAs epitaxial layer has a band gap in the range of about 0.55 eV to about 0.74 eV.
- 3. The method of claim 1 wherein a second InAsyP1−y layer is grown on a first InAsyP1−y layer with a lattice mismatch as high as 1.3% relative to the underlying layer.
- 4. The method of claim 1 wherein the steps of depositing are done at temperatures at which vapor phase epitaxy occurs without a need for subsequent heat treatment.
- 5. The method of claim 1 wherein a value of y increases by-an upward increment between 0.13 and 0.35.
- 6. The method of claim 1 including the step of;depositing up to two InAsyP1−y buffer layers on the InP substrate by an epitaxial growth process.
- 7. A method for growing an InGaAs epitaxial layer on an InP substrate, comprising the steps of:depositing by an epitaxial growth process two or less discreet layers of InAsyP1−y over an InP substrate to provide a buffer, each succeeding buffer layer having a distinct composition which produces less than a critical amount of lattice mismatch relative to the preceding layer and increasing yield strength; stepping a level of y by an increment of at least 0.13 between layers; and growing an InxGa1−xAs epitaxial layer over the buffer, wherein 0.53≦x≦0.76.
- 8. The method of claim 7 wherein the InAsyP1−y layer has a lattice mismatch no more than 1.3%.
- 9. The method of claim 8 wherein the InAsyP1−y layer has a lattice mismatch greater than 0.26%.
- 10. The method of claim 7 wherein a change is y between layers is an upward step between 0.13 and 0.35.
Parent Case Info
This application claims the benefit of Provisional Application Serial 60/064,413 filed Nov. 6, 1997.
Government Interests
The U.S. Government has a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of PR. No. 73-907775 awarded by Bettis Atomic Power Laboraty.
US Referenced Citations (6)
Non-Patent Literature Citations (4)
Entry |
High-Performance, Lattice-Mismatched InGaAs/InP Monolithic Interconnected Modules (MIMs) 1998 NREL TPV Conference. |
InGaAs/InAsP lasers with output wavelengths of 1.58-2.45 μm Martinelli, Zamerowski, and Longeway Appl. Phys. Lett., vol. 54, No. 3, Jan. 16, 1989. |
Efficient 2.0-2.6 μm Wavelength Photoluminescence from Narrow Bandgap InAsP/ InGaAs Double Heterostructures Grown on InP Substrates Journal of Electronic Materials, vol. 25, No. 9, 1996. |
Selective area MOVPE growth of InP, InGaAs and InGaAsP using TBAS and TBP at different growth conditions—Journal of Crystal Growth 170 (1997) 645-649. |
Provisional Applications (1)
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Number |
Date |
Country |
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60/064413 |
Nov 1997 |
US |