The present invention relates to a computer program product, system, and method for using a machine learning module to determine a group of execution paths of program code and a computational resource allocation to use to execute the group of execution paths.
A program is comprised of multiple activity steps that may be arranged in different execution paths to execute in parallel to reduce execution time. An activity step comprises a group of computer operations that perform an activity as part of the program code operations. The time required to complete processing an execution path depends on the processor and memory resources assigned to execute the activity steps in the execution path. Increasing the amount of processor and memory resources assigned to an execution path reduces the execution time. Likewise decreasing processor and memory resource increases the time to execute the execution path.
Different activity steps in a workflow or sequence of activity steps take different amounts of time to complete and have different complexities. A critical execution path comprises a sequency of activity steps that require the longest duration to execute of the different parallel execution paths. In this way, the bottleneck in completing processing the activity steps comprises the critical execution path that takes the longest time to execute. A greater amount of processor and memory resources may be assigned to the critical path in the workflow to reduce the overall execution time of the execution paths executed in parallel and improve the overall performance in completing execution of the activity steps of the program code.
There is a need in the art for improved techniques to determine execution paths of activity steps in program code and the computational resources to assign to the execution paths to optimize the execution of the program code.
Provided are computer program product, system, and method for using a machine learning module to determine a group of execution paths of program code and a computational resource allocation to use to execute the group of execution paths. Information on activity steps in program code and a system load of a system in which the program code is executed are provided as inputs to a resource allocation machine learning module. The resource allocation machine learning module processes the provided inputs to output computational resource allocations for execution paths of activity steps in the program code to execute in parallel, including memory and processing resource allocations optimized according to an optimization criteria. The outputted computational resource allocations are allocated to execute the activity steps in the execution paths in parallel.
Described embodiments provide improvements to computer technology to select a group of execution paths of activity steps in program code of different multiple possible groups of execution paths in which the activity steps may be arranged and processor/memory allocations of resources for the selected group of execution paths. Described embodiments utilize a resource allocation machine learning module that receives as input the activity steps and a system load and processes that information to select a group of execution paths and determine the processor/memory allocation of resources to process the selected group according to an optimization criteria. The optimization criteria may seek to minimize execution time or minimize the amount of computational resources to allocate to process the execution paths within required available times to execute the activity steps.
Further described embodiments provide improvements to computer technology to train the resource allocation machine learning module to adjust the processor/memory resource allocations based on an extent to which the realized time to process the execution paths of activity steps with the determined processor/memory resource allocations is within an acceptable margin of error of an estimated time to process the activity steps.
A resource allocation machine learning module (“MLM”) 122, which may be in the main memory 104 or implemented in separate hardware or memory device, receives as input the activity steps 114, dependency graph 116, system load 118, and volume and complexity of the activity steps 120 and uses machine learning and artificial intelligence to output, based on the inputs 114, 116, 118, and 120 and an optimization criteria 124: available times to complete activity steps 126, groups of execution paths 128, wherein the execution paths in different of the groups include different arrangements of the activity steps, including divisions of activity steps, wherein the execution paths in a group can be processed in parallel; processor/memory resource allocations 130 for the groups of execution paths 128; estimated times 132 to complete execution of the groups of execution paths 132 using the outputted resource allocation 130; a selected group of execution paths 136, which may optimize the selection of processor/memory, e.g., computational, resource allocations and estimated time to complete execution based on the optimization criteria 124; and confidence levels 134 for the groups of execution paths 128. The confidence level 134 for a particular group of execution paths indicates a likelihood that the estimated time 132 to complete execution of the particular group of execution paths and a realized time are within an acceptable margin of error, i.e., sufficiently similar.
The optimization criteria 124 may be used by the resource allocation MLM 122 to select the selected group 136. One optimization criteria may select the selected group 136 that has a lowest estimated time to complete execution of the groups 128 using less than a maximum allowed amount of available system resources indicated in the input system load 118. Another optimization criteria may determine the selected group 136 that has a lowest allocation of computational resources, e.g., processor and memory resources, of the computational resources 130 allocated of the groups that is estimated to complete execution within an available time 126 required to complete execution of the activity steps in the critical path bottleneck execution path in the selected group 136.
In an alternative embodiment, available times to complete activity steps 126, the groups of execution paths 128, and estimated times to complete execution of the groups 132 may be determined by the critical path analyzer 110 and then inputted into the resource allocation MLM 122 to determine the outputs 136, 130, 132, 134.
Upon receiving execution results 138 including a realized time to execute the selected group of execution paths 136, the resource allocation manager 108 may generate historical allocation information 300 having information on the inputs 113, 116, 118, 120, the outputs 126, 128, 136, 130, 132, 134, and the realized time to execute the selected group 136 of execution paths. The historical allocation information 300 may be used by the resource allocation manager 108 to train the resource allocation MLM 122 to increase or lower the confidence level produced for the inputs and outputs based on whether the realized and estimated times are sufficiently close or similar.
In certain embodiments, the resource allocation MLM 122 may use machine learning and deep learning algorithms, such as decision tree learning, association rule learning, neural network, inductive programming logic, support vector machines, Bayesian network, etc. For artificial neural network program implementations, the neural network may be trained using backward propagation to adjust weights and biases at nodes in a hidden layer to produce the computed output. In backward propagation used to train a neural network machine learning module, biases at nodes in the hidden layer are adjusted accordingly to produce the output 126-136 with a specified confidence level based on the input parameters 114-120. Backward propagation may comprise an algorithm for supervised learning of artificial neural networks using gradient descent. Given an artificial neural network and an error function, the method may calculate the gradient of the error function with respect to the neural network's weights and biases.
In backward propagation used to train a neural network machine learning module, such as the resource allocation MLM 122, a margin of errors is determined based on a difference of the estimated time to complete execution of execution paths in the selected group 136 and the realized time to complete execution in the execution results 138. This information on whether output selected group 136 optimizes execution of the activity steps 114 based on the optimization criteria 124 may be used to modify the confidence level 134 for the selected group of execution paths 136 based on various inputs 114-120. Biases at nodes in the hidden layer are adjusted accordingly to decrease the confidence level for the selected group 136 based on an extent the realized times to execute the execution paths in the selected group 136 using the allocated resources 130 exceed the estimated times 132, i.e., the resource allocation 130 failed to meet expectations, and increase the confidence level of the selected group 136 based on an extent the realized times to execute the execution paths in the selected group 136 using the allocated resources 130 fell below the estimated time 132, i.e., the resource allocation exceeded expectations.
In an alternative embodiment, the resource allocation engine 122 may be implemented not as a machine learning module, but implemented using a rules based system to determine the outputs from the inputs.
The arrows shown in
Generally, program modules, such as the program components 106, 108, 110, and 122 may comprise routines, programs, objects, components, logic, data structures, and so on that perform particular tasks or implement particular abstract data types. The program components and hardware devices of the system 100 of
The program components 106, 108, 110, and 122 may be accessed by the processor 102 from the memory 104 to execute. Alternatively, some or all of the program components 106, 108, 110, and 122 may be implemented in separate hardware devices, such as Application Specific Integrated Circuit (ASIC) hardware devices.
The functions described as performed by the programs 106, 108, 110, and 122 may be implemented as program code in fewer program modules than shown or implemented as program code throughout a greater number of program modules than shown.
The memory 104 may comprise non-volatile and/or volatile memory types, such as a Flash Memory (NAND dies of flash memory cells), a non-volatile dual in-line memory module (NVDIMM), DIMM, Static Random Access Memory (SRAM), ferroelectric random-access memory (FeTRAM), Random Access Memory (RAM) drive, Dynamic RAM (DRAM), storage-class memory (SCM), Phase Change Memory (PCM), resistive random access memory (RRAM), spin transfer torque memory (STM-RAM), conductive bridging RAM (CBRAM), nanowire-based non-volatile memory, magnetoresistive random-access memory (MRAM), and other electrically erasable programmable read only memory (EEPROM) type devices, hard disk drives, removable memory/storage devices, etc.
The historical allocation information 300i, comprising the inputs to the resource allocation MLM 122, outputs, and realized times to execute the execution paths in the selected group 136 with the determined resource allocations, may be used to retrain the resource allocation MLM 122 based on the difference of the estimated times 308 and realized times 312 to minimize the error in the computational resource allocations.
For instance, if the optimization criteria 124 is to minimize execution time, then the resource allocation MLM 122 selects the group 136 of execution paths from the groups 128 that completes execution in a minimum time. If the optimization criteria 124 is to minimize processor/memory resource allocation 130 to conserve computational resources, then the resource allocation MLM 122 selects the group 136 of execution paths from the groups 128 that minimizes the processor/memory resource allocation 130 and completes execution of the activity steps in the required available times 126 for the activity steps 114. Other optimization criteria 124 may also be used.
After selecting the group 136 of execution paths to execute, the resource allocation manager 108 submits (at block 410) a job to execute, in the system 100 or another system, the selected group 136 of execution paths with the outputted processor/memory resource allocations 130 for the execution paths for the selected group.
With the embodiment of
With the embodiment of operations of
Further, the resource allocation MLM 122 may dynamically arrange the activities, and split one activity step into multiple sub-activity steps if necessary, to allow for parallel or sequential processing to complete execution of the activity steps 114 within the required available times 126.
In the embodiments of
In one embodiment, there may be an estimated time 132, 308, processor/memory resource allocations 130, 310, realized time 312 and confidence level 134, 314 for each execution path in the selected group 128, 306. In an alternative embodiment, there may be one estimated time 132, 308, realized time 312 and confidence level 314 for all the execution paths in the selected group 306, where there may be different processor/memory resource allocations for the different execution paths.
With the embodiment of operations of
If (at block 606) the difference of the estimated time 308 and the realized time 312 for execution path i exceeds the acceptable margin of error, and if (at block 610) the realized time 312 is less than the estimated time 308, i.e., the performance exceeded expectations for the execution path i, then control proceeds to block 608 to train the resource allocation MLM 122 to produce the determined resource allocation 310 with a high confidence level. If (at block 610) the realized time 312 is greater than the estimated time 308, i.e., realized performance fell below expectations, then the resource allocation manager 108 or other component determines (at block 612) an adjustment percentage based on a difference of the estimated time 308 and the realized time 312 for the execution path i. The outputted processor/memory resource allocations 310 is adjusted (at block 614) higher by the adjustment percentage to produce the adjusted processor/memory resource allocations. The resource allocation MLM 122 is trained (at block 616) to output the adjusted computational resource allocation from the inputs used to produce with the outputted computational resource allocation with a predefined high confidence level. Control then proceeds to block 618 where the loop of operations at blocks 60-2 through 618 are performed for further of the non-critical and critical execution paths.
With the embodiment of
In the embodiment of
The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
The computational components of
As shown in
Computer system/server 702 typically includes a variety of computer system readable media. Such media may be any available media that is accessible by computer system/server 702, and it includes both volatile and non-volatile media, removable and non-removable media.
System memory 706 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) 710 and/or cache memory 712. Computer system/server 702 may further include other removable/non-removable, volatile/non-volatile computer system storage media. By way of example only, storage system 713 can be provided for reading from and writing to a non-removable, non-volatile magnetic media (not shown and typically called a “hard drive”). Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”), and an optical disk drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media can be provided. In such instances, each can be connected to bus 708 by one or more data media interfaces. As will be further depicted and described below, memory 706 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.
Program/utility 714, having a set (at least one) of program modules 716, may be stored in memory 706 by way of example, and not limitation, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data or some combination thereof, may include an implementation of a networking environment. The components of the computer 702 may be implemented as program modules 716 which generally carry out the functions and/or methodologies of embodiments of the invention as described herein. The systems of
Computer system/server 702 may also communicate with one or more external devices 718 such as a keyboard, a pointing device, a display 720, etc.; one or more devices that enable a user to interact with computer system/server 702; and/or any devices (e.g., network card, modem, etc.) that enable computer system/server 702 to communicate with one or more other computing devices. Such communication can occur via Input/Output (I/O) interfaces 722. Still yet, computer system/server 702 can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and/or a public network (e.g., the Internet) via network adapter 724. As depicted, network adapter 724 communicates with the other components of computer system/server 702 via bus 708. It should be understood that although not shown, other hardware and/or software components could be used in conjunction with computer system/server 702. Examples, include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.
The letter designators, such as i, is used to designate a number of instances of an element may indicate a variable number of instances of that element when used with the same or different elements.
The terms “an embodiment”, “embodiment”, “embodiments”, “the embodiment”, “the embodiments”, “one or more embodiments”, “some embodiments”, and “one embodiment” mean “one or more (but not all) embodiments of the present invention(s)” unless expressly specified otherwise.
The terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless expressly specified otherwise.
The enumerated listing of items does not imply that any or all of the items are mutually exclusive, unless expressly specified otherwise.
The terms “a”, “an” and “the” mean “one or more”, unless expressly specified otherwise.
Devices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.
A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary a variety of optional components are described to illustrate the wide variety of possible embodiments of the present invention.
When a single device or article is described herein, it will be readily apparent that more than one device/article (whether or not they cooperate) may be used in place of a single device/article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device/article may be used in place of the more than one device or article or a different number of devices/articles may be used instead of the shown number of devices or programs. The functionality and/or the features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality/features. Thus, other embodiments of the present invention need not include the device itself.
The foregoing description of various embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto. The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims herein after appended.
Number | Name | Date | Kind |
---|---|---|---|
6934951 | Wilkinson, III | Aug 2005 | B2 |
9705747 | Xue | Jul 2017 | B1 |
10855808 | Mohanty | Dec 2020 | B1 |
11200514 | Chen | Dec 2021 | B1 |
11635993 | Vadapandeshwara | Apr 2023 | B2 |
20090158289 | Toub | Jun 2009 | A1 |
20120159507 | Kwon | Jun 2012 | A1 |
20140055496 | Cunningham | Feb 2014 | A1 |
20150236896 | Brown | Aug 2015 | A1 |
20150277965 | Bradshaw | Oct 2015 | A1 |
20160062800 | Stanfill | Mar 2016 | A1 |
20180081720 | Zlatanchev | Mar 2018 | A1 |
20180089002 | Xia | Mar 2018 | A1 |
20190108055 | Anand | Apr 2019 | A1 |
20190196939 | Lengauer | Jun 2019 | A1 |
20200026633 | Gottin | Jan 2020 | A1 |
20200042216 | Zhang | Feb 2020 | A1 |
20200057675 | Dias | Feb 2020 | A1 |
20200133859 | Gottin | Apr 2020 | A1 |
20200234115 | Pourghassemi | Jul 2020 | A1 |
20200272444 | Nilsen | Aug 2020 | A1 |
20200334083 | Liu | Oct 2020 | A1 |
20210042577 | Martin | Feb 2021 | A1 |
20210126986 | Rolf | Apr 2021 | A1 |
20210349814 | Joshi | Nov 2021 | A1 |
20220121194 | Pritchard | Apr 2022 | A1 |
20220138616 | Patel | May 2022 | A1 |
20220198320 | Walczyk, III | Jun 2022 | A1 |
20220350708 | Vishwakarma | Nov 2022 | A1 |
20230071278 | Karri | Mar 2023 | A1 |
20230105476 | Anil | Apr 2023 | A1 |
Number | Date | Country |
---|---|---|
2016202814 | Mar 2017 | AU |
107995039 | May 2018 | CN |
109144716 | Jan 2019 | CN |
109840248 | Jun 2019 | CN |
112306653 | Feb 2021 | CN |
113157421 | Jul 2021 | CN |
Entry |
---|
PCT International Search Report and Written Opinion, dated Nov. 28, 2022, 10pp., for International Application No. PCT/CN2022/115443. |
Emerald Works Limited, “Critical Path Analysis and PERT Charts”, [online], [Retrieved on Aug. 1, 2021], Retrieved from the Internet at <URL: https://www.mindtools.com/pages/article/critical-path-analysis.htm>, 5 pp. |
Fields, B.A., “Using Criticality to Attack Performance Bottlenecks”, Technical Report No. UCB/EECS-2006-176, [online], Dec. 14, 2006, Retrieved from the Internet at URL <http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-176.html>, 224 pp. |
Widmer, S., et al., “Fast Dynamic Memory Allocator for Massively Parallel Architectures”, Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units, Mar. 16, 2013, 7 pp. |
Witt, C., et a;., “Predictive Performance Modeling for Distributed Computing Using Black-Box Monitoring and Machine Learning”, arXiv:1805.11877, May 30, 2018, 19 pp. |
Number | Date | Country | |
---|---|---|---|
20230071278 A1 | Mar 2023 | US |