Patent Application
20210080327
This invention relates to a vacuum packaged infrared sensor array and, more particularly, to a vacuum packaged infrared sensor array wherein the infrared sensor array has a thermopile made of recrystallized amorphous silicon and the vacuum is enhanced by low temperature oxidization of porous silicon.
Significant progress has been made on infrared sensor array technologies and production capabilities. The detector pixel dimensions have continually decreased with an increase in pixel performance making large format, high-density array products affordable. In turn, this has resulted in the proliferation of IR detectors in commercial and military markets. Presently, infrared detectors are widely used in firefighting, surveillance, industrial process monitoring, machine vision, and medical applications. Within the military arena, infrared detectors are ubiquitous in Army soldier systems such as weapon sights, driver's viewers, and helmet-mounted sights. Infrared detectors are also employed in airborne and ground surveillance sensors including unmanned aerial vehicles and robot vehicles.
Infrared thermopile sensors and arrays are sufficiently known in various forms and designs. Thermopile sensors produced using silicon micromachining on a substrate normally consist of a thin membrane, on which thermocouples produced using thin-film technology are situated. Situated below the membrane there is a hollow in the substrate, said hollow being surrounded by a silicon edge. Thermocouples in the form of elongated thermopile elements have hot contacts at one end and cold contacts at the other end, which are connected to one another by conductive tracks, wherein the hot contacts are situated on or in the central part of the membrane and the cold contacts are situated on the silicon edge, which serves as a heat sink.
Various structures for infrared thermopile sensor arrays were proposed and developed. U.S. Pat. No. 10,128,302 reveals an infrared detector array device comprising a dielectric membrane, supported by a substrate, the membrane having an array of IR detectors, where the array size is at least 3 by 3 or larger, and there are tracks embedded within the membrane layers to separate each element of the array, the tracks also acting as heat sinks and/or cold junction regions.
Uncooled thermal infrared sensors require to be operated in an ambient gas pressure of about 50 mTorr or less to avoid sensitivity being reduced by thermal conduction through the gas.
U.S. Pat. No. 5,701,008 reveals an integrated infrared microlens and gas molecule getter grating in a vacuum package, wherein the array has a plurality of microlenses aligned with respective IR detector array pixels to focus incoming IR radiation onto the pixels to improve the efficiency of IR detection, and a gas molecule getter grating inside a vacuum-sealed Dewar assembly that houses the detector array increases the surface area of the getter to improve the efficiency of removing residual gas molecules from the Dewar assembly.
U.S. Pat. App. 20180335347 reveals a thermal infrared sensor array in substrate-level package, wherein the array in a substrate-level package includes mechanics, comprising a heat-isolating cavity in a silicon substrate surrounded by a silicon edge, and a thin membrane connected to the silicone edge by of thin beams. The cavity extends through the silicon substrate to the membrane, and there are slots between the membrane, the beams and the silicon edge. A plurality of infrared-sensitive individual pixels are arranged in lines or arrays and are designed in a CMOS stack in a dielectric layer, forming the membrane, and are arranged between at least one cover substrate which is designed in the form of a cap and has a cavity and a base substrate. The cover substrate, the silicon substrate and the base substrate are connected to one another in a vacuum-tight manner and enclosing a gas vacuum.
In spite of successful commercialization of infrared thermopile sensor arrays, the infrared community is still searching for a platform for thermal imagers that combine affordability, convenience of operation, and excellent performance.
In response to these needs, the present invention provides a vacuum packaged infrared sensor array wherein the infrared sensor array has a thermopile made of recrystallized amorphous silicon and the vacuum in the package is enhanced by low temperature oxidization of porous silicon incorporated in the vacuum packaged infrared sensor array.
In view of the forgoing background of the invention, the infrared imaging sensor has to be maintained at a certain degree of vacuum so as to ensure the normal operation. The conventional packaging method of the infrared imaging sensor not only has complicated process, but also the allocation amount of its getter is restricted by the size, of the vacuuming pipe, thus resulting in a bottleneck for maintaining the degree of vacuum state in the infrared imaging sensor.
An object of the present invention is to provide a vacuum packaged infrared sensor array with higher performances wherein the individual pixel of the infrared sensor array has a thermopile made of recrystallized amorphous silicon resulting in low resistance, low thermal noise, high integration and high sensitivity and the vacuum in the packaged infrared sensor array is enhanced by low temperature oxidization of the porous silicon layer formed in a lid silicon substrate which is bonded with the infrared sensor array silicon substrate.
Another object of the present invention is to provide a vacuum packaged infrared sensor array wherein the individual pixel of the infrared sensor array comprises a flat bottom and deeper cavity created in a silicon substrate by using a micromachining technology based on selectively forming and etching of porous silicon in the silicon substrate.
Still another object of the present invention is to provide a vacuum packaged infrared sensor array which can be fabricated using any crystal orientation silicon substrates including (111) crystal orientation silicon substrates and get rid of many restrictions to KOH based micromachining technology.
Still another object of the present invention is to provide a vacuum packaged infrared sensor array wherein the infrared sensor array has an infrared absorber created by a stack layer consisting of several CMOS comparable thin layer materials including titanium or a tungsten layer.
Still another object of the present invention is to provide a vacuum packaged infrared sensor array wherein the thermopile is combined with a recrystallized amorphous silicon field effect transistor in each pixel of the infrared sensor array so as to switch on/off the operated pixel and isolate the other pixels.
The above and other features and advantages of the present invention will become more apparent by describing, example embodiments in detail with reference to the attached drawings. The accompanying drawings are intended to depict example embodiments and should not be interpreted to limit the intended scope of the claims. The accompanying drawings are not to be considered as drawn to scale unless explicitly noted.
The present invention is further described below with reference to the accompanying drawings.
Reference to the
The matrix size of the infrared sensor array is large enough, such as 8×8, the array with a microcontroller can detect the presence of warm bodies in a room—as long as those bodies are moving up, down, left, right and diagonally. It can even detect multiple people or objects as they move in different directions. They can also sense an object's proximity to the detector and handle simple gesture control tasks.
According to the present invention, an across sectional view of the said vacuum packaged infrared sensor array can be shown in the
The low temperature oxidized porous silicon layer is formed by anodization of the lid silicon substrate in a HF solution. Before bonding, the lid silicon substrate with the porous silicon layer is thermal treated by heating up to 350° C. in a vacuum system for 30 to 60 min in order to desorb and remove Si-H species on the pore walls of the porous silicon layer.
After loading into a vacuum bonding system, the lid silicon substrate with the porous silicon layer is to pump from atmosphere to vacuum and then fill oxygen from vacuum to atmosphere for 2 to 3 times so that the residual gas in the pores of the porous silicon layer is no nitrogen and hydrogen and only oxygen.
In the vacuum bonding system, the infrared sensor array silicon substrate and the lid silicon substrate are bonded together by aligning, compacting, and then heating the eutectic ring up to 350 to 450° C. for 30 to 60 min to form a continuous thin oxide layer on the pore walls of the porous silicon layer which led to consume the residual oxygen in the sealed chamber and to increases the vacuum in the sealed chamber between the infrared sensor array silicon substrate and the lid silicon substrate.
Low temperature oxidization of porous silicon is benefited from its large surface area. The surface area of porous silicon is million times greater that of a planar surface crystal silicon which significantly lowers its oxidization temperature. The driving force for lowering the oxidization temperature is a reduction in surface energy of porous silicon. It has been reported that the surface energy is 0.0001 J/cm2 for porous silicon and 0.2 J/cm2 for planar crystal silicon. So large surface area makes porous silicon chemically unstable, and its oxidization is common natural process.
According to the present invention, the said individual infrared sensor pixel can be shown in the
According to the present invention, the said silicon substrate can be any crystal orientations including a (111) crystal orientation which is not allowed to use for KOH micromachining. The KOH etch rate is strongly affected by the crystallographic orientation of the silicon (anisotropic). The (110) plane is the fastest etching primary surface. The (111) plane is an extremely slow etching plane that is tightly packed, has a single dangling-bond per atom, and is overall atomically flat. So it is impossible to create a flat bottom cavity in a silicon substrate with a (111) crystal.
The silicon micromachining technology used in the present invention is based on the selective forming and etching of a porous silicon layer in a silicon substrate. A porous silicon layer results from an electrochemical etching of a crystalline silicon substrate in a hydrofluoric acid based electrolyte. The growth rate of porous silicon depends on the type and the doping level, but not the crystallographic orientation of the silicon substrate. The electrolyte composition also influents the growth rate of porous silicon. Pores are grown mainly in the current direction. Their sizes vary from a few nanometers to several micrometers. The thickness of the porous silicon layer mainly depends on the applied current density and duration. So the depth of the cavity can be made in the range of 20 to 50 micron. The flat bottom cavity can be simply modeled as a one-dimensional heat conduction transfer from the said membrane to the said flat bottom.
The infrared sensor array is preferred to be fabricated using a conventional CMOS process. This process is the normal technique used to manufacture typical integrated circuits. Several key benefits to leveraging conventional CMOS processing for MEMS are that fabrication is fast, reliable, repeatable, and economical.
Many thin layers are available in the CMOS process. The type of the thin layers includes silicon dioxide (SiO2), silicon nitride (Si3N4), polysilicon, amorphous silicon layer, recrystallized amorphous silicon, metals such as titanium, tungsten and aluminum. All these thin layers can be chosen according to the equipments of the present invention.
The said thermopile is fabricated from recrystallized amorphous silicon that ensures sufficiently high thermo-power while their conductivity and thermo-power can be adjusted by the proper doping. Individual thermocouple is constructed by a recrystallized p-type such as boron doped polysilicon leg and a recrystallized n-type such as phosphorus doped polysilicon leg. Due to recrystallization of amorphous silicon resulting in larger grain size, the thermopile has a low resistance so as to have a low thermal noise or Johnson-Nyquist noise. The thermopile can be integrated more than 30 thermocouples which still has quite low thermal noise.
The said membrane is built by a stack layer consisting of at least a silicon dioxide layer and a silicon nitride layer or both two layers. Silicon dioxide material and silicon nitride material have high electrical resistivity and low thermal conduction, which make them materials of choice for thermal membrane sensors where minimal losses of the said infrared sensor arrays are required.
The said infrared absorber is built by a stack layer consisting of a top silicon nitride layer, a titanium layer, a silicon dioxide layer, a recrystallized amorphous silicon layer, a silicon dioxide layer and a bottom polysilicon layer. The absorptance of the stack layer can be calculated based on the Fresnel equations. Like other metals, the said titanium layer has a complex index of refraction. This is because metals have free charge carriers that can oscillate in response to an incoming electromagnetic field. When the refractive index is complex, the imaginary part is sometimes called extinction coefficient. The extinction coefficient is larger, the more quickly light gets absorbed as it tries to travel through the material.
Many experiments showed that recrystallized amorphous silicon has electronic properties that closely approximate those of single crystal material. These results led the present invention to fabricate field effect transistors (FET's) and integrated circuits directly in recrystallized amorphous silicon. The recrystallized amorphous silicon can be realized by low temperature furnace annealing. As an alternative, the recrystallized amorphous silicon can be realized by laser annealing.
According to the present invention a method for fabricating a vacuum packaged infrared sensor array comprising two stages: preparing an infrared sensor array silicon substrate and preparing a lid silicon substrate, wherein the said preparing of an infrared sensor array silicon substrate comprises the following fabrication steps: providing a p-type silicon substrate; creating a 200 to 300 nm thick silicon nitride HF resistive mask pattern by low temperature vapor chemical deposition (LPCVD) and conducting a photolithography process; conducting anodization in a HF solution to grow a 20 to 50 μm thick porous silicon layer in said silicon substrate; conducting low temperature oxidization of the said porous silicon layer at 350° C. in oxygen for 30 min; removing the residue silicon nitride layer by etching; depositing both a 100 nm thick polysilicon layer and a 500 nm thick silicon nitride layer over the surface of the said silicon substrate by plasma enhanced chemical vapor deposition (PECVD); depositing a 100 to 200 nm thick amorphous silicon layer over the surface of the said silicon substrate by LPCVD at 475° C.; pattering the said amorphous silicon layer to create an amorphous silicon active area for a thermopile, an amorphous silicon active area for a field-effect transistor (FET) and an amorphous silicon active area for several buried amorphous silicon interconnection bridges by a photolithography process; conducting recrystallization of the said amorphous silicon active areas to form recrystallized amorphous silicon active areas with larger grain size; conducting thermal oxidization of the said recrystallized amorphous silicon areas to grow a 70-100 nm thick silicon dioxide layer on the said recrystallized amorphous silicon active areas; depositing a 300 nm polysilicon layer by LPCVD over the surface of the said silicon substrate at 650° C.; pattering the said polysilicon layer to create a polysilicon element for an infrared absorber and a polysilicon gate for the FET by photolithography process; conducting n+ such as phosphorus ion implantation to form n+ recrystallized amorphous silicon legs for the thermopile, a n+ recrystallized amorphous silicon drain, a n+ recrystallized amorphous silicon source and a n+ polysilicon gate for the FET; conducting p+ such as boron ion implantation to form p+ recrystallized amorphous silicon legs for the thermopile and p+ recrystallized amorphous silicon interconnection bridges; annealed at 950° C. in nitrogen for 30 min; depositing a 1100 nm silicon dioxide layer by PECVD; conducting a photolithography process; conducting a plasma passivation treatment on the n+ recrystallized amorphous silicon drain and source of the said FET; depositing a 200 nm thick titanium layer and conducting a photolithography process; depositing a 1000 nm thick aluminum layer by sputtering and conducting a photolithography process; depositing a 850 nm thick high density plasma (HDP) silicon nitride layer over the surface of the said silicon substrate; producing a seal ring consisting of Ti/Pt/Au on the round edge of the said infrared sensor array; creating an etching window in the said HDP silicon nitride layer down to the said porous silicon layer; etching the said porous silicon layer in a diluted KOH solution to create a cavity replacing the said porous silicon layer and release the stack layer over the said porous silicon layer which results in a membrane over the said cavity and finally finish the fabrication process of the said infrared sensor array silicon substrate and the said preparing of a lid silicon substrate comprises the following fabrication steps: providing a lid silicon substrate; growing a 20 to 50 μm thick central porous silicon layer and a 20 to 50 μm thick edge porous silicon layer in an area sized equal to the said infrared sensor array; creating a seal ring consisting of Ti/Pt/Au/Ge/Au on the round edge of the said central porous silicon layer; removing Si-H species on the pore walls of the said porous silicon layers by heating up to 350° C. in vacuum; loading the said infrared sensor array silicon substrate and the said lid substrate into a vacuum bonding system; before bonding the said vacuum system is pumped from an atmosphere to vacuum and then filled with oxygen back to the atmosphere for 2 to 3 times; conducting eutectic bonding of the said lid silicon substrate and the said sensor silicon substrate in vacuum at 350° C. to 450° C. so as to oxidize the said porous silicon layers and consume the residue oxygen in the chamber sandwiched between the said lid silicon substrate and the said infrared sensor array silicon substrate; cutting the said lid silicon substrate down to the said edge porous silicon layer; etching the said edge porous silicon layer and etching the said HDP silicon nitride layer to real the said aluminum bon pads so as to finish the fabrication process for the said vacuum packaged only silicon substrate infrared sensor array.
After a first several fabrication steps, the top view of a pixel of an infrared sensor array is shown in the
The said silicon substrate can be any crystal orientation silicon substrate including a (111) crystal orientation silicon substrate which is not allowed to use for KOH micromachining.
The said porous silicon layer is used as a sacrificial layer for micromachining so as to create a deep cavity into the silicon substrate with a very smooth bottom surface and four curved sidewalls.
The said etching of the P-type silicon substrate is conducted in a HF solution consisting of 49 wt. % HF in water and ethanol, having a HF concentration ranging from 12 to 35 vol % and at an anodic current density ranging from 20 mA to 80 mA/cm2.
The said porous silicon layer is designed to have a depth ranging from 20 to 50 μm and a top surface size ranging from 100×100 to 500×500 (μm)2.
After a second several fabrication steps, the top view of the said pixel of the said infrared sensor array can be shown in the
The said recrystallization of the said amorphous silicon layer is realized by rapid thermal annealing at 750° C. for 120 s or at 550° C. for 60 s and then at 750° C. for 60 s.
The said recrystallization of the said amorphous silicon layer is realized by laser annealing such as KrF or XeCl excimer laser annealing, which supply intense pulsed light with durations of approximately 30 to 50 ns.
The said recrystallization of the amorphous silicon layer is realized by low thermal furnace annealing such as in vacuum at 600° C. for 10 to 14 hours.
The said ion implantation for the said FET is self-alignment so that the n+ ion implanted is applied only for the said recrystallized silicon drain area and the said recrystallized silicon source area but not for the said recrystallized silicon gate area.
The said p+ and n+ recrystallized amorphous silicon layers have a carrier concentration ranging from 2×1015 to 5×1015/cm2, respectively.
The said plasma passivation on the said n+ recrystallized amorphous silicon drain and source of the said FET is realized by H2 plasma treatment in a parallel-plate plasma reactor at 300° C. with a power density of 0.7 W/cm2.
The said plasma passivation on the said n+ recrystallized amorphous silicon drain and source of the said FET is realized by NH3 plasma treatment in a parallel-plate plasma reactor at 300° C. with a power density of 0.7 W/cm2.
The said recrystallization of the amorphous silicon layers has low electrical resistivity because the annealing can reduce the resistivity by a factor of at least 2-3 compared to the original electrical resistivity.
After a third several fabrication steps, the top view of the said pixel of the said infrared sensor array can be shown in the
In the
After a fourth several fabrication steps, the top view of the said pixel of the said infrared sensor array can be shown in the
In the
After a fifth several fabrication steps, the top view of the said pixel of the said infrared sensor array can be shown in the
In the
After a sixth several fabrication steps, the top view of the said pixel of the said infrared sensor array can be shown in the
As can be seen from the
Before bonding, the said porous silicon layers need to be treated 2 to 3 cycles by vacuuming and filling of the said vacuum bonding system so that the residual gas in the pores of the said porous silicon layers is only oxygen and absolutely no hydrogen and nitrogen. In the first time, the air filled in the said bonding system is pumped out and the next two to three times, the oxygen filled in the said bonding system is pumped out.
Bonding of the said lid silicon substrate and the said infrared sensor array silicon substrate is conducted in the said vacuum bonding system at 350 to 450° C. and for 30 to 60 min. During the bonding process, the said porous silicon layers are oxidized to form a continuous thin oxide layer on the pore walls of the said porous silicon layers which led to consume the residual oxygen completely in the said sealed chamber sandwiched by the two said silicon substrates so as to increases the vacuum in the said sealed chamber.
Only a preferred embodiment of the invention has been shown and described. It should be understood that the invention is not limited to the embodiment disclosed, but is intended to embrace any alternative, modification, rearrangements, or substitutes of parts or elements as fall within the spirit and scope of the invention.
