Patent Application
20140173346
The field generally relates to techniques for validating operation of system-on-chips for storage devices and, in particular, techniques for utilizing a programmable state machine controller to generate test signals that drive a read channel integrated circuit to validate operation of components of the system-on-chip.
Storage devices such as hard disk drives are used to provide non-volatile data storage in a wide variety of different types of data processing systems. A typical hard disk drive comprises a spindle that holds one or more flat circular storage disks, also referred to as platters. Each storage disk comprises a substrate made from a non-magnetic material, such as aluminum or glass, which is coated with one or more thin layers of magnetic material. In operation, data is read from and written to tracks of the storage disk via a read/write head that is moved precisely across the disk surface by a positioning arm as the disk spins at high speed. Within the storage device, various integrated circuit electronics for controlling the writing and reading of data to and from a storage disk are highly integrated into a single system-on-chip. These integrated circuit electronics include, for example, various micro-controllers such as disk controllers and memory controllers, and other integrated circuits such as read channel integrated circuits, etc., which are configured to operate at ever-increasing speeds for storing and accessing data. To facilitate faster operating speeds, a storage device typically employs a high-speed memory device, such as a double-data rate (DDR) synchronous dynamic random access memory (SDRAM), which serves as a data buffer to maintain consistent data throughput as data passes to and from the storage disks. Since state of the art storage devices implement a relatively large number of complex data processing functions at increasingly higher data rates, it is desirable to implement methods for validating operation of the system-on-chip.
In one embodiment of the invention, a system-on-chip for controlling a storage system includes a storage controller, a read channel integrated circuit, a programmable state machine controller, a switching circuit, a buffer memory, and an interface to externally access the buffer memory. The switching circuit operates to switchably connect the storage controller or the programmable state machine controller to the read channel integrated circuit. The buffer memory is connected to the programmable state machine controller. The interface is used to store test control data in the buffer memory. In a test mode to validate operation of the system-on-chip, the switching circuit is controlled to switchably connect the programmable state machine controller to the read channel integrated circuit. In addition, the programmable state machine controller is enabled to access the test control data from the buffer memory, and to process the test control data to generate test signals that are applied to operate the read channel integrated circuit and validate operation of the system-on-chip based on the operation of the read channel integrated circuit.
Other embodiments of the invention will become apparent.
The storage device 100 further comprises other control circuitry mounted on or more printed circuit boards that are disposed in a lower housing 170 of the storage device 100. The control circuitry comprises various drive electronics, signal processing electronics, and associated processing and memory circuitry, to control the writing and reading of data to and from the storage disk, as well as additional or alternative elements that are utilized to drive and control the spindle and actuator motors. A connector 180 is used to connect the storage device 100 to a host computer or other related processing device.
A read/write head as that term is broadly used herein may be implemented in the form of a combination of separate read and write heads. More particularly, the term “read/write” as used herein is intended to be construed broadly as read and/or write, such that a read/write head may comprise a read head only, a write head only, a single head used for both reading and writing, or a combination of separate read and write heads. Such heads may comprise, for example, write heads with wrap-around or side-shielded main poles, or any other types of heads suitable for recording and/or reading data on a storage disk.
In addition, the storage device 100 as illustrated in
The outer zones of the storage disk 110 provide a higher data transfer rate than the inner zones. This is in part due to the fact that the storage disk in the present embodiment, once accelerated to rotate at operational speed, spins at a constant angular or radial speed regardless of the positioning of the read/write head, but the tracks of the inner zones have smaller circumference than those of the outer zones. Thus, when the read/write head 130 is positioned over one of the tracks of an outer zone, it covers a greater linear distance along the disk surface for a given 360° turn of the storage disk than when it is positioned over one of the tracks of an inner zone. Such an arrangement is referred to as having constant angular velocity (CAV), since each 360° turn of the storage disk takes the same amount of time, although it should be understood that CAV operation is not a requirement of embodiments of the invention.
Data bit density is generally constant across the entire storage surface of the storage disk 110, which results in higher data transfer rates at the outer zones. Accordingly, the outermost annular zone 230-0 of the storage disk has a higher average data transfer rate than the innermost annular zone 230-M of the storage disk. The average data transfer rates may differ between the innermost and outermost annular zones in a given embodiment of the invention by more than a factor of two. For example, in one embodiment of the invention, the outermost annular zone may have a data transfer rate of approximately 2.3 Gigabits per second (Gb/s), while the innermost annular zone has a data transfer rate of approximately 1.0 Gb/s. In such an implementation, the hard disk drive may more particularly have a total storage capacity of 500 GB and a spindle speed of 7200 RPM, with the data transfer rates ranging, as noted above, from about 2.3 Gb/s for the outenuost zone to about 1.0 Gb/s for the innermost zone.
The storage disk 110 may be assumed to include a timing pattern formed on its storage surface. Such a timing pattern may comprise one or more sets of servo address marks (SAMs) or other types of servo marks formed in particular sectors in a conventional manner. SAMs may therefore be viewed as an example of what are more specifically referred to herein as servo marks. The particular data transfer rates and other features described above are presented for purposes of illustration only, and should not be construed as limiting in any way. A wide variety of other data transfer rates and storage disk configurations may be used in other embodiments.
The host interface connector 316 represents a physical connector (e.g., connector 180 as shown in
The hard disk controller 302 controls the overall operations of writing and reading data to and from the storage disk 110. In one embodiment of the invention, the hard disk controller 302 is an ARM (Advanced Reduced instruction set computing Machine). In other embodiments, the hard disk controller 302 may comprise other known architectures suitable for controlling hard disk operations. The read channel integrated circuit 304 encodes and decodes data that is written to and read from the storage disk 110 using the read/write head 130. The preamplifier 326 is connected between the read channel integrated circuit 304 and the read/write head 130. The preamplifier 326 amplifies an analog signal output from the read/write head 130 for input to the read channel integrated circuit 304 and provides a voltage bias for a magnetic sensor of the read/write head 130. The APBL interface 324 is used to access internal registers of the read channel integrated circuit 304.
The motor controller 308 is connected to the head/disk assembly 200 via the servo interface 322. The motor controller 308 sends control signals to the spindle motor 202 and actuator motor 150 through the servo interface 322 during read and write operations to spin the storage disk 110 and move the read/write head 130 into a target position. In particular, for a typical read operation, signals for performing a read operation are received through the host interface connector 316 and sent to the hard disk controller 302 through the host interface controller 306. The hard disk controller 302 processes the read signals for performing the read operation and then sends control signals to the motor controller 308 for controlling the actuator motor 150 and spindle motor 202 for the read operation. Additionally, the hard disk controller 302 sends the processed read signals to the read channel integrated circuit 304, which are then sent to the actuator motor 150 through the preamplifier 326 to perform the read operation. The actuator motor 150 positions the read/write head 130 over a target data track on storage disk 110 in response to control signals received by the motor controller 308 and the read channel integrated circuit 304. The motor controller 308 also generates control signals to drive the spindle motor 202 to spin the storage disk 110 under the direction of the hard disk controller 302. The spindle motor 202 spins the storage disk 110 at a determined spin rate.
When the read/write head 130 is positioned adjacent the target data track, magnetic signals representing data on the storage disk 110 are sensed by read/write head 130 as the storage disk 110 is rotated by the spindle motor 202. The sensed magnetic signals are provided as continuous, minute analog signals representative of the magnetic data on the storage disk 110. The analog signals are transferred from the read/write head 130 to the read channel integrated circuit 304 via the preamplifier 326. The preamplifier 326 amplifies the analog signals accessed from storage disk 110, and the read channel integrated circuit 304 decodes and digitizes the received analog signals to recreate the information originally written to the storage disk 110. The data read from the storage disk 110 is then output to a host system or device through the host interface controller 306 and host interface connector 316 under control of the hard disk controller 302.
A write operation is substantially the opposite of a read operation. For example, in one embodiment, write signals for performing write operations are received through the host interface connector 316, wherein the write signals represent commands to perform a write operation and/or data that is to be written to the storage disk 110. The write signals are sent to the hard disk controller 302 through host interface controller 306. The hard disk controller 302 processes the write signals for performing the write operation and then sends control signals to the motor controller 308 for controlling the actuator motor 150 and spindle motor 202 for the write operation. Additionally, the hard disk controller 302 sends the processed write signals (and formatted data) to the read channel integrated circuit 304, wherein the formatted data to be written is encoded. The write signals (control and data) are then sent to the actuator motor 150 through the preamplifier 326 to perform a write operation by writing data to the storage disk 110 via the read/write head 130.
In the embodiment of
In one embodiment of the invention, the external random access memory 328 serves as a buffer memory for data transfers between a host system/device and the storage device 100. For example, the read and or write signals (as discussed above) that are received by the hard disk controller 302 from the host interface controller 306 can be temporarily stored in the external random access memory 328 before being processed by the hard disk controller 302 and the read channel integrated circuit 304, for example. Moreover, data that is read out from the storage disk 110 may be temporarily stored in the external random access memory 328 before being packaged and output to a host system/device by operation of the hard disk controller 302 and the host interface controller 306. This buffering optimizes the throughput of the storage device 100 by matching disparate processing and data transmission speeds as data passes to and from the storage disk 110.
The first multiplexer M1 is a switching circuit that has inputs connected to the minimal pin interface 318 and the hard disk controller 302, and an output connected to the memory controller 310. The first multiplexer M1 is used during a test mode to switchably connect the minimal pin interface 318 to the memory controller 310 and allow input of external test control signals and initialization parameters to debug initialization issues or otherwise validate operation of the external random access memory 328 using known techniques.
Moreover, the second multiplexer M2 is a switching circuit having inputs connected to the disk controller 302 and the programmable state machine controller 312, and an output connected to the read channel integrated circuit 304. The buffer memory 314 is connected to the programmable state machine controller 312. In one embodiment of the invention, the buffer memory 314 stores test control data that is input to the buffer memory 314 using the JTAG interface 320. The test control data is processed by the programmable state machine controller 312 during a test mode to validate operation of components of the system-on-chip 300. For example, in one embodiment of the invention, the second multiplexer M2 switchably connects the programmable state machine controller 312 to the read channel integrated circuit 304 to execute a test mode of the system-on-chip 300. In one embodiment of the invention, a test mode is performed by enabling the programmable state machine controller 312 to access the test control data from the buffer memory 314 and processes the test control data to generate test control signals that are applied to operate the read channel integrated circuit 304 and validate operation of the system-on-chip 300 based on the operation of the read channel integrated circuit 304. Details regarding test mode procedures that can be implemented using the programmable state machine controller 312 according to alternative embodiments of the invention will be discussed below with reference to
It is to be understood that the external random access memory 328, system-on-chip 300 and preamplifier 326 shown in
Furthermore, although the embodiment of
In an embodiment where the external random access memory 328 is implemented as a DDR SDRAM, for example, the higher data rate speeds of the external random access memory 328 can present issues regarding the timing of data transfers. The memory controller 310 in
In the embodiment shown in
For example, in one embodiment of the invention, a test mode is implemented in which test signals for driving the read channel integrated circuit 304 are generated by the programmable state machine controller 312 based on test control data and commands that are stored in the internal buffer memory 314. The programmable state machine controller 312 processes the test control data and commands stored in the internal buffer memory 314 to generate test signals (I/O signals) that drive the read channel integrated circuit 304 to emulate write and read cycles similar to those generated during a functional mode of operation of the read channel integrated circuit 304. In this test mode, the programmable state machine controller 312 drives the read channel integrated circuit 304 with test signal waveforms to generate voltage transients or supply noise, which are similar to voltage transients and noise that would be generated during a functional mode of operation of the read channel integrated circuit 304. The voltage transients and/or supply noise generated in this manner are used to determine the effects of functional mode operation of the read channel integrated circuit 304 on the memory controller 310 and/or the external random access memory 328 when reading/writing data to the storage disk 110 by the system-on-chip 300.
In one embodiment of the invention, the internal buffer memory 314 is used by the system-on-chip 300 as a buffer memory for normal functional mode operations. In one embodiment of the invention, the internal memory buffer 314 is used as a LLI (Long Latency Interface) buffer memory for normal functional mode operations of the system-on-chip 300. The internal buffer memory 314 is reused for test modes to store control signals and commands that are used by programmable state machine controller 312 for driving the read channel integrated circuit 304. The programmable state machine controller 312 is programmed through the JTAG interface 320 to generate different test signal waveforms to emulate different operating behaviors of the read channel integrated circuit 304.
As further shown in
The data block portion 502 specifies an address location of a next data block in the linked sequence of data blocks. In one embodiment of the invention, the data block portion 502 is a 14-bit [13:0] data block that specifies a next address location in the buffer memory 314 at which the programmable state machine controller 312 will access a next data next block 500 in the linked sequence of data blocks when executing a test mode of operation. The data block portion 504 is a 14-bit data block [27:14] that specifies a delay in number of cknrz clock cycles to wait after applying test signals for the given data block to the interface of the read channel integrated circuit 304. The data block portions 506, 508, 510, and 512 specify test signals that are applied to the interface of the read channel integrated circuit 304 for a period of time specified by the number of clock cycles of delay in the data block portion 504.
For example, in one embodiment of the invention, the data block portion 506 is a 1-bit data block [28] that specifies a value of a read gate interface signal rdgate to be applied to the rdgate port of the read channel integrated circuit 304. The value of rdgate may specify a logic “1” or a logic “0” to be applied to the rdgate port of the read channel integrated circuit 304 and held at that logic value for the specified number of delay in cknrz clock cycles as specified by the data block portion 504. Furthermore, the data block portion 508 is a 1-bit data block [29] that specifies a value of a write gate interface signal wrgate to be applied to the wrgate port of the read channel integrated circuit 304. The value of wrgate may specify a logic “1” or a logic “0” to be applied to the wrgate port of the read channel integrated circuit 304 and held at that logic value for the specified number of delay in cknrz clock cycles as specified by the data block portion 504. Moreover, the data block portion 510 is a 1-bit data block [30] that specifies a value of a servo gate interface signal to be applied to the servo port of the read channel integrated circuit 304. The value of servo may specify a logic “1” or a logic “0” to be applied to the servo port of the read channel integrated circuit 304 and held at that logic value for the specified number of delay in cknrz clock cycles as specified by the data block portion 504. In addition, the data block portion 512 is a 1-bit data block [31] that specifies a value of a rst_pinb interface signal to be applied to the rst_pinb port of the read channel integrated circuit 304. The value of rst_pinb may specify a logic “1” or a logic “0” to be applied to the rst_pinb port of the read channel integrated circuit 304 and held at that logic value for the specified number of delay in cknrz clock cycles as specified by the data block portion 504.
As further shown in
After accessing the data block, the programmable state machine controller 312 will compare a current channel ready signal, chn_rdy, output from the read channel integrated circuit 304 with a value of the chn_rdy data block portion 514 specified in the currently accessed data block and wait to apply test signals to the read channel integrated circuit 304 until the channel ready signal, chn_rdy, output from the read channel integrated circuit 304 matches the value of the chn_rdy of the current data block (step 604). When the values match (affirmative result in step 604), the programmable state machine controller 312 will generate test signals based on the test control data specified in the currently accessed data block and drive the interface of the read channel integrated circuit 304 with the generated test signals (step 606). For example, the programmable state machine controller 312 will drive the read channel integrated circuit 304 with test signals using the rdgate, wrgate, servo and rst_pinb values specified in respective data block portions 506, 508, 510 and 512 of the currently accessed data block. These test signals for the current data block will be applied to the interface of the read channel integrated circuit 304 for a given period of time specified by the delay in number of block cycles value specified in the data block portion 504 of the currently access data block.
When the delay period expires (affirmative determination in step 608), a determination is made as to whether the test mode is complete (step 610). The current test mode is complete when the “next address location” value of the data block portion 502 of the currently accessed data block indicates that no further sequential data blocks exist for the given test mode. When the test mode is deemed complete (affirmative determination in step 610), the programmable state machine controller 312 is disabled (step 614). If the test mode is not complete (negative determination in step 610), the programmable state machine controller 312 will proceed to the next memory address location specified in the “next address location” data block portion 502 of the currently accessed data block (step 612). The programmable state machine controller 312 will access the next data block stored in the buffer memory at the specified next address location (return to step 602). Thereafter, the process flow will repeat steps 604, 606, 608, and 612 until the given test mode is complete.
As noted above, the JTAG interface 320 can be readily utilized to store test control data in the buffer memory 314 for various types of test modes for testing the impact of operation of the read channel integrated circuit 304 on various components of the system-on-chip 300. This provides flexible programmability of the programmable state machine controller 312, which allows a user to programming different behaviors of the programmable state machine controller 312. For example, in one embodiment of the invention as discussed above, the read channel integrated circuit 304 can be driven in a given test mode to recreate internally generated voltage supply transients during a functional mode of the read channel integrated circuit 304 and observe the impact of these transients on the performance of system components such as a memory controller and an external DDR memory. By incorporating the programmable state machine controller 312 as an integrated component of the system-on-chip, the interface signals of the read channel integrated circuit 304 can be run at actual functional frequency so that testing can be performed at close to real-time functional mode of operation. Moreover, a separate, external I/O test interface is not needed to input test signals for driving the read channel integrated circuit 304, which eliminates the need for routing test signals for the read channel integrated circuit 304 on existing slower communication busses of the system-on-chip 300, or having to add additional data/control busses to support and route the I/O test signals resulting in problematic routing issues and wiring congestion.
Multiple disk-based storage devices 100 may be incorporated into a virtual storage system 900 as illustrated in
In other embodiments of the invention, a programmable state machine controller can be programmed to operate other types of integrated circuits formed on a system-on-chip to validate operation of the system-on-chip. The system-on-chip can be a storage controller or another type of system-on-chip that is commonly used in other types of devices or systems. In one embodiment, a system-on-chip includes an integrated circuit, a programmable state machine controller, a buffer memory connected to the programmable state machine controller, and an interface for externally accessing the buffer memory and storing test control data in the buffer memory. In a test mode to validate operation of the system-on-chip, the programmable state machine controller is enabled to access test control data from the buffer memory, and process the test control data to generate test signals that are applied to operate the integrated circuit and validate operation of the system-on-chip based on the operation of the integrated circuit.
In this regard, although embodiments of the invention have been described herein with reference to the accompanying drawings, it is to be understood that embodiments of the invention are not limited to the described embodiments, and that various changes and modifications may be made by one skilled in the art resulting in other embodiments of the invention within the scope of the following claims.
