Patent Application
20100019351
This invention relates to varactors, and more particularly, to varactors with improved tuning ranges for use in integrated circuits.
Modern integrated circuits are often formed from metal-oxide-semiconductor (MOS) transistors. For example, integrated circuits often use complementary metal-oxide-semiconductor (CMOS) transistor technology. CMOS integrated circuits have n-channel metal-oxide-semiconductor (NMOS) and p-channel metal-oxide-semiconductor (PMOS) transistors.
NMOS and PMOS transistors have four terminals—a drain, a source, a gate, and a body. A doped body contact is generally used in forming the body terminal. For example, n-channel transistors have bodies that are doped p-type. In a p-type body, the body contact is formed from a heavily doped p+ region. Source and drain terminals, which are sometimes collectively referred to as source-drain terminals, are formed by doping source and drain regions within the body. In an n-channel transistor, the source and drain regions are heavily doped with n-type dopant (i.e., the source and drain regions are doped n+).
In each transistor, a gate is formed between the source and drain. The gate includes an insulator. The insulator is typically a silicon oxide layer. A gate conductor is formed on top of the gate insulator. The gate conductor may be, for example, a layer of metal. In modern integrated circuits, the gate conductor of an MOS transistor is typically formed from heavily doped polysilicon. A metal silicide layer may be formed on the upper surface of the doped polysilicon gate.
Many integrated circuit applications require capacitors. In certain situations, varactors are required. Varactors, which are sometimes referred to as variable capacitors, exhibit tunable capacitance values. The magnitude of a varactor's capacitance may be controlled by controlling the magnitude of the voltage across the varactor's terminals. Varactors may be used in analog and digital circuits (e.g., to tune a frequency of oscillation or other circuit parameter).
Varactors may be formed from metal-oxide-semiconductor (MOS) structures. An advantage of MOS varactor structures is that structures of this type may be formed using the same process technology that is used to form the metal-oxide-semiconductor transistors on a given metal-oxide-semiconductor integrated circuit.
Varactors may be characterized by figures of merit such as quality factor (Q) and tuning range (Cmax versus Cmin). Satisfactory operation of a varactor requires acceptable tuning range performance without sacrificing quality factor performance. As feature sizes shrink with successive generations of integrated circuit, it can be difficult to achieve varactor performance goals.
In view of these challenges it would be desirable to be able to provide improved metal-oxide-semiconductor varactors.
In accordance with the present invention, a varactor may have a first terminal connected to a gate. The gate may be formed from a gate conductor and a gate insulator. The gate conductor may be formed from a doped semiconductor such as doped polysilicon. A p-type dopant may be used in doping the polysilicon. The gate insulator may be formed from a layer of insulator such as silicon oxide. The gate insulator may be located between the gate conductor and a body region. The body of the varactor may be formed from a region of a silicon substrate.
Source and drain contact regions may be formed in the body. The body and the source and drain in the body may be doped with n-type dopant. The varactor may have a second terminal connected to the n-type source and drain.
A control voltage may be used to adjust the level of capacitance produced by the varactor between the first and second terminals. A positive control voltage may produce a larger capacitance than a negative control voltage. When the positive control voltage is applied to the varactor so that the p+ polysilicon gate conductor is at a higher voltage than the n+ source and drain, no depletion layer is formed in the gate, allowing capacitance to be maximized. Application of the negative control voltage may produce a depletion layer in the p+ polysilicon gate layer that helps to reduce the minimum attainable capacitance in the varactor.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description.
The present invention relates to metal-oxide-semiconductor (MOS) varactors that are formed on integrated circuits. The integrated circuits may be of any suitable type. With one suitable arrangement, metal-oxide-semiconductor varactors in accordance with an embodiment of the invention are formed on integrated circuits such as programmable logic device integrated circuits. This is, however, merely illustrative. Metal-oxide-semiconductor varactors in accordance with embodiments of the invention may be formed on integrated circuits such as digital signal processors, microprocessors, custom integrated circuits, or other integrated circuits. In environments such as these, varactors may be used to provide circuits with controllable capacitance values. Controllable capacitance may be used, for example, to adjust the performance of analog and digital circuits.
Varactors in accordance with the invention have two terminals. In a typical circuit, a direct-current (DC) control voltage may be applied across the varactor terminals to adjust the capacitance provided by the varactor. The adjustable capacitance may be used in an alternating-current (AC) circuit (as an example).
A schematic diagram of a conventional p-channel metal-oxide-semiconductor (PMOS) varactor 42 is shown in
Gate G may be formed from gate conductor 48 and a thin layer of insulator 46. Insulator 46 is typically based on silicon dioxide. Gate conductor 48 is generally formed from heavily doped p-type polysilicon.
Conductive paths may be used to connect gate G to a first terminal such as terminal TA and may be used to connect drain D, source S, and body B to a second terminal such as terminal TB. During operation of varactor 42 in a circuit, the voltage across terminals TA and TB serves as a control voltage that adjusts the capacitance exhibited by varactor 42.
A graph showing a capacitance versus voltage characteristic for a conventional varactor such as varactor 42 is shown in
In inversion mode, the voltage Vab across terminals TA and TB is negative. The negative voltage on terminal TA draws minority carriers (holes) under gate G. In this situation, the holes form a conductive inversion layer in the channel region under gate G.
In accumulation mode, the voltage on terminal TA is positive. The positive voltage on gate G draws electrons under gate G to form a conductive electrode for the varactor (i.e., the lower “plate” in the parallel plate varactor).
At low voltages near Vab values of 0 volts, varactor 42 is said to exhibit depletion. In this situation, a series-connected depletion capacitance Cdep is formed due to the absence of carriers under gate G.
Inversion mode varactors can be subject to large parasitics (e.g., parasitic resistances and parasitic capacitances). Varactors operated in inversion mode can also exhibit overly rapid changes of capacitance with respect to voltage changes, making control operations more sensitive than desired. As a result, accumulation mode operation is generally preferred when using PMOS varactors. Nevertheless, PMOS varactors such as varactor 42 may exhibit undesirable parasitics when operated in accumulation mode. In particular, varactor 42 may exhibit a parasitic body (well) resistance between the region under gate G and body terminal 50.
These shortcomings are typically also exhibited by NMOS varactors. A conventional NMOS varactor is shown in
As with PMOS varactors, parasitics tend to degrade performance when NMOS varactors such as varactor 60 of
Because of the shortcomings of inversion mode varactors and the poor performance of NMOS and PMOS varactors in accumulation mode, modern varactors are typically formed using an n-type accumulation mode structure of the type shown in
Varactor structures of the type shown in
Despite these advantages, n-type accumulation mode varactors suffer from degraded capacitance tuning ranges due to formation of a depletion layer in the polysilicon gate. The capacitance produced by an n-type accumulation mode structure varies from a minimum capacitance Cmin when negative control voltages are applied to a maximum capacitance Cmax when positive control voltages are applied. As shown in
As a result of this behavior, depletion layer effects in conventional n-type accumulation mode varactors are counterproductive. When attempting to bias varactor 70 with a positive voltage to maximize the capacitance of varactor 70, the presence of the depletion layer degrades the maximum attainable capacitance. When attempting to bias varactor 70 with a negative voltage to minimize the capacitance of varactor 70, there is no depletion layer, so the minimum capacitance is fixed at the value associated with oxide thickness Tox.
A varactor 82 in accordance with an embodiment of the present invention is shown in
Varactor terminal TB may be connected to source S and drain D using conductive paths. Terminal TA may be connected to the gate portion of varactor 82 using a conductive path. The gate of varactor 82 includes a conductive gate layer 86 and a gate insulating layer 88. Conductive layer 86 may be formed from a p+ semiconductor such as polysilicon doped p+ using p-type dopant. The p+ doped polysilicon layer may, if desired, include a silicided upper portion (e.g., a layer of metal silicide). The presence of the silicide layer may help to reduce the resistance of the gate material. Gate insulating layer 88 may be formed from silicon oxide or any other suitable insulator (e.g., insulators including hafnium or other materials). The conductive paths that connect regions 90 to terminal TB and that connect conductive layer 86 to terminal TA may be formed from metal or other suitable conductors.
A control voltage Vab (i.e., a DC voltage) may be applied to varactor 82 across terminals TA and TB. A minimum capacitance Cmin may be produced when a negative control voltage is applied (e.g., −0.5 volts) and a maximum capacitance Cmax may be produced when a positive control voltage is applied (e.g., 2.0 volts).
When a positive voltage is applied, holes are repelled from terminal TA and accumulate at the interface between polysilicon 86 and oxide 88. As a result, no depletion layer is formed in polysilicon layer 86. The thickness of the insulating layers in varactor 82 is therefore equal to the thickness Tox of oxide layer 88, as shown in
When a negative voltage is applied across varactor 82, the negative voltage produces a depletion region such as depletion region 92 of
In contrast to the conventional n-type accumulation mode varactor structure of
A graph showing the expected behavior of varactor 82 in comparison to a conventional varactor such as varactor 70 of
The measured value of Vs is about 1.0-1.1 volts for p+ doping concentrations of about 1021 cm−3. The tuning range (variation between Cmax and Cmin) for varactor 82 has been measured to improve by 10% relative to the tuning range for conventional varactor 70. Moreover, as a result of the voltage shift and potentially other factors such as reductions in tunneling current through gate oxide, measured leakage currents have been reduced by over 100×. These reductions in leakage current have improved the quality factor Q of the varactor.
In general, there is a tradeoff between quality factor Q and tuning range. To achieve high Q values, it might be desirable to use short channel lengths (gate lengths), as these short gate lengths demonstrate low levels of parasitic well resistance. Structures formed with short gate lengths tend to exhibit reduced tuning ranges, however, because of the presence of non-negligible parasitic capacitances Cgs due to fringing electromagnetic fields. When Cgs is non-negligible, the tuning range (Cmax+Cgs)/(Cmin+Cgs) tends to be reduced.
In a given semiconductor fabrication process, design rules dictate the minimum acceptable gate length LGmin. In conventional varactors, gate lengths LG of about 2×-3× LGmin are used to avoid poor tuning ranges. In arrangements such as these, in which the lateral sizes of the gates are not particularly small, the lack of a self-aligned gate fabrication process is not anticipated to pose significant fabrication challenges. If desired, gate mask arrangements may be used that provide additional design margin for varactor 82. The desirability of these gate arrangements may be understood with reference to
During fabrication of conventional varactor 70, a self-aligned n+ implant process may be used. As shown in
When forming varactors such as varactor 82 of
During the p+ ion implantation step that is used in forming p+ layer, photoresist mask layer 110 may be misaligned as shown in
A top view of varactor 82 showing how the p+ implant region may be configured to underlap the outer perimeter of polysilicon gate conductor 86 in this way is presented in
A flow chart of illustrative steps involved in using varactor 82 in circuitry on an integrated circuit is shown in
At step 120, circuitry in an integrated circuit may be used to apply a control voltage Vab (DC) to varactor 82 across terminals TA and TB. If the control voltage is positive (e.g., Vab=2.0 volts as an example), a maximum capacitance value Cmax may be produced without creating a depletion layer in gate conductor 86 (step 122). If the control voltage is negative (e.g., Vab=−0.5 volts as an example), a depletion layer in polysilicon layer 86 and a corresponding minimum capacitance value Cmin may be produced (step 124) by varactor 82. As shown schematically by step 126, the capacitance that is produced across terminals TA and TB may be used in a circuit (e.g., to tune a circuit, etc.). As indicated by line 128, the varactor adjustment and usage operations of
If desired, varactors of the type shown in
The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.
