An aspect of the present invention relates to a variable attenuator for an RF signal.
A configuration in which field effect transistors (FETs) 161 and 162 and 50Ω resistors 151 and 152 are connected in parallel to a through terminal and a couple terminal of a 90° coupler is known as a variable attenuator of an RF signal (refer to Patent Document 1: Japanese Unexamined Patent Publication No. 2000-507751). In this circuit, when the FETs 161 and 162 are turned off, a signal transmitted to an input terminal is absorbed by the 50Ω resistors 151 and 152, and an attenuation amount of a signal output from an output terminal (an isolation terminal) is maximized, and when the FETs 161 and 162 are turned on, most of the signal is reflected to the output terminal, and the attenuation amount of the signal output from the output terminal is reduced.
In the circuit described in Patent Document 1, when a resistance value of a variable resistor matches a characteristic impedance of a transmission line constituting a quadrature phase hybrid circuit, an attenuation amount of an output signal becomes maximum. However, the maximum value of the attenuation amount may be insufficient depending on the application. Therefore, a variable attenuation circuit with a sufficiently large attenuation amount is desired.
A variable attenuator according to an aspect of the present invention is a variable attenuator which is formed by coupling a first transmission line and a second transmission line having an electrical length of λ/4 corresponding to a wavelength λ of an input signal, has one end of the first transmission line as an input terminal, has the other end of the first transmission line as a through terminal, has one end of the second transmission line as a coupling terminal and has the other end of the second transmission line as an output terminal, wherein the variable attenuator has two first resistance elements having the same impedance at both the through terminal and the coupling terminal, and has two second resistance elements having the same impedance at both the input terminal and the output terminal.
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same elements will be designated by the same reference symbols, and redundant description will be omitted.
Each of the two transmission lines L1 and L2 is configured with a linear pattern and has an electrical length of λ/4 corresponding to a wavelength λ of an input signal. The two transmission lines L1 and L2 are coupled to each other over a portion of the electrical length λ/4. One end of the transmission line L1 is electrically connected to an input terminal RFIN, and the other end is electrically connected to a through terminal RFTH. Additionally, one end of the transmission line L2 coupled to the transmission line L1 is electrically connected to a coupling terminal RFCP, and the other end of the transmission line L2 is electrically connected to an output terminal RFOUT. The output terminal RFOUT may be called an isolation terminal. In such a configuration, an input signal input from the input terminal RFIN is transmitted from the transmission line L1 side to the transmission line L2 side, and an output signal is generated at the output terminal RFOUT.
The resistance elements 3a and 3b have the same resistance value and are provided between the through terminal RFTH and the coupling terminal RFCP and a ground GND. The resistance elements 5a and 5b have the same resistance value and are provided between the input terminal RFIN and the output terminal RFOUT and the ground GND.
Specifically, the resistance element 3a includes an FET 7a and a resistor 9a. A drain which is one terminal of the FET 7a is connected to the through terminal RFTH, a source which is the other terminal of the FET 7a is connected to the ground GND, and a gate which is a control terminal of the FET 7a is connected to a control terminal Vg2 via the resistor 9a. Thus, the gate of the FET 7a receives a control signal supplied to the control terminal Vg2.
Similarly, the resistance element 3b includes an FET 7b and a resistor 9b. A drain which is one terminal of the FET 7b is connected to the coupling terminal RFCP, a source which is the other terminal of the FET 7b is connected to the ground GND, and a gate which is a control terminal of the FET 7b is connected to the control terminal Vg2 via the resistor 9b. Thus, as in the FET 7a, the gate of the FET 7b receives a control signal supplied to the control terminal Vg2.
The FETs 7a and 7b constituting the resistor pair 3 have substantially the same electrical characteristics. Therefore, the resistance values of the resistance elements 3a and 3b can be changed while maintaining the same value by adjusting the control signal supplied to the control terminal Vg2.
The resistance element 5a includes an FET 13a and a resistor 15a. A drain which is one terminal of the FET 13a is connected to the input terminal RFIN, a source which is the other terminal of the FET 13a is connected to the ground GND, and a gate which is a control terminal of the FET 13a is connected to a control terminal Vg1 via the resistor 15a. Thus, the gate of the FET 13a receives the control signal supplied to the control terminal Vg1.
Similarly, the resistance element 5b is configured to include an FET 13b and a resistor 15b. A drain which is one terminal of the FET 13b is connected to the output terminal RFOUT, a source which is the other terminal of the FET 13b is connected to the ground GND, and a gate which is a control terminal of the FET 13b is connected to the control terminal Vg1 via the resistor 15b. Thus, the gate of the FET 13b receives the control signal supplied to the control terminal Vg1.
The FETs 13a and 13b constituting the resistor pair 5 have substantially the same electrical characteristics. Therefore, the resistance values of the resistance elements 5a and 5b can be changed while being set to the same value by adjusting the control signal supplied to the control terminal Vg1.
Here, the resistor pairs 3 and 5 may be set to have the same resistance value by setting the electric characteristics of the FETs 7a and 7b and the electric characteristics of the FETs 13a and 13b to be the same, setting the resistance values of the resistors 9a and 9b and the resistance values of the resistors 15a and 15b to be the same and making the control signals supplied to the control terminal Vg1 and the control terminal Vg2 the same. On the other hand, the resistance values of the resistor pair 3 and the resistor pair 5 may be set to be different from each other by making the control signals supplied to the control terminal Vg1 and the control terminal Vg2 different from each other.
A configuration example of the transmission lines L1 and L2 will be described with reference to
As shown in
Further, a ground layer 25 which is spaced apart from upper portions of the transmission lines L1 and L2, extends parallel to the transmission lines L1 and L2 and is formed of a metal (for example, gold) having a predetermined thickness (for example, 2 μm or more) is formed on the outermost surface of the insulating layer 23. The transmission lines L1 and L2 have a gap of 2 μm therebetween, and a degree of coupling between the transmission lines L1 and L2 is determined by the gap and a dielectric constant of the insulating layer filling the gap. The width of the transmission line L1 is made narrower than a width of the transmission line L2 in order to widen the width of the transmission line L2 (to narrow the width of the transmission line L1) and to equalize the degree of coupling of both the transmission lines L1 and L2 with the ground layer 25, and this is because a distance between the ground layer 25 and the transmission line L1 is narrow and thus the degree of coupling of the transmission line L1 with the ground becomes larger than that of the other transmission line L2. In addition, a region of the ground layer 25 overlapping the transmission lines L1 and L2 is also removed in order to equalize the degree of coupling of the transmission lines L1 and L2 with the ground layer 25 by providing the removal region without making the widths of the two transmission lines L1 and L2 largely different, and this is because, when the ground layer is provided on the entire surface without removing the region and the degree of coupling of the transmission line L1 and the transmission line L2 with the ground layer 25 is made equal, the width of the upper transmission line L1 becomes too narrow.
According to the variable attenuator 1 according to the embodiment, the impedance of the resistor pair 3 provided on the through terminal RFTH and the coupling terminal RFCP can be changed. Furthermore, the impedance of the resistor pair 5 provided on the input terminal RFIN and the output terminal RFOUT can be changed by changing. Specifically, when the resistance values (the impedances) of the resistor pairs 3 and 5 are matched to a characteristic impedance of one of the transmission lines L1 and L2 which is respectively connected thereto, reflection of signals is minimized. On the other hand, as the respective resistance values (the impedances) deviate from the characteristic impedance of the one of the transmission lines L1 and L2, the reflection of signals increases due to the impedance mismatch. As a result, the attenuation amount of the signal output from the output terminal RFOUT can be changed.
In the embodiment, the attenuation amount can be increased by providing the resistor pair 5 in addition to the resistor pair 3. Further, since the resistance elements 5a and 5b constituting the resistor pair 5 are set to have the same resistance value, the attenuation operation of the attenuator 1 can be stabilized.
In particular, in the embodiment, control signals received at control terminals of a transistor pair included in the resistor pair 3 and a transistor pair included in the resistor pair 5 are set to be the same, and thus resistance values between terminals of transistors are matched to each other. Thus, the maximum attenuation amount can be increased. Furthermore, when the control signals received at the control terminals of the transistor pair included in the resistor pair 3 and the transistor pair included in the resistor pair 5 are set to match each other, the maximum attenuation amount can also be further increased.
Hereinafter, the measurement result of the characteristic of the variable attenuator 1 will be shown.
Further,
Further,
While the principles of the present invention have been illustrated and described in the preferred embodiment, it will be appreciated by those skilled in the art that the present invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the embodiment. Therefore, all modifications and changes coining from the scope of claims and the scope of the spirit thereof will be claimed.
For example, the configurations of the resistor pairs 3 and 5 included in the variable attenuator 1 of the above-described embodiment can be variously changed.
The resistance element 5a shown in
Number | Date | Country | Kind |
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2018-113524 | Jun 2018 | JP | national |
Number | Name | Date | Kind |
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6414565 | Tanaka | Jul 2002 | B1 |
6480708 | Tanaka | Nov 2002 | B1 |
7492235 | Vice | Feb 2009 | B2 |
20060273863 | Quan | Dec 2006 | A1 |
Number | Date | Country |
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2000-507751 | Jun 2000 | JP |
WO 9728598 | Jul 1997 | WO |
Number | Date | Country | |
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20190386367 A1 | Dec 2019 | US |