Claims
- 1. A device for tuning an electronic circuit, comprising:
a moveable membrane, wherein changes in distance between the membrane and the electronic circuit produce changes in capacitance of the electronic circuit; and a first capacitive arrangement operatively associated with the membrane, comprising a first capacitor plate and a second capacitor plate, wherein the first capacitor plate is located at a first distance from the electronic circuit and connected with the membrane, and the second capacitor plate is located at a second distance from the electronic circuit, the second distance being greater than the first distance.
- 2. The device of claim 1, wherein the membrane has a non-actuated condition and an actuated condition, and wherein tuning of the electronic circuit occurs during the actuated condition of the membrane.
- 3. The device of claim 2, wherein the distance between the membrane and the electronic circuit during the actuated condition of the membrane is greater than the distance between the membrane and the electronic circuit during the non-actuated condition of the membrane.
- 4. The device of claim 2, further comprising a second capacitive arrangement having a third capacitor plate and a fourth capacitor plate.
- 5. The device of claim 4, wherein a distance between the membrane and the electronic circuit during the actuated condition of the membrane can either be greater or shorter than a distance between the membrane and the electronic circuit during the nonL&P actuated condition of the membrane.
- 6. The device of claim 4, wherein the third capacitor plate is the first capacitor plate and the fourth capacitor plate comprises the electronic circuit.
- 7. The device of claim 1, wherein the device is fabricated using a wafer-level packaging technique.
- 8. An actuator for varying a capacitance of an electronic circuit, comprising:
a moveable membrane, wherein movement of the membrane varies the capacitance of the electronic circuit; and a rod connected with the membrane, wherein: the movement of the membrane is obtained by varying the distance of the rod from the electric circuit; the membrane has a static condition and a dynamic condition; and a distance between the membrane and the electronic circuit during the dynamic condition of the membrane can either be greater or shorter than a distance between the membrane and the electronic circuit during static condition of the membrane.
- 9. The actuator of claim 8, wherein the rod is a micrometer rod.
- 10. A membrane actuator for tuning an electronic circuit, comprising:
a first substrate; a first conductive material disposed on the first substrate and containing the electronic circuit, the first substrate and the first conductive material forming a first layer; a deformable membrane; a second conductive material connected with the flexible membrane, the flexible membrane and the second conductive material forming a second layer, the flexible membrane and the second conductive material being located at a distance from the first substrate and the first conductive material; a second substrate; a third conductive material connected with the second substrate, the second substrate and third conductive material forming a third layer; and a magnetic element attached to the membrane, wherein, upon application of a bias voltage to the magnetic element, a magnetic force is produced, causing the membrane to deform, thereby varying the distance of the second conductive material from the electronic circuit and tuning the electronic circuit.
- 11. The membrane actuator of claim 10, wherein a distance between the membrane and the electronic circuit upon application of the bias voltage is greater than a distance between the membrane and the electronic circuit in absence of application of the bias voltage.
- 12. The membrane actuator of claim 10, wherein a distance between the membrane and the electronic circuit upon application of the bias voltage can either be greater or shorter than a distance between the membrane and the electronic circuit in absence of application of the bias voltage.
- 13. The membrane actuator of claim 10, wherein the magnetic element is a voice coil.
- 14. A membrane actuator for tuning an electronic circuit, comprising:
a first substrate; a first conductive material disposed on the first substrate and containing the electronic circuit, the first substrate and the first conductive material forming a first layer; a flexible membrane; a second conductive material contacting the flexible membrane, the flexible membrane and the second conductive material forming a second layer, the flexible membrane and second conductive material being disposed above the first substrate and first pattern; a second substrate; a third conductive material contacting the second substrate, the second substrate and third conductive material forming a third layer, wherein: a parallel plate capacitor having an upper plate and a lower plate is formed between the second layer and the third layer, the second conductive material forming the upper plate of the capacitor and the third conductive material forming the lower plate of the capacitor, and when a bias voltage is applied between the upper plate and the lower plate, an electrostatic force is produced, causing the membrane to deform, thereby varying the capacitance of the electronic circuit.
- 15. The membrane actuator of claim 14, wherein a distance between the membrane and the electronic circuit upon application of the bias voltage is greater than a distance between the membrane and the electronic circuit in absence of application of the bias voltage.
- 16. The membrane actuator of claim 14, wherein a distance between the membrane and the electronic circuit upon application of the bias voltage can either be greater or shorter than a distance between the membrane and the electronic circuit in absence of application of the bias voltage.
- 17. The membrane actuator of claim 14, wherein the first substrate is a micromachined wafer.
- 18. The membrane actuator of claim 14, further comprising polymide spacers for separating the first layer from the second layer.
- 19. The membrane actuator of claim 14, further comprising polymide spacers for separating the first layer from the second layer and the second layer from the third layer.
- 20. The membrane actuator of claim 14, further comprising a feedback control system to control the membrane position.
- 21. The membrane actuator of claim 20, wherein the feedback control system comprises:
a voltage controlled oscillator having a voltage controlled oscillator frequency, the voltage controlled oscillator frequency being associated with the capacitance of the capacitor; a reference oscillator having a reference oscillator frequency; a mixer for comparing the voltage controlled oscillator frequency with the reference oscillator frequency, the mixer having a first mixer input connected to the voltage controlled oscillator, a second mixer input connected to the reference oscillator, and a mixer output, the mixer output having a mixer output amplitude and a mixer output frequency; a low-pass filter, having a low-pass filter input connected to the mixer output, and a low-pass filter output; a detecting device having a detecting device input connected to the low-pass filter output and having a detecting device output; and a differential amplifier having a first differential amplifier input connected to the detecting device output, a second differential amplifier input connected to a control signal, and a differential amplifier output, the differential amplifier output being connected to the upper and lower plate of the capacitor.
- 22. The membrane actuator of claim 21, wherein the low-pass filter is designed so that the mixer output frequency falls outside a passband edge of the lowpass filter during normal operation.
- 23. The membrane actuator of claim 21, wherein the detecting device output has an output signal strength inversely proportional to the mixer output amplitude.
- 24. The membrane actuator of claim 21, wherein the control signal is adjustable.
- 25. An actuator for tuning an electronic circuit, comprising:
a first substrate; a first cavity located in the first substrate; a first electrically conductive arrangement disposed in the first cavity, the first electrically conductive arrangement comprising the electronic circuit; a second substrate; a second cavity located in the second substrate; a second electrically conductive arrangement disposed in the second cavity; a flexible membrane located between the first substrate and the second substrate; and a third electrically conductive arrangement contacting the flexible membrane, wherein tuning of the electronic circuit is obtained by movement of the flexible membrane.
- 26. The actuator of claim 25, wherein the first substrate and the second substrate are micromachined wafers.
- 27. The actuator of claim 25, wherein the flexible membrane is attached to the first substrate.
- 28. The actuator of claim 25, wherein the first cavity and second cavity are formed by etching the first and second substrate for about 40 microns.
- 29. The actuator of claim 25, wherein movement of the membrane is obtained through electrostatic actuation.
- 30. A method for fabricating a membrane, comprising the steps of:
providing a substrate; depositing a first metal layer on the substrate; patterning the first metal layer to form a first metal pad; depositing a membrane layer on the substrate and the first metal pad; curing the membrane layer; depositing a second metal layer on the cured membrane layer; depositing a photoresist layer on the second metal layer; patterning the photoresist layer to form a photoresist pad; patterning the second metal layer to form a second metal pad; removing the first metal pad; and removing the photoresist pad.
- 31. The method of claim 30, wherein the membrane layer is a polymide layer.
- 32. The method of claim 30, wherein the substrate is provided with an upper protective layer and a lower protective layer, the upper protective layer being disposed between the substrate and the first metal layer after the step of depositing the first metal layer over the substrate.
- 33. The method of claim 30, further comprising the steps of:
patterning the lower protective layer; patterning the substrate; and patterning the upper protective layer.
- 34. The method of claim 33, wherein the substrate is a silicon wafer and the step of patterning the substrate is performed through immersion in a KOH solution at about 100° C.
- 35. The method of claim 33, wherein the substrate is a silicon wafer and the upper protective layer and lower protective layer are made of SiN, the step of patterning the lower protective layer, the step of patterning the upper protective layer and the step of removing the first metal pad being performed by immersing the substrate in etchant.
- 36. The method of claim 35, wherein the etchant comprises buffered oxide etchant and Au etchant.
- 37. The method of claim 30, wherein the first metal layer is a Ti—Au layer.
- 38. The method of claim 30, wherein the second metal layer is a Ti—Au layer.
- 39. The method of claim 32, wherein the upper protective layer and the lower protective layer are made of SiN and deposited using a PECVD technique.
- 40. The method of claim 32, wherein the upper protective layer and the lower protective layer are made of SiN and deposited using a LPCVD technique.
- 41. A membrane fabrication method comprising the steps of:
providing a substrate having a first side and a second side; depositing a first protective layer on the first side; depositing a second protective layer on the second side; depositing a first metal layer on the first protective layer; patterning the first metal layer to form a first metal pad; patterning the second protective layer to form etch windows; forming a membrane layer on the substrate and the first metal pad; curing the membrane layer; depositing a second metal layer on the cured membrane layer; forming a photoresist layer on the second metal layer; patterning the photoresist layer to form a photoresist pad; removing a portion of the substrate through the etch windows of the second protective layer; patterning the second metal layer to form a second metal pad; removing the first metal pad; and removing the photoresist pad.
- 42. The method of claim 41, wherein the upper protective layer and the lower protective layer are made of SiN and deposited using a PECVD technique.
- 43. The method of claim 41, wherein the upper protective layer and the lower protective layer are made of SiN and deposited using a LPCVD technique.
CLAIM OF BENEFIT OF PROVISIONAL APPLICATION
[0001] This application claims the benefit of U.S. provisional application Serial No. 60/420,176 filed on Oct. 21, 2002, which is incorporated herein by reference in its entirety.
[0002] The present document is related to the copending and commonly assigned patent application documents entitled “Piezoelectric Switch for Tunable Electronic Components,” Ser. No. ______ (Attorney Docket No. 620723), and “Piezoelectric Actuator for Tunable Electronic Components,” Ser. No. ______ (Attorney Docket No. 620724), which are all filed of even date herewith. The contents of these related applications are hereby incorporated by reference herein.
Provisional Applications (1)
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Number |
Date |
Country |
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60420176 |
Oct 2002 |
US |