This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2021-0040437 filed on Mar. 29, 2021 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.
The present inventive concept relates to a variable capacitor circuit and related control circuits.
Variable capacitor circuits are circuits having a capacitance that varies according to voltage, and may include one or more varactor elements having a capacitance that varies linearly according to voltage. A variable capacitor circuit implemented in an analog manner using the capacitance of a varactor element that changes linearly according to voltage may have limits as to a capacitance range or reducing a capacitance difference that the circuit may provide, and/or may be vulnerable to factors such as variability in manufacturing processes and external noise.
Example embodiments provide a variable capacitor circuit in which capacitance may be finely adjusted and a Q-factor may be improved in a high-frequency environment, and a digitally-controlled oscillator including the same.
According to example embodiments, a variable capacitor circuit includes a capacitor block including a first varactor element comprising a first transistor having a first size, a second varactor element comprising a second transistor having a second size different from the first size, a first terminal commonly connected to a source and a drain of the first transistor, and a second terminal commonly connected to a source and a drain of the second transistor. An RC circuit is connected to a gate of the first transistor and a gate of the second transistor.
According to example embodiments, a variable capacitor circuit includes a first varactor element comprising a first transistor having a first size and configured to operate responsive to a first control signal commonly applied to a source and a drain of the first transistor; and a second varactor element comprising a second transistor having a second size and configured to operate responsive to a second control signal commonly applied to a source and a drain of the second transistor. The second size is different from the first size, and the second control signal is a complementary signal of the first control signal.
According to example embodiments, a digital-controlled oscillator includes an inductor circuit connected to a first power node that is configured to supply a first power supply voltage; a current mirror circuit connected between the inductor circuit and a current circuit that is configured to supply a bias current; and a variable capacitor circuit connected between the current mirror circuit and the inductor circuit and having capacitance determined based on a control signal including digital data of N bits, where N is a natural number. The variable capacitor circuit includes a first transistor and a second transistor connected to each other in parallel, each of the first transistor and the second transistor comprising a gate connected to a node between the current mirror circuit and the inductor circuit, and a source and a drain configured to commonly receive the control signal. A first size of the first transistor is different from a second size of the second transistor.
The above and other aspects, features, and advantages of the present inventive concept will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:
Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.
Referring to
The control signal CTRL may correspond to or carry digital data having a number of bits determined according to the number of varactor elements included in the capacitor block 11. For example, the capacitor block 11 may include 2N varactor elements, and the control signal CTRL may include N-bit digital data.
The RC circuit 12 may include at least one each of a capacitor and a resistor. In an example embodiment, the capacitor of the RC circuit 12 may be connected in series to the capacitor block 11, and a resistor may be connected between a node between the capacitor and the capacitor block 11 and a ground node. By connecting the RC circuit 12 to the capacitor block 11, the Q-factor may be improved.
A capacitance difference ΔC that may be controlled by the varactor element may be determined as a difference between the maximum value CA and the minimum value CD of the capacitance, as illustrated in the graph of
In digital methods, since the capacitance of one varactor element is determined only by the maximum value CA or the minimum value CD, it may be necessary to precisely design the transistors constituting the varactor element for fine capacitance control. However, as the size of the transistor gradually decreases and the process becomes finer, there may be a limit in reducing the capacitance difference ΔC, which may lead to a decrease in the resolution of the capacitance adjustable by the variable capacitor circuit 10.
In an example embodiment, the variable capacitor circuit 10 capable of increasing the resolution of adjustable capacitance using two or more varactor elements is proposed. For example, a first varactor element and a second varactor element may be commonly connected to one RC circuit 12, and the first varactor element and the second varactor element may be implemented with transistors of different sizes (e.g., based on channel length, channel width, number of fin structures, etc.) and/or other different characteristics such that the first and second varactor elements provide different capacitances. The terms first, second, etc. may be used herein merely to distinguish one element from another. When the first varactor element is in the depletion mode, the second varactor element operates in the accumulation mode, and when the first varactor element is in the accumulation mode, the second varactor element operates in the depletion mode. Since the adjustable capacitance difference ΔC is determined by the difference in size of transistors providing the first varactor element and the second varactor element, the variable capacitor circuit 10 capable of finely adjusting the capacitance while significantly reducing an increase in process difficulty may be implemented.
Referring first to
A capacitor block 31 may include a first varactor element VAR1 including a first transistor and a second varactor element VAR2 including a second transistor. In the example embodiment illustrated in
Since the first transistor and the second transistor have different sizes, the capacitance that the first varactor element VAR1 has in the depletion mode and the accumulation mode, respectively, may be different from the capacitance that the second varactor element VAR2 has in the depletion mode and the accumulation mode, respectively. For example, the first transistor may be larger than the second transistor. In this case, the capacitance of the first varactor element VAR1 in the accumulation mode may be greater than the capacitance of the second varactor element VAR2 in the accumulation mode. Therefore, when the first varactor element VAR1 is in the accumulation mode, the second varactor element VAR2 is set to the depletion mode, and when the first varactor element VAR1 is in the depletion mode, the second varactor element VAR2 may be set to the accumulation mode, the adjustable capacitance difference in the variable capacitor circuit 30 may be reduced. As a result, the variable capacitor circuit 30 capable of finely adjusting the capacitance may be implemented, and the capacitance resolution of the variable capacitor circuit 30 may be improved.
A variable capacitor circuit 40 according to an example embodiment illustrated in
Next, referring to
The source and drain of the first transistor and the source and drain of the second transistor may be commonly connected to a second external node EN2. When a control signal CTRL has a low voltage level corresponding to a low logic value, the first varactor element VAR1 may operate in an accumulation mode and the second varactor element VAR2 may operate in a depletion mode. On the other hand, when the control signal CTRL has a high voltage level corresponding to a high logic value, the first varactor element VAR1 may operate in a depletion mode and the second varactor element VAR2 may operate in an accumulation mode.
The voltage level of the first control signal CTRL1 may be determined as one of a low voltage level VLOW and a high voltage level VHIGH. The second control signal CTRL2 may have a high voltage level VHIGH when the first control signal CTRL1 has a low voltage level VLOW, and may have a low voltage level VLOW when the first control signal CTRL1 has a high voltage level VHIGH.
The low voltage level VLOW and the high voltage level VHIGH may be determined by a first threshold voltage VTH1 and a second threshold voltage VTH2 at which the first varactor element VAR1 and the second varactor element VAR2 operate in a linear range. The low voltage level VLOW may be lower than the first threshold voltage VTH1, and the high voltage level VHIGH may be higher than the second threshold voltage VTH2.
When the first control signal CTRL1 has a low voltage level VLOW corresponding to a low logic value, a voltage less than the first threshold voltage VTH1 is input to the source and drain of the first transistor, and a voltage greater than the second threshold voltage VTH2 may be input to the source and drain of the second transistor. On the other hand, when the first control signal CTRL1 has a high voltage level VHIGH corresponding to a high logic value, a voltage greater than the second threshold voltage VTH2 is input to the source and drain of the first transistor, and a voltage less than the first threshold voltage VTH1 may be input to the source and drain of the second transistor.
When the first control signal CTRL1 has the low voltage level VLOW, the first varactor element VAR1 may operate in an accumulation mode and the second varactor element VAR2 may operate in a depletion mode. Accordingly, capacitance CHIGH provided by the capacitor block 31 may be determined as a sum of a first accumulation capacitance CA1 of the first varactor element VAR1 and a second depletion capacitance CD2 of the second varactor element VAR2. On the other hand, when the first control signal CTRL1 has the high voltage level VHIGH, the first varactor element VAR1 may operate in a depletion mode and the second varactor element VAR2 may operate in an accumulation mode. Accordingly, capacitance CLOW provided by the capacitor block 31 may be determined as a first depletion capacitance CD1 of the first varactor element VAR1 and a second accumulation capacitance CA2 of the second varactor element VAR2.
In the example embodiment illustrated in
ΔC=CHIGH−CLOW=(CA1+CD2)−(CA2+CD1) [Equation 1]
As a result, the capacitance difference ΔC adjustable by the capacitor block 31 may decrease as the size difference between the first transistor and the second transistor decreases. Accordingly, the capacitance difference ΔC that may be adjusted in the capacitor block 31 may be determined using the difference in size between the first transistor and the second transistor, for example, using the difference in channel length and channel width, or the like, and the capacitor block 31 and the variable capacitor circuit 30 capable of finely adjusting the capacitance may be implemented.
Since the first transistor and the second transistor are PMOS transistors, in the example embodiment described with reference to
Other operations may be similar to the example embodiment described above with reference to
Referring to
Referring to
The first transistor 110 may include a first source region 111, a first drain region 112, and a first gate structure 115, and the second transistor 120 may include a second source region 121, a second drain region 122 and a second gate structure 125. The source regions 111 and 121 and the drain regions 112 and 122 may be formed in a well region 102 formed in a substrate 101. The well region 102 may be a region doped with impurities of a specific conductivity type.
The first gate structure 115 may include a gate insulating layer 116, a gate electrode layer 117, and a gate spacer 118. The second gate structure 125 may also include a gate insulating layer 126, a gate electrode layer 127, and a gate spacer 128.
The first transistor 110 and the second transistor 120 may have different sizes. Referring to
Referring to
Referring first to
However, in the example embodiment illustrated in
Next, referring to
Referring to
The first transistor 210 may include a first source region 211, a second drain region 212, and a first gate structure 215, and the second transistor 220 may include a second source region 221, a second drain region 222 and a second gate structure 225. The source regions 211 and 221 and the drain regions 212 and 222 may be connected to the fin structures F1 to F3 and may be electrically connected to active regions 202 and 203 formed in a substrate 201.
The active regions 202 and 203 may include a lower active region 202, and an upper active region 203 connected to the fin structures F1 to F3. For example, the source regions 211 and 221 and the drain regions 212 and 222 may be formed by a selective epitaxial growth (SEG) process performed using the upper active region 203.
The first gate structure 215 may include a gate insulating layer 216, a gate electrode layer 217, a gate spacer 218, and a capping layer 219. The second gate structure 225 may also include a gate insulating layer 226, a gate electrode layer 227, a gate spacer 228, and a capping layer 229.
The first transistor 210 and the second transistor 220 may have different sizes. As illustrated in
Referring to
Accordingly, in the accumulation mode, the capacitance of the first transistor 210 may be greater than that of the second transistor 220A, and in the depletion mode, the capacitance of the first transistor 210 may be less than the capacitance of the second transistor 220A. The difference between the capacitance of the first transistor 210 and the capacitance of the second transistor 220A may be greater than in the example embodiment described with reference to
Referring to
Accordingly, the difference between the capacitance of the first transistor 210 and the capacitance of the second transistor 220A may be greater than in the example embodiment described with reference to
First, referring to
The inverter INV may receive a first control signal through the second external node EN2, and may output a second control signal by inverting the first control signal. Accordingly, a signal input to the source and drain of the first varactor element VAR1 and a signal input to the source and drain of the second varactor element VAR2 may have a complementary relationship with each other. Since the first varactor element VAR1 and the second varactor element VAR2 are connected to each other in parallel, the capacitance provided by the capacitor block 310 may be determined as a sum of the capacitance of the first varactor element VAR1 and the capacitance of the second varactor element VAR2.
Next, referring to
Referring to
The first transistor providing the first varactor element VAR1 may have a size different from that of the second transistor providing the second varactor element VAR2. For example, when the first transistor is larger than the second transistor, the capacitance provided by the capacitor block 310 has a maximum value when the first varactor element VAR1 is in the accumulation mode, and has a minimum value when the second varactor element VAR2 is in the accumulation mode.
First, referring to
In an example embodiment, the control signal may have a voltage determined by N-bit digital data, and the number of bits of the digital data may be determined by the number of unit capacitor blocks 411-414 included in the variable capacitor circuit 400. For example, when the variable capacitor circuit 400 includes N unit capacitor blocks 411-414, N control signals input to the unit capacitor blocks 411-414 may be generated by N-bit digital data. For example, a control signal input to each of the unit capacitor blocks 411-414 may have a voltage determined to correspond to any one of N bits included in digital data.
A configuration of each of the unit capacitor blocks 411-414 may be similar to the above-described embodiments. For example, each of the unit capacitor blocks 411-414 may include a pair of varactor elements and one inverter. According to example embodiments, the pair of varactor elements may be implemented as NMOS transistors or PMOS transistors. Alternatively, in an example embodiment, one of the pair of varactor elements may be implemented as an NMOS transistor, and the other may be implemented as a PMOS transistor. In this case, each of the unit capacitor blocks 411-414 may not include an inverter.
The configuration of the unit capacitor blocks 411-414 may be determined by a difference between a maximum value and a minimum value of the capacitance to be controlled by the variable capacitor circuit 400, and/or the minimum unit of a difference in capacitance to be controlled by the variable capacitor circuit 400. For example, when the capacitance is adjusted in a very small unit (for example, atto farads) by the variable capacitor circuit 400, a size difference between a pair of transistors providing a pair of varactor elements in each of the unit capacitor blocks 411-414 may be formed to be significantly small. Also, when the difference between a maximum value and a minimum value of the capacitance that may be provided by the variable capacitor circuit 400 is relatively large, the number of unit capacitor blocks 411-414 included in the variable capacitor circuit 400 may increase.
Referring to
Referring to
Each of the unit capacitor blocks UCB[0]-UCB[N−1] includes first and second varactor elements VAR1 and VAR2 and an inverter INV, and the first and second varactor elements VAR1 and VAR2 may be connected to each other in parallel. Each of the first and second varactor elements VAR1 and VAR2 may be implemented as a transistor. In at least some of the unit capacitor blocks UCB[0]-UCB[N−1], the first and second varactor elements VAR1 and VAR2 may have different sizes. For example, a transistor providing the first varactor element VAR1 of the first unit capacitor block UCB[0] and a transistor providing the first varactor element VAR1 of the second unit capacitor block UCB[0] may have different sizes.
The capacitor circuit 510 receives control signals CTRL[0]-CTRL[N−1] corresponding to N-bit digital data, and the control signals CTRL[0]-CTRL[N−1] may be input to the unit capacitor blocks UCB[0]-UCB[N−1], respectively. For example, the first control signal CTRL[0] may be input to the first unit capacitor block UCB[0], and the N-th control signal CTRL[N−1]) may be input to the N-th unit capacitor block UCB[N−1].
The operation of each of the unit capacitor blocks UCB[0]-UCB[N−1] may be determined by the control signals CTRL[0]-CTRL[N−1]. For example, when the N-th bit of the digital data has a high logic value, the N-th control signal CTRL[N−1] may have a voltage corresponding to the high logic value, and the first varactor element VAR1 may operate in a depletion mode and the second varactor element VAR2 may operate in an accumulation mode, in the N-th unit capacitor block UCB[N−1]).
The total capacitance of the capacitor block 510 may be determined as the sum of capacitances provided by the unit capacitor blocks UCB[0]-UCB[N−1]. Accordingly, in the example embodiment illustrated in
Although the example embodiment illustrated in
Referring first to
The first varactor element VAR1 and the second varactor element VAR2 included in the first unit capacitor block 611 may have different characteristics from the first varactor element VAR1 and the second varactor element VAR2 included in the second unit capacitor block 612. For example, a difference in size between the first transistor providing the first varactor element VAR1 and the second transistor providing the second varactor element VAR2, in the first unit capacitor block 611, may be different from a difference in size between the first transistor providing the first varactor element VAR1 and the second transistor providing the second varactor element VAR2 in the second unit capacitor block 612.
By configuring the capacitor block 610 in this manner, the capacitance difference that is adjustable in the first unit capacitor block 611 by the first control signal CTRL1 may be different from the capacitance difference that is adjustable in the second unit capacitor block 612 by the second control signal CTRL2. The capacitance difference adjustable in each of the first unit capacitor block 611 and the second unit capacitor block 612 may increase as the size difference between the first transistor and the second transistor increases.
Hereinafter, the operation of the variable capacitor circuit 600 will be described in more detail with reference to
Referring to
Referring to
In an example embodiment of
Referring to
In the example embodiments described with reference to
As described above, in each of the first unit capacitor block 611 and the second unit capacitor block 612, the first transistor providing the first varactor element VAR1 It may have an area larger than that of the second transistor providing the second varactor element VAR2. Accordingly, referring to Table 1, when the digital data is 00, the capacitance C1 of the capacitor block 610 may have a maximum value, and when the digital data is 11, the capacitance C4 of the capacitor block 610 may have a minimum value. On the other hand, a case in which the first transistor providing the first varactor element VAR1 in the first unit capacitor block 611 is larger than the first transistor providing the first varactor element VAR1 in the second unit capacitor block 612 may be provided as an example, and in this case, the capacitance C2 when the digital data is 01 may be less than the capacitance C3 when the digital data is 10.
Referring to
The TDC 710 may receive a reference clock signal CLKREF and a division signal DIV and output a phase difference between the two signals as a digital code. The loop filter 720 may filter a phase error signal of the TDC 710 and output the phase error signal. The digitally-controlled oscillator (DCO) 730 may generate a clock signal CLK by using the filtered signal. The divider 740 divides the clock signal CLK output from the digitally-controlled oscillator 730 to generate a division signal DIV, and the division signal DIV may be input to the TDC 710. For example, the clock signal CLK output by the digitally-controlled oscillator 730 may be a signal having a frequency of several tens of GHz.
The digitally-controlled oscillator 730 may include an inductor circuit, a current mirror, a variable capacitor circuit, and the like. The inductor circuit may be connected to a first power node supplying the first supply voltage, and the current mirror may be connected between the current circuit supplying the bias current and the inductor circuit. The variable capacitor circuit may be one of the circuits according to the example embodiments described above with reference to
Referring first to
The variable capacitor circuit 810 may have a capacitance determined by the control signals CTRL. For example, the variable capacitor circuit 810 may include a first transistor providing the first varactor element and a second transistor providing the second varactor element. In an example embodiment, a gate of each of the first and second transistors is connected to the first output node OUT1, and a source and a drain of each of the first and second transistors may commonly receive one of the control signals CTRL. The first transistor and the second transistor may be connected to each other in parallel.
The variable capacitor circuit 810 may include a pair of varactor elements connected to the first output node OUT1 and a pair of varactor elements connected to the second output node OUT2. Hereinafter, the operation of the digitally-controlled oscillator 800 and the variable capacitor circuit 810 included in the digitally-controlled oscillator 800 will be described in more detail with reference to
Referring to
The unit capacitor blocks 911-914 may (but do not necessarily) include circuits having a similar structure. In describing the first unit capacitor block 911 as an example, the first unit capacitor block 911 may include a first varactor element VAR1 and a second varactor element VAR2, connected to each other in parallel, and an inverter INV. In this case, the first varactor element VAR1 may be provided by a first transistor, and the second varactor element VAR2 may be provided by a second transistor.
Gates of the first transistor and the second transistor may be connected to the first output node OUT1 through the first RC circuit 915. The source and drain of the first transistor are connected to each other to commonly receive a first control signal CTRL[0], and the source and drain of the second transistor are connected to each other to receive a signal output by the inverter INV in common. Accordingly, a complementary signal of the first control signal CTRL[0] may be input to the source and drain of the second transistor.
The size of the first transistor may be different from the size of the second transistor, in the first unit capacitor block 911. For example, in a case in which the first transistor is larger than the second transistor, when the first varactor element VAR1 operates in the accumulation mode and the second varactor element VAR2 operates in the depletion mode, the first unit capacitor block 911 may have a relatively greater capacitance. The second to fourth unit capacitor blocks 912-914 may be implemented with a circuit similar to that of the first unit capacitor block 911.
Referring to
An operation of each of the unit capacitor blocks 911-914 may be understood with reference to the example embodiments illustrated in
In at least some of the unit capacitor blocks 911-914, size differences between the first transistors providing the first varactor elements VAR1 and the second transistors providing the second varactor elements VAR2 may be different. For example, a size difference between the first transistor and the second transistor included in the first unit capacitor block 911 may be different from a size difference between the first transistor and the second transistor included in the second unit capacitor block 912. An adjustable capacitance difference in each of the unit capacitor blocks 911-914 may be determined according to a size difference between the first transistor and the second transistor. Accordingly, by configuring the first transistor and the second transistor to have different size differences in at least some of the unit capacitor blocks 911-914, capacitances of various magnitudes may be provided to the variable capacitor circuit 910, and capacitance may be adjusted with fine differences.
First, referring to
The delay amount of the delay circuit 1000 may be determined by capacitance of each of the variable capacitor circuits CC. For example, when the capacitance of the variable capacitor circuits CC increases, the delay amount of the delay circuit 1000 may increase, and a phase difference between the input signal IN and the output signal OUT may also increase.
Although the example embodiment illustrated in
The variable capacitor circuits CC may be operated by control signals CTRL1-CTRL16. Each of the variable capacitor circuits CC may have a structure similar to that of the example embodiment described with reference to
In an example embodiment, each of the variable capacitor circuits CC may include the capacitor block 1310 and share one RC circuit 1320. For example, the variable capacitor circuits CC included in the first group 1100 share one RC circuit 1320, and the variable capacitor circuits CC included in the second group 1200 may share one RC circuit 1320.
In an example embodiment, a minimum delay amount adjustable by each of the variable capacitor circuits CC included in the first group 1100 may be different from a minimum delay amount adjustable by each of the variable capacitor circuits CC included in the second group 1200. Also, a maximum delay amount adjustable by the first group 1100 and a maximum delay amount adjustable by the second group 1200 may be different from each other. Accordingly, the phase difference between an input signal INT and an output signal OUT may be variously set by the delay circuit 1000, which will be described below in more detail with reference to
Referring to
As a result, by using the control signals CTRL1-CTRL16 input to the variable capacitor circuits CC in each of the first group 1100 and the second group 1200, a phase difference between the input signal IN and the output signal OUT may be finely adjusted. In the example embodiment illustrated in
As set forth above, according to an example embodiment, a variable capacitor circuit may be implemented in which capacitance may be finely adjusted using two or more varactor elements having different sizes, and a Q-factor may be improved by adding an RC circuit. Each of the varactor elements is set to one of an accumulation mode and a depletion mode according to a control signal, thereby significantly reducing an influence of variables or variability occurring in a manufacturing process.
While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.
Number | Date | Country | Kind |
---|---|---|---|
10-2021-0040437 | Mar 2021 | KR | national |
Number | Name | Date | Kind |
---|---|---|---|
6906596 | Kitamura et al. | Jun 2005 | B2 |
7129801 | Wu | Oct 2006 | B2 |
7183870 | Takagi | Feb 2007 | B2 |
7336134 | Janesch | Feb 2008 | B1 |
7449970 | Yu et al. | Nov 2008 | B2 |
8502614 | Nakamura | Aug 2013 | B2 |
8803616 | Zhang | Aug 2014 | B2 |
10270388 | Hoshino | Apr 2019 | B2 |
20030189466 | Kitamura | Oct 2003 | A1 |
20040150483 | Cho | Aug 2004 | A1 |
20040222838 | McCorquodale et al. | Nov 2004 | A1 |
20070040625 | Yu | Feb 2007 | A1 |
20070075791 | Dedieu | Apr 2007 | A1 |
20070103248 | Nakamura | May 2007 | A1 |
20070188244 | Waheed et al. | Aug 2007 | A1 |
20080136544 | Tang | Jun 2008 | A1 |
20100188158 | Ainspan et al. | Jul 2010 | A1 |
20100214715 | Thaller | Aug 2010 | A1 |
20120049913 | Tadjpour | Mar 2012 | A1 |
20130147566 | Voinigescu | Jun 2013 | A1 |
20180159471 | Zhang | Jun 2018 | A1 |
Number | Date | Country |
---|---|---|
101255465 | Apr 2013 | KR |
Number | Date | Country | |
---|---|---|---|
20220311382 A1 | Sep 2022 | US |