Claims
- 1. An impedance network, comprising:
at least one end terminal; a wiper terminal providing a tap position at a selected impedance value of the impedance network, selectable at a specified increment value, said wiper terminal selectable as an end terminal; a center impedance element; and a first plurality of impedance elements configured to provide a range of impedance values with less number of wiper switching elements than for an impedance network with impedance elements having a uniformly selected increment value, the first plurality of impedance elements connected in series in a mirrored configuration about the center impedance element.
- 2. The network of claim 1, further comprising:
at least first and second end impedance elements coupled between the at least one end terminal and the first plurality of impedance elements.
- 3. The network of claim 2, wherein the first and second end impedance elements are unit valued resistors.
- 4. The network of claim 1, wherein said first plurality of impedance elements includes a plurality of connection nodes which enables said first plurality of impedance elements to be connected in series.
- 5. The network of claim 4, wherein said first plurality of impedance elements includes a first plurality of wiper switching elements to selectively couple said plurality of connection nodes to the wiper terminal.
- 6. The network of claim 5, wherein said first plurality of wiper switching elements includes a plurality of transistors.
- 7. The network of claim 6, wherein on/off states of said plurality of transistors are in a mirrored configuration around the center impedance element.
- 8. The network of claim 6, wherein said plurality of transistors includes a plurality of field-effect transistors (FET).
- 9. The network of claim 1, wherein each impedance element of said first plurality of impedance elements includes a second plurality of impedance elements selectively connectable in parallel.
- 10. The network of claim 9, further comprising:
a second plurality of switching elements configured to selectively connect said second plurality of impedance elements in parallel.
- 11. The network of claim 10, wherein said second plurality of switching elements includes a plurality of transistors.
- 12. The network of claim 11, wherein said plurality of transistors includes a plurality of field-effect transistors (FET).
- 13. The network of claim 10, wherein said second plurality of impedance elements includes a pair of resistors of equal values, selectively connectable in parallel.
- 14. The network of claim 12, wherein said pair of resistors in different impedance elements of said first plurality of impedance elements are of unequal values.
- 15. The network of claim 14, wherein the value of the center impedance element is of equal value to the value of the pair of resistors in said second plurality of impedance elements on both sides of the center impedance element.
- 16. The network of claim 1, wherein the center impedance element and appropriate number of impedance elements adjacent to the center impedance element are configured to reduce resistance variation during switching from one tap position to another tap position.
- 17. The network of claim 16, wherein the center impedance element and appropriate number of impedance elements adjacent to the center impedance element are configured with at least two more impedance elements than the appropriate number.
- 18. The network of claim 17, wherein said at least two more impedance elements has impedance value less than that of the center impedance element and adjacent impedance elements, but with equal value.
- 19. An impedance network, comprising:
at least one end terminal; a wiper terminal providing a tap position at a selected impedance value of the impedance network, selectable at a specified increment value, said wiper terminal selectable as an end terminal; a center impedance element; and a first plurality of impedance elements configured to reduce resistance variation during switching from one tap position to another tap position, the first plurality of impedance elements connected in series in a mirrored configuration about the center impedance element.
- 20. The network of claim 19, wherein the center impedance element and appropriate number of impedance elements adjacent to the center impedance element are configured with at least two more impedance elements than the appropriate number.
- 21. The network of claim 20, wherein said at least two more impedance elements has impedance value less than that of the center impedance element and adjacent impedance elements, but with equal value.
- 22. A resistance network having end terminals and a wiper terminal, comprising:
a first set of switching elements; a first plurality of resistors selectively connectable in parallel with said first set of switching elements to form an equivalent resistive element where values of said first plurality of resistors are equal; a center resistor; a second plurality of resistors connected in series in a mirrored configuration about the center impedance element, each resistor of said second plurality of resistors including said equivalent resistive element, resistance values of different equivalent resistive elements in said second plurality of resistors is in a binary configuration with two middle equivalent resistive elements having an equal value with the value of the center resistor; and a second set of switching elements to couple nodes of said second plurality of resistors to the wiper terminal.
- 23. The network of claim 22, further comprising:
at least first and second end resistors coupled to the end terminals.
- 24. The network of claim 23, wherein the at least first and second end resistors are unit-valued resistors.
- 25. The network of claim 22, wherein said first set of switching elements includes a plurality of transistors.
- 26. The network of claim 25, wherein said plurality of transistors includes a plurality of field-effect transistors (FET).
- 27. A method for configuring an impedance network, comprising:
first configuring a first plurality of resistors selectively connectable in parallel; connecting a second plurality of resistive elements in series, where each resistive element includes equivalent resistance formed by the first plurality of resistors; providing a center resistor; second configuring said second plurality of resistive elements into a mirrored configuration with respect to the center resistor; and selectively connecting nodes of said second plurality of resistive elements to a wiper terminal of the impedance network.
- 28. The method of claim 27, further comprising:
providing a pair of unit-sized resistors, one at each end of the second plurality of resistive elements.
- 29. The method of claim 27, wherein providing the center resistor includes configuring the value of the center resistor that is of equal value to the resistance of said second plurality of resistive elements on both sides of the center resistor.
- 30. The method of claim 27, further comprising:
selectively connecting said first plurality of resistors in parallel with a plurality of switching elements.
- 31. The method of claim 27, wherein said first configuring includes providing resistors of equal value.
- 32. The method of claim 27, wherein said second configuring includes providing resistors of different values to different resistive elements of the second plurality of resistive elements.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 09/989,874, filed Nov. 20, 2001 and entitled “Variable Impedance Network for an Integrated Circuit” and commonly assigned to the assignee of the present invention.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09989874 |
Nov 2001 |
US |
Child |
10102117 |
Mar 2002 |
US |