The United States Government has rights to use this invention pursuant to subcontract B338314 issued by the University of California, which operates Lawrence Livermore National Laboratory for the United States Department of Energy under Contract No. W-7405-ENG-48.
Number | Name | Date | Kind |
---|---|---|---|
4375051 | Theall | Feb 1983 | A |
4477713 | Cook et al. | Oct 1984 | A |
4514749 | Shoji | Apr 1985 | A |
4523310 | Brown et al. | Jun 1985 | A |
4587445 | Kanuma | May 1986 | A |
4823184 | Belmares-Sarabia et al. | Apr 1989 | A |
4896272 | Kurosawa | Jan 1990 | A |
4926066 | Maini et al. | May 1990 | A |
5194765 | Dunlop et al. | Mar 1993 | A |
5295132 | Hashimoto et al. | Mar 1994 | A |
5315175 | Langner | May 1994 | A |
5394528 | Kobayashi et al. | Feb 1995 | A |
5416606 | Katayama et al. | May 1995 | A |
5481567 | Betts et al. | Jan 1996 | A |
5490252 | Macera et al. | Feb 1996 | A |
5502733 | Kishi et al. | Mar 1996 | A |
5506953 | Dao | Apr 1996 | A |
5521836 | Hartong et al. | May 1996 | A |
5535223 | Horstmann et al. | Jul 1996 | A |
5544203 | Casasanta et al. | Aug 1996 | A |
5555188 | Chakradhar | Sep 1996 | A |
5603056 | Totani | Feb 1997 | A |
5604450 | Borkar et al. | Feb 1997 | A |
5617537 | Yamada et al. | Apr 1997 | A |
5623611 | Matsukawa et al. | Apr 1997 | A |
5631611 | Luu | May 1997 | A |
5657346 | Lordi et al. | Aug 1997 | A |
5682512 | Tetrick | Oct 1997 | A |
5748547 | Shau | May 1998 | A |
5757658 | Rodman et al. | May 1998 | A |
5778308 | Sroka et al. | Jul 1998 | A |
5778429 | Sukegawa et al. | Jul 1998 | A |
5784706 | Oberlin et al. | Jul 1998 | A |
5787268 | Sugiyama et al. | Jul 1998 | A |
5793259 | Chengson | Aug 1998 | A |
5811997 | Chengson et al. | Sep 1998 | A |
5828833 | Belville et al. | Oct 1998 | A |
5844954 | Casasanta et al. | Dec 1998 | A |
5847592 | Gleim et al. | Dec 1998 | A |
5898729 | Boezen et al. | Apr 1999 | A |
5910898 | Johannsen | Jun 1999 | A |
5915104 | Miller | Jun 1999 | A |
5929717 | Richardson et al. | Jul 1999 | A |
5978953 | Olarig | Nov 1999 | A |
6005895 | Perino et al. | Dec 1999 | A |
6016553 | Schneider et al. | Jan 2000 | A |
6272651 | Chin et al. | Aug 2001 | B1 |
6310815 | Yamagata et al. | Oct 2001 | B1 |
6363502 | Jeddeloh | Mar 2002 | B1 |
6412056 | Gharachorloo et al. | Jun 2002 | B1 |
6487685 | Fiske et al. | Nov 2002 | B1 |
6564269 | Martin | May 2003 | B1 |
Entry |
---|
Lattice Semiconductor Corporation, http://www.latticesemi.com,(2002),7 pgs. |
“Dynamic Datapath Selection for Unpredictable Transger Starts”, IBM Technical Disclosure Bulletin, TBA-ACC-NO: NA9402589, Issue No:2A, Cross Reference: 0018-8689-37-2A-589,(1994),589-592. |
“Dynamic Switch to Data Slow Mode on a Memory Card”, IBM Technical Disclosure Bulletin, 37, NA9402637,(1994),321-322. |
“Low Power Quad Differential Line Driver with Cut-Off”, National Semiconductor, F100K ECL 300 Series Databook and Design Guide, pp. 2-54—2-60. (1992). |
“Memory Card Data Fastpath”, IBM Technical Disclosure Bulletin, 37, TDB-ACC-NO: NA9402637, Issue No: 2A, Cross Reference: 0018-8689-37-2A-637,(1994),637-638. |
“The SA27 library includes programmable delay elements DELAYMUXO and DELAYMUXN. How are these cells used?”, IBM Delaymuxn Book, (Feb. 1999),pp.1-6. |
Brewer, Kevan , “Re: Memory mapped registers”, (Online): comp.arch.embedded, (May 2, 1996). |
Djordjevic, A. R., et al., “Time Domain Response of Multiconductor Transmission Lines”, Proceedings of the IEEE, 75(6), (Jun. 1987),743-64. |
Gjessing, et al., “Performance of the RamLink Memory Architecture”, Proceedings HICSS'94, (1994), 154-162. |
Gjessing, Stein , et al., “RamLink: A High-BandwidthPoint-to-Point Memory Architecture”, Proceeding CompCon, (1992),328/331. |
IEEE STD, “IEEE Standard for High-Bandwidth Memory Interface Based on Scalable Coherent Interface(SCI) Signaling Technology (RAMLink)”, IEEE Std. 1596.4-1996, (1996), 1-91. |
Im, G., et al., “Bandwidth-Efficient Digital Transmission over Unshielded Twisted-Pair Wiring”, IEEE Journal on Selected Areas in Communications, 13(9), (Dec. 1995) 1643-1655. |
Mooney, Randy , et al., “A 900 Mb/s Bidirectional Signaling Scheme”, IEEE Journal of Solid-State Circuits, 30(12), (Dec. 1995), 1538-1543. |
Rao, A. , “Memory mapped registers”, new://comp.arch.ambedded, (Apr. 27, 1996). |
Takahashi, T. , et al., “110GB/s Simultaneous Bi-Directional Transceiver Logic Synchronized with a System Clock”, IEEE International Solid-State Circuits Conference, (1999), 176-177. |