Claims
- 1. A signal processing system for converting a variable frequency input signal to an interpolated signal at a fixed sampling frequency, comprising:
a recipient clock providing a recipient clock signal at a recipient clock frequency; a numerically controlled oscillator responsive to a frequency control signal and the recipient clock signal for providing a second clock signal at a fixed second clock frequency representing baud rate of said variable frequency input signal, and a phase offset signal representing an offset in phase between the recipient clock signal and the second clock signal, and an interpolator that offsets a pair of variable frequency input signals in accordance with the phase offset signal to provide the interpolated signal at the fixed sampling frequency.
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of allowed application Ser. No. 09/570,238 filed May 12, 2000, which is a continuation of U.S. Pat. No. 6,144,712, issued Nov. 7, 2000. The priority of this patent is hereby claimed under 35 U.S.C. § 120.
[0002] This application contains subject matter that is related to U.S. Pat. No. 6,421,396, issued Jul. 16, 2002.
Continuations (2)
|
Number |
Date |
Country |
Parent |
09570238 |
May 2000 |
US |
Child |
10272759 |
Oct 2002 |
US |
Parent |
08948101 |
Oct 1997 |
US |
Child |
09570238 |
May 2000 |
US |