Patent Application
20080054943
The present invention may be understood, and its numerous objects, features and advantages obtained, when the following detailed description is considered in conjunction with the following drawings, in which:
A variable switching point circuit is described in which the threshold voltage is lowered for both rising and falling edge input voltages by changing the P/N ratio of the circuit based on the delayed output state of the circuit. While described with reference to an example inverter circuit, it will be appreciated that various embodiments of the present invention may be implemented with other switching circuits, including but not limited to logic gate circuits, operational amplifier circuits or other circuits whose output depends on the relationship between the input and a threshold voltage. In selected embodiments, the variable switching point inverter is constructed from a first inverter stage coupled in parallel to a second inverter stage having extra PMOS and NMOS transistors connected between respective reference voltages and the output node, where the extra PMOS and NMOS transistors are controlled by the delayed output signal from the first inverter stage. By using a delayed feed back signal to control the extra PMOS and NMOS gates, the threshold voltages of the first inverter stage are altered.
Various illustrative embodiments of the present invention will now be described in detail with reference to the accompanying figures. While various details are set forth in the following description, it will be appreciated that the present invention may be practiced without these specific details, and that numerous implementation-specific decisions may be made to the invention described herein to achieve the device designer's specific goals, such as compliance with process technology or design-related constraints, which will vary from one implementation to another. While such a development effort might be complex and time-consuming, it would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. For example, selected aspects are shown in simplified schematic diagram form, rather than in detail, in order to avoid limiting or obscuring the present invention. Such descriptions and representations are used by those skilled in the art to describe and convey the substance of their work to others skilled in the art.
The first pair of the complementary devices 35, 36 in the second stage 32 are switched ON depending on the level of the VIN signal, and hence the feedback control signal 40, such that they add to the respective input stage inverter devices 33, 34 only one at time. For example, if PMOS device 37 is ON in response to the delayed feedback control signal 40 being LOW, the effective transconductance ratio resulting from PMOS devices 33, 35, 37 and NMOS device 34 being ON provides a higher switch or trip point. This result, in effect, is the addition of a PMOS drive while the NMOS drive (which would be provided by NMOS device 36) is disconnected, and in this circuit, the high-to-low transitions are faster, but the low-to-high transitions are slower. On the other hand, if the NMOS device 38 is ON in response to the delayed feedback control signal 40 being HIGH, the effective transconductance ratio resulting from NMOS devices 34, 36, 38 and PMOS device 33 being ON provides a lower switch or trip point. The resulting effect is to add an NMOS drive while the PMOS drive (which would be provided by PMOS device 35) is disconnected, and in this circuit, the voltage input low-to-high transitions are faster, but the voltage input high-to-low transitions are slower. In this way, the extra PMOS device 37 and NMOS device 38 dynamically alter the threshold voltage of the inverter by changing the ratio of PMOS and NMOS devices.
The operation of the variable switching point inverter circuit 30 is illustrated with the positive hysteresis transfer curve 41 shown in
Once tripped, the output voltage VOUT goes LOW, causing the delayed feedback control signal 40 to go LOW which turns NMOS device 38 OFF and turns PMOS device 37 ON, thereby raising the high-to-low switching point voltage (VSPL) for subsequent high-to-low input voltage transitions. As a result, when the input voltage VIN again goes LOW at the high-to-low transition (indicated at curve 43), the trip point VSPL is set by the transconductance ratio of the activated PMOS devices 33, 35, 37 and NMOS device 34 so that the high-to-low transitions are faster. By lowering or raising the switching point voltages for input rising edge transition or falling edge transition with respect to the midpoint, the variable switching point inverter circuit 30 provides a positive hysteresis so that the inverter circuit 30 is triggered when the rising input signal crosses the lowered switch point VSPH or when the falling input signal crosses the raised switch point VSPL, such as illustrated in
The relative values of the low-to-high switch point VSPH and high-to-low switch point VSPL are shown in
As the input signal 45 increases (from LOW to HIGH) above the trip point VSPL, the inverter output 49 remains unchanged, but as the input signal 45 decreases (from HIGH to LOW) below the trip point VSPL (as indicated at node 47), the inverter output 49 changes from LOW to HIGH, again doing so more rapidly than with a conventional CMOS inverter because the extra PMOS drive devices (e.g., PMOS 35 and PMOS 37) are pulling the output voltage to VDD for so long as the delay buffer circuit 39 prevents the feedback control signal 40 from turning OFF the PMOS device 37. Thus, the trip point VSPL for the inverter circuit changes since it is now set by the transconductance ratio of the activated PMOS devices 33, 35, 37 and NMOS device 34 until the inverter output signal propagates through the delay buffer circuit. Finally, while the inverter output 49 remains unchanged as the input signal 45 decreases (from HIGH to LOW) below the trip point VSPH, the inverter output 49 changes from HIGH to LOW as the input signal 45 increases (from LOW to HIGH) above the trip point VSPH (as indicated at node 48).
As will be appreciated, other variable switching point inverter circuit designs may be used to alter the switching point of the inverter and obtain lower threshold voltages for both rising and falling edges of the input signal. For example,
In one form, there is provided herein a variable switching point inverter circuit in which a first inverter stage (e.g., a CMOS inverter) receives an input signal at an input node and generates an output signal at an output node. In addition, inverter includes a switching point voltage control stage coupled to the output node to provide a positive hysteresis to the first inverter stage. The switching point voltage control stage also includes a delay circuit that is connected to the output node for generating the delayed output signal that controls the switching point voltage control stage, which in turn dynamically controls a switching point voltage of the first inverter stage. In various embodiments, the switching point voltage control stage may be constructed with a second CMOS inverter stage which is coupled in parallel to the first inverter stage to receive an input signal at a shared input node and to generate an output signal at a shared output node, and which is further coupled in series with additional PMOS and NMOS devices that are controlled by the delayed output signal. For example, by including a first PMOS device that is source-drain connected between the second CMOS inverter stage and a first reference voltage and a first NMOS device that is source-drain connected between the second CMOS inverter stage and a second reference voltage, the delay circuit may be implemented as one or more series-connected buffers to generate a feedback control signal by delaying the output signal, where the feedback control signal is applied to the gate electrodes of the first PMOS and NMOS devices. Alternatively, by including a first NMOS device that is source-drain connected between the second CMOS inverter stage and a first reference voltage and a first PMOS device that is source-drain connected between the second CMOS inverter stage and a second reference voltage, the delay circuit may be implemented as one or more series-connected inverter circuits to generate an feedback control signal by delaying and inverting the output signal, where the feedback control signal is applied to the gate electrodes of the first PMOS and NMOS devices. In this way, the switching point voltage control stage reduces threshold voltage values in the first inverter stage for both low-to-high and high-to-low input signal transitions. In effect, the switching point voltage control stage reduces the threshold voltage of the first inverter stage by adjusting the inverter trip point, depending on whether the input transitions are high-to-low or low-to-high.
In another form, there is provided herein an integrated circuit device having a switching circuit (such as an inverter or an operational amplifier) for generating an output signal in response to receiving an input signal. The switching circuit's operational behavior is defined with reference to a first transfer curve (having a first trip point for rising edge input signal transitions) and a second transfer curve (having a second trip point for falling edge input signal transitions), where the first trip point is less than the second trip point. Together, the first and second transfer curves define a positive hysteresis for the switching circuit. In a selected embodiment, the switching circuit includes a conventional CMOS inverter stage (formed from series-coupled NMOS and PMOS devices), a PMOS drive stage and an NMOS drive stage. The PMOS drive stage is coupled in parallel to the PMOS device in the inverter for selectively coupling the inverter's output node to a first reference voltage (e.g., VDD) during falling edge input signal transitions, while the NMOS drive stage is coupled in parallel to the NMOS device in the inverter for selectively coupling the inverter's output node to the second reference voltage (e.g., VSS) during rising edge input signal transitions. The PMOS drive stage may include a feedback delay circuit connected to the inverter's output node for generating a feedback control signal by delaying the output signal, where the feedback control signal is applied to the gate of a second PMOS device, which in turn is source-drain coupled between the first reference voltage and an additional PMOS drive device which has its source electrode connected to the output node and its gate electrode connected to the inverter's input node. Alternatively, the PMOS drive stage may include a feedback delay circuit connected to the inverter's output node for generating a feedback control signal by delaying and inverting the output signal, where the feedback control signal is applied to the gate of a second NMOS device, which in turn is source-drain coupled between the first reference voltage and an additional PMOS drive device which has its source electrode connected to the output node and its gate electrode connected to the inverter's input node. As will be appreciated, the NMOS drive stage can be implemented with a similar design so long as the device types are reversed as appropriate.
In yet another form, there is disclosed an integrated circuit switching device which includes a first CMOS inverter for receiving and switching an input signal to generate an output signal, and which also includes a drive circuit coupled between the first CMOS inverter and the inverter's output for selectively driving the output node only during rising and falling edge input signal transitions in response to a delayed output signal, thereby providing a positive hysteresis to the first CMOS inverter stage.
Although the described exemplary embodiments disclosed herein are directed to various examples of a variable switching point inverter circuits and methods for using same, the present invention is not necessarily limited to the example embodiments. For example, various embodiments of the variable switching point inverter may be used to form non-inverting buffer circuits by including an additional inverter at the output node. In addition, the variable switching point inverter can advantageously be used as a receiver amplifier for slow edge signals, as a receiver amplifier for clock distribution H-tree and as a receiver for noise-free signals, among other possible applications. Thus, the particular embodiments disclosed above are illustrative only and should not be taken as limitations upon the present invention, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Accordingly, the foregoing description is not intended to limit the invention to the particular form set forth, but on the contrary, is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims so that those skilled in the art should understand that they can make various changes, substitutions and alterations without departing from the spirit and scope of the invention in its broadest form.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
