Patent Application
20160099678
1. Field
The present disclosure relates generally to electronic circuits, and more particularly, to methods and apparatuses for calibrating voltage-controlled capacitive elements, voltage-controlled oscillators, and phase-locked loops.
2. Background
A wireless device (e.g., a cellular phone or a smartphone) may transmit and receive data for two-way communication with a wireless communication system. The wireless device may include a transmitter for data transmission and a receiver for data reception. For data transmission, the transmitter may modulate a local oscillator (LO) signal with data to obtain a modulated radio frequency (RF) signal, amplify the modulated RF signal to obtain an output RF signal having the desired output power level, and transmit the output RF signal via an antenna to a remote device. For data reception, the receiver may obtain a received RF signal via the antenna, amplify and downconvert the received RF signal with an LO signal, and process the downconverted signal to recover data sent by the remote device.
Voltage-controlled oscillators (VCOs) are often used to generate the LO signals. A VCO is an oscillator whose frequency is controlled by a voltage input. A type of the VCO utilizes a voltage-controlled capacitive element (such as a varactor) in an inductor-capacitor (LC) tank to tune and generate a target oscillating frequency. A phase-locked loop (PLL) may incorporate the VCO and adjusts the input voltage of the VCO to tune the transmitter or receiver. The PLL is generally implemented with a phase detector that compares the phase of the VCO output with the phase of a reference signal and adjusts the voltage input to the VCO to keep the phases aligned. The ability of the PLL to accurately maintain the phase alignment between the reference signals depends on the VCO generating accurate oscillating frequencies. A common challenge among skilled artisans in designing a wireless device transmitters and receivers is to achieve the accurate VCO oscillating frequencies.
Another application of a PLL incorporating a VCO is in a serializer/deserializer or SerDes interface. In one example, a SerDes transmitter converts parallel data into a bitstream, and each such bitstream is transmitted serially via a pair of differential transmission lines to a SerDes receiver. The parallel-to-serial conversion and the transmission of the bitstream may be synchronized with a bit-rate clock generated by a PLL (incorporating a VCO) based on a reference clock. The reference clock is likewise provided to the SerDes receiver. The SerDes receiver may utilize a PLL to generate a recover clock (which may have a same frequency as the bit-rate clock) from the received reference clock, and clock the input bitsteam or bitstreams using the recover clock.
Aspects of a VCO apparatus are provided. The apparatus includes an inductor, a voltage-controlled capacitive element configured to operate with the inductor to generate an oscillating signal, a voltage supply configured to provide a plurality of voltages to the voltage-controlled capacitive element in a calibration mode, and a control circuit configured to store frequency information indicating frequencies of the oscillating signal in response to the plurality of voltages being provided to the voltage-controlled capacitive element.
Aspects of a PLL apparatus are provided. The PLL apparatus includes means for selecting, in an open loop configuration, a capacitance of a capacitor based on a target frequency and means for selecting, in a closed loop configuration, an operation voltage of a voltage-controlled capacitive element based on the capacitance of the capacitor.
Aspects of a method for operating a VCO are provided. The method includes providing a plurality of voltages from a first source to a voltage-controlled capacitive element, storing frequency information indicating frequencies of an output signal generated in response to the plurality of voltages, selecting an operation voltage for the voltage-controlled capacitive element based on the stored frequency information of the output signal, and providing the operation voltage from a second source to the voltage-controlled capacitive element.
Aspects of a method for operating a PLL are provided. The method includes selecting, in an open loop configuration, a capacitance of a capacitor based on a target frequency and selecting, in a closed loop configuration, an operation voltage of a voltage-controlled capacitive element based on the capacitance of the capacitor.
It is understood that other aspects of apparatus, circuits and methods will become readily apparent to those skilled in the art from the following detailed description, wherein various aspects of apparatus, circuits and methods are shown and described by way of illustration. As will be realized, these aspects may be implemented in other and different forms and its several details are capable of modification in various other respects. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.
Various aspects of apparatus, circuits and methods will now be presented in the detailed description by way of example, and not by way of limitation, with reference to the accompanying drawings, wherein:
The detailed description set forth below in connection with the appended drawings is intended as a description of various exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention. Acronyms and other descriptive terminology may be used merely for convenience and clarity and are not intended to limit the scope of the invention.
The word “exemplary” is used herein to mean serving as an example, instance, or illustration. Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiment” of an apparatus, circuit or method does not require that all embodiments of the invention include the described components, structure, features, functionality, processes, advantages, benefits, or modes of operation.
The terms “connected,” “coupled,” or any variant thereof, mean any connection or coupling, either direct or indirect, between two or more elements, and can encompass the presence of one or more intermediate elements between two elements that are “connected” or “coupled” together. The coupling or connection between the elements can be physical, logical, or a combination thereof. As used herein, two elements can be considered to be “connected” or “coupled” together by the use of one or more wires, cables and/or printed electrical connections, as well as by the use of electromagnetic energy, such as electromagnetic energy having wavelengths in the radio frequency region, the microwave region and the optical (both visible and invisible) region, as several non-limiting and non-exhaustive examples.
Any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.
As used herein, the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Various aspects of PLLs and VCOs for, e.g., tuning the frequency of transmitters and receivers in wireless devices or a SerDes interface will now be presented. However, as those skilled in the art will readily appreciate, such aspects may be extended to other circuit configurations and devices. By way of example, various aspects of the present invention may be used for signal recovery in a noisy channel, frequency synthesis, clock distribution, and other suitable uses that require PLL, VCO, or similar circuit. Accordingly, all references to a specific application for a PLL or a VCO, or any component, structure, feature, functionality, or process within a PLL are intended only to illustrate exemplary aspects of a PLL with the understanding that such aspects may have a wide differential of applications.
Various embodiments of PLLs may be used in SerDes interfaces of an electronic device.
Various embodiments of a PLL may be used in a wireless device, such as a mobile phone, personal digital assistant (PDA), desktop computer, laptop computer, palm-sized computer, tablet computer, set-top box, navigation device, work station, game console, media player, or any other suitable device.
The wireless device 100 includes a baseband processor 102, a wireless transceiver 104, and an antenna 106. The wireless transceiver 104 may employ various aspects of phase-locked loops presented throughout this disclosure to generate one or more LO signals to support both a transmitting and receiving function. The wireless transceiver 104 performs the transmitting function by modulating one or more carrier signals with a data generated by the baseband processor 102 for transmission over a wireless channel through the antenna 106. The wireless transceiver 104 performs a receiving function by demodulating one or more carrier signals received from the wireless channel through the antenna 106 to recover data for further processing by the baseband processor 102. The baseband processor 102 provides the basic protocol stack required to support wireless communications, including for example, a physical layer for transmitting and receiving data in accordance with the physical and electrical interface to the wireless channel, a data link layer for managing access to the wireless channel, a network layer for managing source to destination data transfer, a transport layer for managing transparent transfer of data between end users, and any other layers necessary or desirable for establishing or supporting a connection to a network through the wireless channel.
In the transmit path, the baseband processor 102 (see
In the receive path, the antenna 106 may receive signals transmitted by a remote device. The received RF signal may be routed through the duplexer 260 to the receiver 250. Within the receiver 250, the received RF signal is amplified by a low noise amplifier (LNA) 252 and filtered by a filter 254 and to obtain an input RF signal. A mixer 256 receive the input RF signal and an LO signal from a RX local oscillator 258. The mixer 256 mixes the input RF signal with the LO signal to provide a downconverted signal. The downconverted signal is amplified by an amplifier 261 to obtain an amplified downconverted signal. A filter 262 is used to filter the amplified downconverted signal to remove images caused by the frequency mixing. The signal from the filter 262 is provided to an analog-to-digital converter (ADC) 264. The ADC 264 converts the signal to a digital output signal. The digital output signal may be provided to the baseband processor 102 (see
The conditioning of the signals in the transmitter 200 and the receiver 250 may be performed by one or more stages of amplifiers, filters, mixers, etc. These circuits may be arranged differently from the configuration shown in
Various embodiments of PLLs may be used to support transmitter and receiver functions. In one exemplary embodiment, the PLLs may be implemented with a VCO that provides the oscillating signal to the transmitter and/or receiver. An example of a VCO is a positive feedback amplifier that has a tuned resonator in the feedback loop. Oscillations occur at the resonant frequency, which can be tuned by the PLL. The PLL may be implemented with a phase detector that compares the phase of the VCO output with the phase of a reference signal and tunes the resonator of the VCO to keep the phases aligned.
The phase detector 302 compares the reference signal to the feedback signal from the fractional-N frequency divider 310 and activates the charge pump 304 based on the phase difference between the two signals. The phase detector 302 operates in a phase detection mode and a phase locked state. For this reason, the phase detector is sometimes referred to as a phase/frequency detector (PFD). For the purposes of this disclosure, the term “phase detector” shall be construed broadly to include a component capable of detecting a difference in phase and/or frequency of two input signals.
The phase detector 302 operates in a phase detection mode, in which the duty cycles of the UP and DOWN signals are varied based on the phase error measured by the phase detector 302. As a result, the charge pump 304 is activated for only a portion of the time, which is proportional to the phase difference between the two signals. The loop filter 306 accumulates a charge that produces a filtered control voltage (e.g., VCTRL) which adjusts the frequency of the VCO output signal until the phase difference reaches zero. Once this occurs, the phase detector 302 enters the phase locked state. In this state, the duty cycles of the UP and DOWN signals are substantially equal, and therefore, no net charge is injected into the loop filter 306. The control voltage input to the VCO 308 remains constant, which ensures that the VCO output signal remains at a constant frequency. The loop filter 306 may be active or passive, and the charge pump 304 may also be implemented in several ways. These circuit elements may be implemented in accordance with the knowledge in the art.
The VCO 308 receives the control voltage VCTRL and adjusts the oscillating frequency of the differential outputs CLKP and CLKN accordingly. The frequency adjustment results from adjusting the inductance-capacitance (LC) constant of the LC tank 402. In one example, the LC constant of the LC tank 402 is adjusted based on the voltage level of the control voltage VCTRL. The LC tank 402 includes inductors 410 and 420, which account for the inductance portion of the LC constant. The inductors 410 and 420 are connected to the power source 408 at node N2. The inductor 410 is connected to the output CLKP, and the inductor 420 is connected to the CLKN. The capacitors of the LC tank 402 include tunable capacitors 414 and 424. The tunable capacitor 414 is connected to the output CLKP, and the tunable capacitor 424 is connected to the output CLKN. In one example, the tunable capacitors 414 and 424 may be capacitor banks selected by CCOARSE CONTROL signals. A capacitor bank may include a plurality of capacitors selectively connected by the control signals, as is known in the art. In one implementation, the tunable capacitors 414 and 424 are tuned for coarse capacitance adjustments (as compared to the adjustments of the varactors 412 and 422).
The LC tank 402 includes voltage-controlled capacitive elements, such as the varactors 412 and 422. The varactors 412 and 422 receive the control voltage VCTRL at node N1. The varactor 412 is connected to the output CLKP, and the varactor 422 is connected to the output CLKN. An example of a varactor includes a diode with a variable depletion region. The input voltage voltage-controlled capacitive element varies the depletion region and therefore, the capacitance of the device. In one implementation, the varactors 412 and 422 are tuned by the control the voltage VCTRL at node N1 for fine capacitance adjustments (as compared to the adjustments by the changing the selections on the tunable capacitors 414 and 424). The varactors 412 and 422 operate with the inductors 410, 420 and the tunable capacitors 414 and 424 to output the CLKP and CLKN at a given frequency.
Various embodiments of methods and apparatus for PLLs and VCOs to calibrate the varactors are provided. The PLLs and VCOs may calibrate and adjust the bias points for the varactors to compensate for process and technology change. Moreover, the responses of the varactors are not static; the responses may be operational frequency dependent. In one example, since the tunable capacitors 414 and 424 are tuned for coarser capacitance adjustments by the CCOARSE CONTROL signals, the responses of the varactors (and therefore the oscillating frequency of the VCO 308) may depend on the settings of the CCOARSE CONTROL signals.
The VCO 600 further includes a programmable pull-down source 606, the pull-down capacity of which may be controlled by digital SWING CODE signals. The VCO 600 further includes a programmable power source 608, the capacity of which may be controlled by digital VOP CODE signals. In the operation mode, the loop filter 306 is connected to the control voltage VCTRL input at the node N1. The power source 608 is connected to the common voltage node N2. In one implementation, the operation voltage of the varactors 412 and 422 may be provided by the power source 608 (with respect to the voltage provided by the charge pump 304). In this fashion, the calibration of the VCO 600 is isolated from the charge pump 304 and loop filter 306. In one implementation, the charge pump 304 and the loop filter 306 are not used in the calibration mode, and do not need to be configured to provide the operation voltage of the varactors 412 and 422 determined in the calibration mode. In one implementation, the selection of the operation voltage (such as the bias voltage VBIAS) for the varactors 412 and 422 needs not alter a configuration of the charge pump 304 and the loop filter 306.
A memory 691 is provided to store a result of calibrating the VCO 600. The memory may be implemented with a register, a non-volatile memory, or other types of memories known in the art. In one example, the memory 691 is configured to store frequency information indicating frequencies of the outputs CLKP and CLN generated in response to the plurality of voltages provided to the varactors 412 and 422.
A control circuit 690 may be configured to control the various features of the VCO 600 presented above. The control circuit 690 may be implemented in hardware/circuit, software, or combination thereof in accordance with the knowledge of persons of ordinary skill in the art. For example, the modules may include logic gates to perform the functions described herein, processor(s) performing those functions, logic gates generating the signals for the functions described herein, or combinations thereof. In one example, the control circuit 690 may refer to the logic gates generating the CALIBRATION CODE signals, the VOP CODE signals, the CCOARSE CONTROL signals, and the SWING CODE signals. The control circuit 690 may further be configured to provide the switch 630 control signal that controls the settings (A or B) of the switch 630.
An example of the operations of the VCO 600 and a PLL incorporating the VCO 600 are presented below. The VCO 600 may be calibrated in a calibration mode to generate the frequency information. In the calibration mode, the PLL incorporating the VCO 600 may be placed in an open loop configuration. For example, the PLL 300 may incorporate the VCO 600, which includes varactors 412 and 422. The PLL 300 may be placed in an open loop configuration when the feedback signal is disconnected or disabled from the phase detector 302.
In the calibration mode, the control circuit 690 may be configured to set each of the tunable capacitors 414 and 424 to a plurality of capacitances by varying the CCOARSE CONTROL signals. For each of the capacitance settings of the tunable capacitors 414 and 424, the control circuit 690 may be configured to provide a plurality of voltages from the calibration voltage source 632 to the varactors 412 and 422.
Examples of providing the plurality of voltages from the calibration voltage source 632 to the varactors 412 and 422 are presented below. The control circuit 690 may be configured to switch the switch 630 from the setting A to the Setting B, thereby disconnecting the charge pump 304 and the loop filter 306 to the varactors 412 and 422. This step may also place the PLL incorporating the VCO 600 in the open loop configuration, as the feedback to the VCO 600 is disconnected. With the switch 630 at setting B, the calibration voltage source 632 is connected to the varactors 412 and 422. For each of the capacitance settings of the tunable capacitors 414 and 424, the control circuit may be configured to provide a plurality of voltages to the varactors 412 and 422 by arranging the power source 608 to output a reference voltage to the node N2. This step may be implemented by using the VOP CODE signals. In this fashion, the plurality of voltages may be provided to the varactors 412 and 422 via the node N1 with the node N2 serving as a reference.
With the node N2 set to the reference voltage (e.g., ground), for each capacitance setting of the tunable capacitors 414 and 424, the control circuit 690 may provide the plurality of voltage to the varactors 412 and 422 (e.g., providing the voltages to the node N1) by varying the CALIBRATION CODE signals. The VCO 600 outputs CLKP and CLKN oscillate in varying frequencies in response to the plurality of voltages provided to the varactors 412 and 422. A measuring circuit 692 measures the frequencies of the outputs CLKP and CLKN generated in response to the plurality of voltages provided to the varactors 412 and 422 and provides the frequency information to a control circuit 690. The control circuit 690 may be configured to store in the memory 619 the frequency information indicating the frequencies of the output nodes CLKP and CLKN generated in response to the plurality of voltages provided to the varactors 412 and 422.
In one configuration, the stored frequency information may reflect the graph of
In another aspect of the VCO 600, the control circuit 690 may be configured to maximize an amplitude swing of the outputs CLKP and CLKN. In one example, the control circuit 690 may be configured to generate the SWING CODE signals corresponding to the maximum amplitude swing for the outputs CLKP and CLKN for each of the plurality of voltages provided to the varactors 412 and 422. In the calibration mode, for each of the plurality of voltages provided to the varactors 412 and 422, the control circuit 690 may sweep the SWING CODE signals to obtain a set of the SWING CODE signals that produces the maximum amplitude swing for the outputs CLKP and CLKN. The frequency information stored in the memory 691 may store the set of the SWING CODE signals that produces the maximum amplitude swing with respect to each of the plurality of voltages provided to the varactors 412 and 422.
In the calibration mode (e.g., the PLL incorporating the VCO 600 is in the open loop configuration), the control circuit 690 may set the calibration voltage source 632 to output a reference voltage (e.g., ground) to node N1 of the varactors 412 and 422. The control circuit 690 may sweep the VOP CODE signals and generate, as a response, CLKP and CLKN oscillating at various frequencies. This set of frequencies and VOP CODE signals relationship may be stored in the in the memory 691 as part of the frequency information.
The control circuit 690 may be configured to select the operation voltage for the varactors 412 and 422 based on the stored frequency information using various factors. In one example, the operation voltage may be selected for a maximum frequency swing produced by a change in the operation voltage of the varactors 412 and 422. For example, if the response 504 is selected (by a setting of the CCOARSE CONTROL signals), the setting of the bias voltage VBIAS of the varactors 412 and 422 may determine a range (FMIN-FMAX) of the oscillating frequency of the VCO 308. In one example, the bias voltage VBIAS is a voltage at the center of the operation voltage range which allows for a maximum frequency swing of the output signal. Thus, the operation voltage for the varactors 412 and 422 may be selected to maximize a change in the frequencies of the output signal (e.g., outputs CLKP and CLKN) in response to a change in voltages of the varactors 412 and 422 (e.g., across the nodes N1 and N2). In one example, referring to
As shown in
In an operation mode (e.g., the PLL incorporating the VCO 600 is in a closed loop configuration), the selected operation voltage (e.g., VBIAS) may be provided to the varactors 412 and 422 by, e.g., the power source 608. To facilitate this feature, the control circuit 690 may be configured to generate the needed VOP CODE signal to instruct the power source 608 to provide the selected operation voltage. For example, as described above, the memory 691 may include the set of frequencies and VOP CODE signals relationship. The VOP CODE signal may be selected therefrom that matches best with the selected the operation voltage. For example, the VOP CODE signals-to-output frequencies relationship best matches the selected operation voltage and the associated frequency responses may be selected. The control circuit 690 may be configured to provide the selected operation voltage to the varactors 412 and 422 (at node N2) by providing the corresponding VOP CODE signals to the power source 608. In this fashion, the selected operation voltage may be provided as VBIAS to varactors 412 and 422 at node N2 by the power source 608.
At 702, a capacitor coupled to the voltage-controlled capacitive element is set to a plurality of capacitances in the open loop configuration. For example, the PLL 300 may incorporate the VCO 600, which includes varactors 412 and 422. The PLL 300 may be placed in an open loop configuration when the feedback signal is disconnected or disabled from the phase detector 302. In the calibration mode, the control circuit 690 may be configured to set the set each of the tunable capacitors 414 and 424 to a plurality of capacitances by varying the CCOARSE CONTROL signals. For each of the capacitance settings of the tunable capacitors 414 and 424, the control circuit 690 may be configured to provide a plurality of voltages from the calibration voltage source 632 to the varactors 412 and 422.
In one implementation, steps 704, 706, and 708 may be performed for each of the capacitance of step 702. At 704, a plurality of voltages is provided (e.g., from a first source) to the voltage-controlled capacitive element. For example, the control circuit 690 may be configured to switch the switch 630 from the setting A to the Setting B, thereby disconnecting the charge pump 304 and the loop filter 306 to the varactors 412 and 422. This step may also place the PLL incorporating the VCO 600 in the open loop configuration, as the feedback to the VCO 600 is disconnected. With the switch 630 at setting B, the calibration voltage source 632 is connected to the varactors 412 and 422. For each of the capacitance settings of the tunable capacitors 414 and 424, the control circuit may be configured to provide a plurality of voltages to the varactors 412 and 422 by arranging the power source 608 to output a reference voltage (e.g., ground) to the node N2. This step may be implemented by using the VOP CODE signals. In this fashion, the plurality of voltages may be provided to the varactors 412 and 422 via the node N1 with the node N2 serving as a reference.
With the node N2 set to the reference voltage (e.g., ground), for each capacitance setting of the tunable capacitors 414 and 424, the control circuit 690 may provide the plurality of voltage to the varactors 412 and 422 (e.g., providing the voltages to the node N1) by varying the CALIBRATION CODE signals. The VCO 600 outputs CLKP and CLKN oscillate in varying frequencies in response to the plurality of voltage provided to the varactors 412 and 422.
At 706, frequency information indicating frequencies of an output signal generated in response to the plurality of voltages is stored. For example, the control circuit 690 may be configured to store in the memory 619 the frequency information indicating the frequencies of the output nodes CLKP and CLKN generated in response to the plurality of voltages provided to the varactors 412 and 422. In one configuration, the stored frequency information may reflect the graph of
At 708, a swing of the output signal is determined based on swings of the output signal generated in response to the plurality of voltages. For example, the control circuit 690 may be configured to maximize an amplitude swing of the outputs CLKP and CLKN. In one example, the control circuit 690 may be configured to generate the SWING CODE signals corresponding to the maximum amplitude swing for the outputs CLKP and CLKN for each of the plurality of voltages provided to the varactors 412 and 422. In the calibration mode, for each of the plurality of voltages provided to the varactors 412 and 422, the control circuit 690 may sweep the SWING CODE signals to obtain a set of the SWING CODE signals that produces the maximum amplitude swing for the outputs CLKP and CLKN. The frequency information stored in the memory 691 may store the set of the SWING CODE signals that produces the maximum amplitude swing with respect to each of the plurality of voltages provided to the varactors 412 and 422.
At 710, an operation voltage for the voltage-controlled capacitive element is selected based on the stored frequency information of the output signal. For example, the control circuit 690 may be configured to select a bias voltage VBIAS for the varactors 412 and 422 and for the operation mode. In one implementation, the control circuit 690 may select the bias voltage VBIAS based on the maximizing changes of the oscillating frequency (Δf) vs. changes of the control voltage VCTRL (Δv)(e.g., maximize KVCO).
In one example, the operation voltage may be selected for a maximum frequency swing produced by a change in the operation voltage of the varactors 412 and 422. For example, if the response 504 is selected (by a setting of the CCOARSE CONTROL signals), the setting of the bias voltage VBIAS of the varactors 412 and 422 may determine a range (FMIN-FMAX) of the oscillating frequency of the VCO 308. In one example, the bias voltage VBIAS is a voltage at the center of the operation voltage range which allows for a maximum frequency swing of the output signal. Thus, the operation voltage for the varactors 412 and 422 may be selected to maximize a change in the frequencies of the output signal (e.g., outputs CLKP and CLKN) in response to a change in voltages of the varactors 412 and 422 (e.g., across the nodes N1 and N2). In one example, referring to
At 712, a capacitance of the capacitor is selected based on the stored frequency information. For example, a capacitance setting of the tunable capacitors 414 and 424 may be selected based on a target frequency and the frequency information stored in the memory 691. Moreover, the operation voltage for the varactors 412 and 422 may be selected based on the target frequency and the frequency information stored in the memory 691. The target frequency may be within the range FMIN-FMAX outputted by the selected capacitance setting of the tunable capacitors 414 and the selected operation voltage for the varactors 412 and 422. In one example, the selected operation voltage for the varactors 412 and 422 may be the bias voltage VBIAS, which is a voltage at the center of the operation voltage range (VMIN-VMAX) which allows for a maximum frequency swing of the output signals CLKP and CLKN.
At 716, the operation voltage is provided (e.g., from a second source) to the voltage-controlled capacitive element. For example, in an operation mode (e.g., the PLL incorporating the VCO 600 is in a closed loop configuration), the selected operation voltage may be provided to the varactors 412 and 422 by, e.g., the power source 608. As presented above, the frequency information stored in the memory 691 may include a setting of the power source (VOP CODE signals) that corresponds to the selected operation voltage. The control circuit 690 may be configured to provide the selected operation voltage to varactors 412 and 422 (at node N2) by providing the corresponding VOP CODE signals to the power source 608.
A voltage providing module 804 provides a plurality of voltages (e.g., from a first source) to a voltage-controlled capacitive element. Examples of the voltage providing module 804 are presented with
A frequency information storing module 806 provides storing of frequency information indicating frequencies of an output signal generated in response to the plurality of voltages. Examples of the frequency information storing module 806 are presented with
A swing determination module 808 provides for determining a swing of the output signal based on swings of the output signal generated in response to the plurality of voltages. Examples of the swing determination module 808 are presented with
A module for selecting operation voltage selection based on the stored information 810 selects the operation voltage based on, e.g., the frequency information stored in the memory 691. Examples of the module for selecting operation voltage selection based on the stored information 810 are presented with
A capacitance selection module 812 selects, in the closed loop configuration, a capacitance of the capacitor based on the stored frequency information. Examples of the capacitance selection module 812 are presented with
An operation voltage providing module 816 provides the selected operation voltage (e.g., from a second source) to the voltage-controlled capacitive element. Examples of the operation voltage providing module 816 are presented with
The modules may be one or more hardware components specifically configured to carry out the stated processes/algorithm, implemented by a processor configured to perform the stated processes/algorithm, stored within a computer-readable medium for implementation by a processor, or some combination thereof.
The control circuit 800 may include additional modules that perform each of the steps of the algorithm in the aforementioned flow chart of
The specific order or hierarchy of blocks in the method of operation described above is provided merely as an example. Based upon design preferences, the specific order or hierarchy of blocks in the method of operation may be re-arranged, amended, and/or modified. The accompanying method claims include various limitations related to a method of operation, but the recited limitations are not meant to be limited in any way by the specific order or hierarchy unless expressly stated in the claims.
The previous description is provided to enable any person skilled in the art to fully understand the full scope of the disclosure. Modifications to the various exemplary embodiments disclosed herein will be readily apparent to those skilled in the art. Thus, the claims should not be limited to the various aspects of the disclosure described herein, but shall be accorded the full scope consistent with the language of claims. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. §112(f) unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.”
