Patent Application
20080068092
The present invention may be further understood from the following description in conjunction with the appended drawing. In the drawing:
More particularly, a coarse frequency select stage F, a tuning gain control stage VC, and a variable transconductance output stage G (which includes circuitry like that of the oscillator 100 of
The frequency select stage F consists of binary weighted capacitors that are switched into the tank through NMOS switches. Coarse frequency control can be achieved in conventional fashion as depicted in
The voltage control stage consists of binary weighted varactors that are switched either onto the tuning line or to the cmin or cmax state, as depicted in
More particularly, a series of binary weighted varactors VS1 is formed with one plate of each varactor being connected to one side (C) of the oscillator configuration. The other plate of the respective varactors is connected to respective control voltage nodes N1, N1, etc. A complementary series of binary weighted varactors VS2 is connected to the other side (CZ) of the oscillator configuration. Capacitors of the same weight on opposite sides of the oscillator configuration are paired together, and are commonly controlled. Hence, the state of each varactor pair is determined by a voltage applied to the control voltage node. That voltage may be a supply voltage VDD, a reference voltage VSS, or an intermediate control voltage (VOLTAGE_CONTROL) applied by the user. A circuit CTL1 that determines a voltage applied to the control voltage node N1 will be described.
The control voltage node N1 is connected to VDD through a pair of PMOS transistors M1, M2, to VSS through a pair of NMOS transistors M3, M4, and to a voltage control input signal through a pass gate P. An enable signal ENABLE_1X is applied in its true form to one side of the pass gate and to the PMOS transistor M2. The enable signal is inverted by an inverter INV and is applied in its inverted form to the other side of the pass gate P and to the NMOS transistor M3. When the enable signal is asserted, the pass gate is opened, and the VOLTAGE_CONTROL signal is applied to the control voltage node N1. At the same time, the PMOS transistor M2 and the NMOS transistor M3 are rendered non-conducting.
An UNUSED_VARACTOR_STATE signal is applied to the PMOS transistor M1 and to the NMOS transistor M4. Depending on the value of this signal, one of these two transistors is rendered conducting and the other non-conducting. As a result, when the UNUSED_VARACTOR_STATE signal is low, the voltage VDD is applied to the source of the PMOS transistor M2 while the source of the NMOS transistor M3 remains floating. When the UNUSED_VARACTOR_STATE signal is high, the voltage VSS is applied to the source of the NMOS transistor M3 while the drain of the NMOS transistor M2 remains floating. When the enable signal is deasserted, the voltage determined by the UNUSED_VARACTOR_STATE signal is applied to the control voltage node.
Note that UNUSED_VARACTOR_STATE signal is connected in common to all of the varactor pairs. Similarly, the VOLTAGE_CONTROL signal is connected in common to all of the varactor pairs. Hence, if a varactor pair is enabled, it will be controlled by the VOLTAGE_CONTROL signal. If a varactor pair is not enabled, it, along with any and all other varactor pairs not enabled, will be set to either a minimum capacitance state or a maximum capacitance state depending on the UNUSED_VARACTOR_STATE signal.
The voltage control stage may be programmed to achieve a desired tuning voltage gain independent of the chosen frequency of operation (i.e., independent of the address number of the fine frequency adjust stage). To illustrate, the frequency of operation is given by the following equation:
F+dF=1/(2π(L*(C+dC))1/2) (2)
If it is desired to keep dF constant for any frequency(F), then setting dF equal to a constant and solving for dC will provide an equation modeling the desired behavior of the tuning voltage gain stage.
Substituting ½π(LC)2 for F to give only two variables:
F=1/(2π(L*C)1/2) (3)
F+dF=1/(2π(L*(C+dC)2π) (4)
(F+dF)2=1/4π2*L*(C+dC) (5)
C+dC=¼π2*L*(F+dF)2 (6)
Substituting (3) into (6):
C+dC=1/(4π2*L*(½π(L*C)1/2+dF)2)) (7)
dC=1/(4π2*L*(½π(L*C)1/2+dF)2)−C (8)
Eq. (8), gives the required dC (delta C) as a function of L, C, and dF.
Since dF is set to a constant, and L is constant for this discussion, dC is a function of C (frequency).
Notice that (4) provides F as a function of C, and dF as an independent function of dC. Since dC is now programmable (variable) by means of the tuning voltage gain stage, C determines the frequency, F, and dC determines the tuning voltage gain, dF, in an independent manner.
F is determined by the programmable capacitor switches which, with enough bits, gives fine digital control of center frequency. dF is determined by the programmable varactor switches, which gives continuous analog control of the frequency, ie, tuning gain.
The Gm stage is consists of N selectable complementary cross coupled CMOS inverters used to offset resistive losses found in the LC tank, and is depicted in
When any cell is selected, the cross coupled NMOS devices are pulled to ground by the select NMOS, and the cross coupled PMOS devices are pulled to a intermediate voltage created by the active filter R1, C1, M9. This filter isolates supply noise from the VCO. When deselected, the cross coupled transistors are left connected to the tank, but with no path to either rail, which consequently has little affect on the selected frequency, since the device parasitics are not removed from the tank. The number of stages selected to be active is determined by performance criteria, such as noise or power, and start-up requirements, due to the load. In this case, there is no binary weighting.
More particularly, the inverter stages INV1, INV2, etc. are connected in common with CZ as the input signal and C as the output signal. Separate enable signals ENABLE_1, ENABLE_2, etc. are provided for each inverter and determine whether a particular inverter will be connected or will be disconnected (floating). Taking as an example the first inverter INV1, the inverter itself is formed by PMOS transistors M11, M12 and NMOS transistors M13, M14 connected in the same manner as previously described in relation to the oscillator 100 of
As described in the foregoing description, a VCO, preferably wideband VCO, is provided that achieves independent control of critical VCO parameters including center frequency, tuning voltage gain and output drive strength (Gm). Incorporation of the VCO into PLLs or other systems is simplified in that operation of the VCO is readily optimized to achieve system design goals.
It will be appreciated by those of ordinary skill in the art that the invention can be embodied in other specific forms without departing from the spirit or essential character thereof. The foregoing description is therefore intended in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents thereof are intended to be embraced therein.
