Disclosed embodiments relate to circuits and methods for verifying proper bandgap reference circuit startup.
A bandgap reference (BGR) circuit is an essentially temperature independent voltage reference circuit widely used in integrated circuits (ICs). The principle of the bandgap voltage reference is to balance the negative temperature coefficient of a pn junction with the positive temperature coefficient of the thermal voltage, Vt=kT/q where T is the temperature, k the Boltzmann constant, and q is the electronic charge, to reduce reference voltage variation with temperature by having circuitry which sums a Proportional to Absolute Temperature (PTAT) current in a first branch and a Complementary to Absolute Temperature (CTAT) current in a second branch.
The BGR thus generates an essentially fixed (constant) voltage that is largely invariant irrespective of power supply variations, temperature changes and the loading on the BGR. The BGR typically has an output voltage around 1.25 V, which is nearly the voltage corresponding to the theoretical 1.22 eV bandgap energy of silicon at 0 K.
The BGR circuit has two stable states, an off state, which does not output a reference voltage (its off-state), and an operational state (its on-state), which provides the desired reference voltage. When power is first applied to a BGR circuit, the BGR enters its off-state, in which no current initially flows through the BGR circuit. The BGR remains in its off-state until another circuit referred to as a startup circuit forces it to transition to its on-state. Once the on-state has been established, the startup circuit is electrically disconnected from the BGR circuit so that the startup circuit no longer influences the operation of the circuit being served by the BGR circuit.
This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. This Summary is not intended to limit the claimed subject matter's scope.
Disclosed embodiments recognize there are applications for bandgap reference (BGR) circuits that span a wide range of power supply ramp rates. In some of these applications, such as for energy harvesting where there may be low power and a slow supply voltage ramp rate, the BGR circuit may not properly start, and thus may undesirably remain in its off-state. Disclosed BGR startup verification circuits include a plurality of verification sub-circuits which each act independently to provide a separate verification output which are collectively used by a digital logic state machine (digital state machine) to determine a startup status (either OK (i.e., on-state, acceptable) or not-OK (the off-state, not acceptable) for a variety of BGR circuit topologies and for a wide range of power supply ramp rates.
Disclosed BGR startup verification circuits combine a plurality of different startup verification sub-circuits including for example a current comparator to handle steep power ramps, a voltage comparator to check if the power supply exceeds the bandgap voltage (for slow ramps), and a voltage comparator to ensure the branch currents in the BGR circuit are greater than zero. All verification sub-circuits have their respective outputs coupled to the digital state machine. If the verification outputs provided by the respective verification sub-circuits all generate an OK status, the startup status for the BGR circuit is determined by the digital state machine to be OK, and the disclosed BGR startup verification sub-circuits can all be disabled (e.g., using at least one switch in the respective sub-circuits controlled by control signals generated by the digital state machine) to conserve power. If the startup status for the BGR circuit is determined by the digital state machine to not be OK, the BGR circuit generally stays in this state and the BGR startup verification sub-circuits can remain enabled. As an alternative, a pin of the digital state machine can be used to indicate a verified BG circuit startup failure.
Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:
Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
Also, the terms “coupled to” or “couples with” (and the like) as used herein without further qualification are intended to describe either an indirect or direct electrical connection. Thus, if a first device “couples” to a second device, that connection can be through a direct electrical connection where there are only parasitics in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal but may adjust its current level, voltage level, and/or power level.
A startup circuit for the BGR circuit 160 is not shown in
Startup verification circuit 100 includes a first verification sub-circuit 120 coupled to receive the first output current IPTAT1 and as shown in
The voltage comparator 121 converts analog input signals at its inputs being VBG and Vdet to a digital output signal, OK1. First verification sub-circuit 120 is configured to check if the power supply (shown as VDD in
When the BGR circuit 160 settles down its final value (typically VBG˜1.2V), the circuitry in the BGR circuit 160 will also settle to a steady state. When there is a current IPTAT1 which flows through PMOS transistors 126 and 127 in the first verification sub-circuit 120 shown in
Startup verification circuit 100 includes a second verification sub-circuit 130 comprising a voltage comparator (i.e. VTH comparator) shown in
Regarding operation of second verification sub-circuit 130, IBIAS2 from POR block 180 charges the capacitor C2a shown in second verification sub-circuit 130 in
Startup verification circuit 100 also includes a third verification sub-circuit 140 comprising a current comparator shown in
As noted above, the digital state machine 170 has respective inputs coupled for receiving the first verification output OK1, receiving the second verification output OK2, and receiving the third verification output OK3. Digital state machine 170 also includes circuitry for processing OK1, OK2 and OK3 to determine whether the BGR circuit 160 has properly started. Digital state machine 170 is shown in
The digital state machine 170 is shown providing enable outputs En.BG, En.OK1, En.OK2, and En.OK3 which are used as control signals to disable the sub-circuits in the startup verification circuit 100 when not needed (e.g., after successful BGR circuit 160 startup is verified) to save power. Switches which enable disabling of the BG circuit 160 are shown as switches 166 and 167 in
Regarding the second verification sub-circuit 130, as shown in
Based on the digital state machine 170, there is generally a sequence for enabling the respective verification sub-circuits 120, 130, and 140. There are a variety of possible enable sequences. A first possibility is to first enable En_OK2→ when OK2 is high→ disable En_OK2 and enable En_OK3→ when OK3 is high→ disable En_OK3 and finally enable OK1-> when OK1 is high, meaning the BGR circuit startup is successful.
A second possibility is to first enable En_OK2→ when OK2=high, further enable En_OK3→ when OK3=high, then further enable en_OK1→ when all OK1=OK2=OK3=high at the same time, meaning the BGR circuit startup is successful. Other sequencing possibilities can also be generated by one having ordinary skill in the art of circuit design.
The digital state machine 170 can include a processor and in this embodiment generally comprises a MCU (see
Startup verification circuit 100 can be modified in a variety of ways. For example, bipolar transistors can be used instead or together with MOS devices, such as for implementing the current mirror 110 and first verification sub-circuit 120. Additional verification sub-circuits may be added. In addition, all Ok outputs, OK1=OK2=OK3=low at the same time instead of being high can be used to indicate whether the BGR circuit startup is successful.
Step 204 comprises coupling the third output current to a third verification sub-circuit generally comprising a current comparator coupled to receive the third output current and a third reference current (IBias3 in
MCU chip 300 is shown including a non-volatile program memory 372, a volatile data memory 373, an input/output (I/O) interface 374, central processing unit (CPU) 375, and clock 376. MCU chip 300 is also shown including a digital data bus 278 and an address bus 279. Disclosed BGR startup verification circuit software 119 is shown in non-volatile program memory 372. BGR startup verification circuit software 119 generally provides the functionality described above, including processing the first verification output, the second verification output, and third verification output to determine whether the BGR circuit has properly started.
Advantages of disclosed embodiments include disclosed BGR startup verification circuits able to interrogate at least three 3 different conditions with 3 separate OK elements over a very wide range of supply voltage ramp rates, such as from <|1V|/ms to >1V/10 nsec, which are controlled and combined in a digital state machine that ensures that the BGR circuit is properly started. Each condition is checked with a separate (independent) verification sub-circuit. As noted above, the BGR circuit and each of the verification sub-circuits can be disabled after usage to save power.
Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.
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