Verifier for a personal indentification system

Abstract

A verifier for use in a personal identification system of the type in which a generator receives at least a personal account number (PAN) and a secret personal identification number (PIN) and based thereon produces digits A.sub.i 's which are present in a feedback shift register (FSR) A and digits C.sub.i 's present in a feedback shift register (FSR) C respectively. The A.sub.i 's and C.sub.i 's are mapped into D.sub.i 's which represent digits of an Offset Number which together with the PAN are recorded on the magnetic stripe of a card. To use the cards the Offset Number and the PAN are read off therefrom and an intended user enters a secret PIN. In the verifier, the PIN is operated upon to produce C.sub.i 's and the PAN is operated upon to produce A.sub.i 's. The latter together with the D.sub.i 's of the received Offset Number are mapped by a processer (201) to form C.sub.i.sup.c 's. These are compared with the C.sub.i 's by a comparator (202) to determine whether the intended card user is the rightful user.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a Personal Identification System and, more particularly, to an improved arrangement in the verification position of such a system.

2. Description of the Prior Art

In U.S. patent application Ser. No. 229,085 filed on Jan. 28, 1982, an advanced Personal Identification System is described. The application entitled "Personal Identification System" was filed by the inventors Marvin Perlman and Milton Goldfine and assigned to the same assignee as the present application.

Briefly, the system described in said application comprises a generator which generates an Offset Number which is recorded on the magnetic stripe of a card, together with the account number (PAN) of the person to whom the card is to be issued. The generator stores transformed digits of a sequence of digits (IN) which have been secretly entered by one or more officers of the card-issuing institution. To generate the Offset Number the PAN is entered and transformed before initializing a first feedback shift register. The person to whom the card is to be issued enters a secretly chosen alphanumeric sequence (PIN), known only to him. The PIN, after undergoing a transformation initializes a second feedback shift register. When both registers have been initialized they are reinitialized by different parts of the representation of different digits of the transformed IN. The contents of a subset of the stages of the two registers are used to initialize a control feedback shift register which when reaching a selected state in its cycle of states assumes the timing and control of the generator during the derivation of the Offset Number, based on a selected mapping of the digits, then present, in the first and second feedback shift registers.

A credit card is entered into a verifier at the inception of a validation test of identity. Therein the PAN and Offset Number on the magnetic stripe on the card are read out. The user enters a secret PIN, and the verifier, like the generator, generates an Offset Number. Only if the PIN, entered into the verifier, is identical to that originally entered into the generator, does the verifier produce an Offset Number which is identical to that read off the card, thereby verifying the identity of the card user as the one to whom the card was issued.

The above described system, as disclosed in said application, represents a very significant break through in the state of the art in that it provides a higher degree of security than any attainable with any prior art system. However, as herebefore described, the verifier, to a very large degree, operates as the generator in that, like the generator, it generates an Offset Number. In addition, the verifier compares the Offset Number it generates with the one, present on the card's magnetic stripe, and only when the two are identical is an indication given that the person who entered the secret PIN has been identified as the rightful user of the card.

It is believed that an added degree of security may be achieved if the verifier were to operate in a mode different from that of the generator. This is partially based on the fact that whereas each generator will be located in a very secure location, where cards are to be issued, verifiers, however, will be present and transportable in the many thousands of establishments where cards can be used. Thus verifiers are accessible to unscrupulous people who may try to determine how the original generators produce valid PAN-PIN-OFFSET combinations. As described in said application, the verifier contains portions which make it practically impossible for one to open the verifier and completely analyze its mode of operation, and thereby determine the operation of the generator. It is believed, however, that an added degree of security may be attained by designing the verifier so that it does not mimic the behavior of the generator.

SUMMARY OF THE INVENTION

In accordance with the present, just like in the prior application, the Offset Number together with the PAN are read off the card and fed to the verifier. The latter is also supplied with the secret PIN which the card user supplies. The PIN and PAN together with the digits of any Institution Number (IN) are processed so that feedback shift registers A and C store digits A.sub.1, A.sub.2 --An and C.sub.1, C.sub.2 --C.sub.n, generally referred to in the prior application as A.sub.i and C.sub.i. The digits of the Offset Number are designated D.sub.i. In the prior application, when the feedback shift register B (See FIGS. 1 and 12) realizes a particular state, a decoder 40 (See FIG. 12) sensing that state actuates a processor 45 (See FIG. 12). The latter sequentially combines the A.sub.i 's and the C.sub.i 's in accordance with a preselected processing function to generate and produce the D.sub.i 's of the Offset Number, which are then compared with the D.sub.i 's which were read off the card and stored in the verifier.

In accordance with the present invention, the C.sub.i 's are derived in the same manner as described in the prior application. However, instead of mapping them with the A.sub.i 's to produce the D.sub.i 's, the derived A.sub.i 's and the stored D.sub.i 's are mapped into a set of computed digits, generally designated as C.sub.i.sup.c 's where the superscript c designates computed C.sub.i 's, as the result of the mapping of the derived A.sub.i 's and the stored D.sub.i 's. The derived C.sub.i 's and the computed C.sub.i.sup.c 's are compared and only when they are identical is an indication given that the one who entered the secret PIN is the rightful card user. Thus, in the improved verifier an Offset Number, like the one stored on the card, is never generated.

Briefly stated, in the new improved verifier, C.sub.i 's are derived as a function of PIN, as in the generator. Also A.sub.i 's are derived as a function of PAN, as in the generator. However, whereas in the prior verifier the A.sub.i 's and C.sub.i 's are mapped into D.sub.i 's which are the Offset Number, which is compared with the D.sub.i 's of the Offset Number recorded on the card, in the present verifier the D.sub.i 's of the Offset Number are mapped with the A.sub.i 's into C.sub.i.sup.c 's which are compared with the C.sub.i 's actually derived in the verifier, from the secretly entered PIN.

The novel features of the invention are set forth with particularity in the appended claims. The invention will be best understood from the following description when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a flow chart type diagram useful in explaining the generation of one Offset Number in a generator;

FIG. 2 is a flow chart type diagram useful in explaining the operation of one embodiment of the improved verifier;

FIG. 3 is a multiline diagram of A.sub.i 's and C.sub.i 's used in the generator to form D.sub.i 's of the Offset Number;

FIG. 4 is a diagram of a Latin Square to map the A.sub.i 's and C.sub.i 's into the D.sub.i 's;

FIG. 5 is a multiline diagram showing one example of mapped A.sub.i 's and D.sub.i 's into C.sub.i.sup.c 's;

FIG. 6 is a Latin Square to produce to mapping of the A.sub.i 's and D.sub.i 's into the C.sub.i.sup.c 's;

FIGS. 7, 8 and 9 are diagrams useful in explaining other embodiment of the invention;

FIG. 10 is a block diagram useful in explaining another advantage of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present application incorporates by reference the description in patent application which matured into U.S. Pat. No. 4,376,279, issuing on Mar. 8, 1983. Ser. No. 229,085 filed on Jan. 28, 1981, by the applicants of the present application and assigned to the same assignee, said application being deemed as fully set out and described herein.

The manner of generating the Offset Number in the generator as well as in the verifier described in the prior application may best be summarized in connection with FIG. 1. Therein and in the other figures when referring to various parts of prior application (PA) will also be used in the present application.

Briefly in the generator 10 (see PA FIG. 1) the PAN is entered into and effectively initializes FSR A, the contents of which are designated by PAN'. Similarly, PIN is entered and effectively initializes FSR C, the contents of which are designated PIN'. These operations are performed asynchronously. When both FSR A AND FSR C have been initialized, the system enters a synchronous mode, during which both FSR A AND FSR C are reinitialized, such as by selected portions of the representation of digits of the Institution Number (IN) in the IN STORAGE 15. The reinitialized PAN and PIN are designated by PAN" and PIN", respectively. The stages of FSR B (35 & 95) are then initialized. The FSR's A,B and C are clocked and assume successive states, until FSR B reaches a selected state. Thereafter, during a succession of clock periods the C.sub.i 's in FSR C and corresponding A.sub.i 's in FSR A are mapped to generate the D.sub.i 's, which from the Offset Number, which is recorded on the card. That is, D.sub.i =A.sub.i *C.sub.i. The mapping is provided by processor 45 (See PA FIGS. 1 & 12).

As pointed out in the prior application, the mapping may be a Latin Square, as shown in FIG. 13 of the prior application. Therein a 10.times.10 Latin Square is shown. As also pointed out in the prior application, the number of possible 10.times.10 Latin Squares has not been computed as yet. The number of 9.times.9 Latin Squares is known to be greater than 3.7.times.10.sup.17 (See PA FIG. 40).

The verifier, described in the prior application, generates D.sub.i 's just like the generator. Once the D.sub.i 's are generated in the verifier, they are correspondingly compared with those read off the card.

Unlike the prior verifier, with an arrangement in accordance with the present invention, D.sub.i 's are never generated in the verifier, for comparison with corresponding D.sub.i 's which were recorded on the card. The mode of operation in one embodiment of the improved verifier may best be explained in connection with FIG. 2. As shown therein, the D.sub.i 's of the Offset Number are read off the card and temporarily stored in the verifier. The PAN which is read off the card effectively initializes FSR A to form PAN'. Likewise the PIN, which the user secretly enters into the verifier, effectively initializes FSR C to form PIN'. Then, both FSR A and FSR C are reinitialized to form PAN" and PIN", respectively. The FSR B is effectively initialized by portions of PIN" and PAN". Then FSR's A, B and C are clocked synchronously until FSR B reaches the particular state, which is sensed by the decoder 40 (See PA FIG. 12). At this point the contents of FSR A i.e. the A.sub.i 's and the stored D.sub.i 's, are mapped by a processor 201 to form computed C.sub.i 's, hereafter referred to as C.sub.i.sup.c 's. They are subsequently compared with the corresponding derived C.sub.i 's in FSR C by a comparator 202. Only when corresponding C.sub.i.sup.c 's and C.sub.i 's are identical is a valid signal provided, thereby indicating that the user who entered the secret PIN into the verifier is the rightful user. On the other hand if one or more corresponding C.sub.i.sup.c 's and C.sub.i 's are not identical, an invalid signal is produced.

The foregoing may further be explained in connection with a specific example. Let it be assumed that in the generator, the state of FSR B is decoded by decoder 40 (See PA FIG. 12) and such state indicates that the processor 45 should be activated to map the A.sub.i 's in FSR A and the C.sub.i 's in FSR C and that the A.sub.i 's and C.sub.i 's are as shown in lines a and b of FIG. 3. Let it further be assumed that processor 45 provides a mapping, based on the Latin Square shown in FIG. 4. That is, D.sub.i =A.sub.i *C.sub.i. It should be apparent that the D.sub.i 's of the Offset Number would be as shown in line c of FIG. 3. These D.sub.i 's are recorded on the magnetic stripe of the card.

As to the verifier, these D.sub.i 's are stored therein, as shown in line c of FIG. 5. In the verifier the A.sub.i 's and C.sub.i 's are generated as they were in the generator. They are shown in lines b and a, respectively of FIG. 5. As to the processor 201 (See FIG. 2) as previously pointed out, it maps corresponding A.sub.i 's and the stored D.sub.i 's into the C.sub.i.sup.c 's. The processor 201 produces a mapping based on a preselected Latin Square which is related to the Latin Square in the processor 45 of the generator. Such a Latin Square in processor 201 is shown in FIG. 6. With such a Latin Square, the mapping can be expressed as C.sub.i.sup.c =A.sub.i D.sub.i, resulting in computed C.sub.i.sup.c 's as shown in line d of FIG. 5, at the time the C.sub.i.sup.c 's are produced. C.sub.i 's are present in FSR C, as shown in line a of FIG. 5.

The comparator 202 (See FIG. 2) compares each C.sub.i with a corresponding C.sub.i.sup.c. Only if respective components are identical, does the comparator 202 produce a valid signal. The C.sub.i 's (line a of FIG. 5) do not match corresponding C.sub.i.sup.c 's whenever the PIN which was entered is not the correct secret PIN. Thus, the comparator produces an invalid signal.

To further increase the security provided by the system, traps may be introduced in the verifier to prevent unauthorized use of the system. For example, the C.sub.i 's generated in the verifier as a function of PIN may undergo a transformation T in a transformation unit 205 (See FIG. 7). Let it be assumed that the transformation is as follows:

______________________________________digit 0 1 2 3 4 5 6 7 8 9T transformed digit 7 2 8 6 0 3 5 9 1 4______________________________________ Thus comparator 202 (FIG. 7) will no longer be provided with C.sub.i 's but rather with transformed C.sub.i 's, designated C.sub.i T's. Let it be assumed that in the following example the A.sub.i 's, C.sub.i 's and D.sub.i 's in the generator are the same as in the previous example, as shown in lines a, b and c, respectively, in FIG. 3. As to the verifier the C.sub.i 's generated therein as a function of a correct PIN would be the same, i.e. 8 1 0 3 6 6 1 9 3 1, as shown in line a of FIG. 8. However, after undergoing the transformation T the C.sub.i 's are converted into the C.sub.i T's as shown in line b.

The A.sub.i 's, produced in the verifier, and the stored D.sub.i 's which were read off the card are mapped by processor 201x, which is similar to processor 201, heretofore described. However, its output, i.e. the C.sub.i.sup.c 's, have to be compared not with corresponding C.sub.i 's, but with corresponding transformed C.sub.i 's, namely with C.sub.i T's. Therefore, a Latin Square, different from that shown in FIG. 6, must be employed to account for the transformation of the C.sub.i 's, into C.sub.i T's. Such a Latin Square is shown in FIG. 9. Its mapping can be expressed as C.sub.i.sup.c T=A.sub.i D.sub.i =(A.sub.i D.sub.i)T to account for the transformation of the C.sub.i 's in te verifier, as shown in line a of FIG. 8 into the C.sub.i T's, as shown in line b. The A.sub.i 's and D.sub.i 's are unaffected as shown in lines c and d. Also, once mapped by processor 201x, the output would be C.sub.i.sup. c T's, as shown in line e. It is the C.sub.i.sup.c T's which are compared with the corresponding C.sub.i T's by comparator 202.

It should be stressed that in either embodiment, the verifier never generates an Offset Number to be compared with that on the card. Rather the digits of the Offset Number (the D.sub.i 's) which are supplied to the verifier are mapped with the A.sub.i 's, derived therein as a function of PAN, to produce C.sub.i.sup.c 's (or C.sub.i.sup.c T's), which are compared, with corresponding C.sub.i 's (or C.sub.i T's) to verify whether or not the one using the card is the rightful card owner.

At present, in establishments where cards are used, little, if any, effort is devoted to validate the identity of the card user. More often only the account status is checked to determine if charges can be made. To this end, establishments have a small unit with a keyboard. The proprietor enters the account number via a keyboard or it is read off from the card by a card reader. This number is then communicated to a computer wherein the status of all accounts are stored. An indication of the account status is sent back to the proprietor. However, it must be stressed that this procedure only checks the account status. It in no way validates the user's identity.

In accordance with an improved embodiment of the invention, the existing unit may be eliminated and its functions incorporated in the verifier, as diagrammed in FIG. 10. Therein numeral 210 designates a card reader which reads at least the PAN i.e. the A.sub.i 's and the Offset Number i.e. the D.sub.i 's and stores them into the verifier 215. Once the secret PIN is entered by the user, the verifier validates the identity of the user. Only if he (or she) is the rightful user will comparator 202 provide a valid signal (C.sub.i =C.sub.i.sup.c or C.sub.i T=C.sub.i.sup.c T). Only a valid signal output from comparator 215 enables the automatic transmission of PAN, which is stored in the verifier, to a location wherein the status of all accounts are stored, e.g., a remotely located computer via lines 216. If the account status is good an appropriate indication is returned, e.g. a green light 217 is illuminated. On the other hand, if the account status is bad by one or more criteria, a red light 218 is turned on. It should be stressed, that the return indication corresponding to a good account status can be used as a secure enabling signal which permits the completion of the transaction.

It should be pointed out that the determination of the account status may be done at the same time the person's identity is being validated. However, since for each inquiry of account status the proprietor is charged a fee, it is preferable to determine the account status only after the identity of the card user has been validated.

Although particular embodiments of the invention have been described and illustrated herein, it is recognized that modifications and variations may readily occur to those skilled in the art and consequently, it is intended that the claims be interpreted to cover such modifications and equivalents.

Claims

1. A verifier for use in a personal identification system of the type in which a card is issued to a person by an entity with a personal assigned number, definable as PAN, which is recorded on the card, and a number definable as an Offset Number, which is also recorded on the card, said Offset Number being generated by a generator of said system as a function of at least said PAN and a secret code in the form of a digital sequence secretly chosen, by and known only by said person, definable as PIN, the verifier comprising:

first means for receiving said PAN and said Offset Number, recorded on said card, for processing said PAN and thereafter mapping said PAN and the digits of the Offset Number, definable as D.sub.i 's, to provide a sequence of digits, definable as C.sub.i.sup.c 's;

second means for receiving a PIN from a person the identity of which is to be verified and for processing said PIN to provide a sequence of digits, definable as C.sub.i 's; and

comparing means for comparing corresponding C.sub.i.sup.c 's and C.sub.i 's to provide a valid signal when C.sub.i.sup.c 's=C.sub.i 's for each i and for providing an invalid signal when C.sub.i.sup.c 's.noteq.C.sub.i 's for one or more i's.

2. A verifier as recited in claim 1 wherein said first means include feedback shift register means, definable as FSR A, and means for transforming the PAN into transformed digits, prior to storing them in said FSR A, and said second means include second feedback shift register means, definable as FSR C and means for transforming the PIN digits prior to storing them in said FSR C, said verifier further including third feedback shift register means definable as FSR B, means for clocking said FSR's A, B and C, means for initializing said FSR B with at least portions of digits in said FSR's A and C, said first means producing said C.sub.i.sup.c 's only during a sequence of clock periods following a selected sensed state of FSR B and said comparing means comparing said C.sub.i.sup.c 's with said C.sub.i 's which are provided from FSR C during said sequence of clock periods.

3. A verifier as recited in claim 2 wherein said first means include mapping means for providing said C.sub.i.sup.c 's during said sequence of clock pulses by mapping A.sub.i 's, provided by said FSR A during said sequence, with D.sub.i 's stored in said verifier, whereby C.sub.i.sup.c =A.sub.i * D.sub.i, where * represents a mapping operation.

4. A verifier as recited in claim 3 wherein said mapping means include means for mapping said A.sub.i 's and D.sub.i 's based on a preselected criteria, which is related to mapping in the generator of the outputs of said FSR's A and C into the D.sub.i 's, comprising said Offset Number.

5. A verifier as recited in claim 4 wherein the mapping is based on a Latin Square of n.times.n, where n is an integer.

6. A verifier as recited in claim 5 wherein n=10.

7. A verifier as recited in claim 4 wherein said verifier includes transformation means for transforming the outputs of said FSR C, definable as C.sub.i 's, into C.sub.i T's (corresponding to C.sub.i Transformed) and said mapping means includes means for mapping said A.sub.i 's and D.sub.i 's based on a preselected criteria which is related to mapping, in the generator, of the outputs of said FSR's A and C to generate the D.sub.i 's, comprising said Offset Number and is further related to the transformation performed by said transformation means.

8. A verifier as recited in claim 7 wherein the mapping is based on a Latin Square of N.times.N where N is an integer.

9. A verifier as recited in claim 8 wherein N=10.

10. A verifier as recited in claim 1 further including means for indicating whether said comparing means provides a valid signal or an invalid signal.

11. A verifier as recited in claim 1 further including means responsive to a valid signal from said comparing means for transmitting the PAN, received from a card, to a location whereat the status of accounts, including the account represented by said PAN, are present, and means in said verifier for enabling the transaction involving the use of said card to be completed only if a signal is received from said location, indicating that the status of the account, identified by said PAN, is good.