Vertical type nitride semiconductor light emitting device and method of manufacturing the same

Abstract

A vertical nitride semiconductor light emitting device and a manufacturing method thereof are provided. In the device, an ohmic contact layer, a p-type nitride semiconductor layer, an active layer, an n-type nitride semiconductor layer and an n-electrode are sequentially formed on a conductive substrate. At least one of a surface of the p-type nitride semiconductor layer contacting the ohmic contact layer and a surface of the n-type nitride layer contacting the n-electrode has a high resistance area of damaged nitride single crystal in a substantially central portion thereof. The high resistance area has a Schottky junction with at least one of the ohmic contact layer and the n-electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a side sectional view illustrating a conventional nitride light emitting device;

FIG. 2 a is a side sectional view illustrating a vertical nitride light emitting device according to an embodiment of the invention;

FIG. 2 b is a top plan view cut along the line X-X′ of FIG. 2a;

FIGS. 3 a to 3e are cross-sectional views for explaining a method for manufacturing the vertical nitride light emitting device shown in FIG. 2a; and

FIG. 4 is a side sectional view illustrating a vertical nitride light emitting device according to another embodiment of the invention.

Claims

1. A vertical nitride semiconductor device comprising an ohmic contact layer, a p-type nitride semiconductor layer, an active layer, an n-type nitride semiconductor layer and an n-electrode sequentially formed on a conductive substrate, wherein at least one of a surface of the p-type nitride semiconductor layer contacting the ohmic contact layer and a surface of the n-type nitride layer contacting the n-electrode has a high resistance area of damaged nitride single crystal in a substantially central portion thereof, the high resistance area having a Schottky junction with at least one of the ohmic contact layer and the n-electrode.

2. The vertical nitride semiconductor device according to claim 1, wherein the high resistance area has a contact resistance of at least 10−2Ω·cm2 with respect to the ohmic contact layer or the n-electrode.

3. The vertical nitride semiconductor device according to claim 1, wherein the high resistance area has a thickness smaller than that of the p-type or n-type nitride semiconductor layer where the high resistance area is formed.

4. The vertical nitride semiconductor device according to claim 1, wherein the high resistance area represents 10% to 50% with respect to at least one of a total area of the surface of the p-type nitride semiconductor layer which is in the side of the ohmic contact layer and a total area of the surface of the n-type nitride semiconductor layer which is in the side of the n-electrode.

5. The vertical nitride semiconductor device according to claim 1, wherein the high resistance area is formed on both the surface of the p-type nitride semiconductor layer contacting the ohmic contact layer and the surface of the n-type nitride semiconductor layer contacting the n-electrode.

6. The vertical nitride semiconductor device according to claim 1, wherein the ohmic contact layer has high reflectivity.

7. The vertical nitride semiconductor device according to claim 1, further comprising a high reflectivity metal layer between the ohmic contact layer and the conductive substrate, wherein the ohmic contact layer comprises a light transmissible material.

8. A method for manufacturing a vertical nitride semiconductor device comprising an ohmic contact layer, a p-type nitride semiconductor layer, an active layer, an n-type nitride semiconductor layer and an n-electrode sequentially formed on a conductive substrate, the method comprising a step of selectively plasma-treating a substantially central portion of at least one of a surface of the p-type nitride semiconductor layer contacting the ohmic contact layer and a surface of the n-type nitride layer contacting the n-electrode to damage a corresponding portion of nitride single crystal thereof, thereby forming a high resistance area having a Schottky junction with at least one of the ohmic contact layer and the n-electrode.

9. The method according to claim 8, wherein the high resistance area forming step is carried out by plasma generated from an inert gas.

10. The method according to claim 9, wherein the inert gas comprises at least one selected from a group consisting of Ar, He, N2, CF4 and H2.

11. The method according to claim 8, wherein the high resistance area has a contact resistance of at least 10−2Ω·cm2 with respect to the ohmic contact layer or the n-electrode.

12. The method according to claim 8, wherein the high resistance has a thickness smaller than that of the p-type or n-type nitride semiconductor layer where the high resistance area is formed.

13. The method according to claim 8, wherein the high resistance area represents 10% to 50% with respect to at least one of a total area of the surface of the p-type nitride semiconductor layer which is in the side of the ohmic contact layer and a total area of the surface of the n-type nitride semiconductor layer which is in the side of the n-electrode.

14. The method according to claim 8, wherein the ohmic contact layer has high reflectivity.

15. The method according to claim 8, wherein the ohmic contact layer comprises a light transmissible material, and wherein the vertical nitride semiconductor device further comprises a high reflectivity metal layer between the ohmic contact layer and the conductive substrate,

16. The method according to claim 8, wherein the high resistance forming step is carried out on both the surface of the p-type nitride semiconductor layer contacting the ohmic contact layer and the surface of the n-type nitride semiconductor layer contacting the n-electrode.