The present invention relates generally to transistor circuits, and more specifically to circuits useful for biasing transistor circuits.
In some applications, transistors may be “biased” to operate in a particular fashion. For example, a field effect transistor (FET) may be biased by having a “bias voltage” applied between two device terminals of the FET. Prior art bias circuits may apply a constant gate-to-source voltage (Vgs) between gate and source terminals of a transistor.
Transistor characteristics may vary due to manufacturing variations and/or operating conditions. For example, a transistor's threshold voltage (Vth) may change due to temperature or power supply voltage variations.
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein in connection with one embodiment may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
Transistor 110 also has a gate node coupled to the drain node. This configuration is referred to herein as a “diode-connected” transistor. When a current is drawn through a diode-connected transistor, a gate-to-source voltage will result. In some embodiments, transistor 110 is not diode-connected. For example, the gate of transistor 110 may be coupled to an auxiliary bias circuit, and the drain may be suitably connected for transistor 110 to operate in the saturation region.
In operation, current source 140 provides current I1 drain-to-source through transistor 110. In response to current I1 traveling from drain-to-source through transistor 110, a voltage (VBIAS1) appears as the gate-to-source voltage (Vgs) between the gate node and source node of transistor 110. VBIAS1 is related to the threshold voltage of transistor 110 and the amplitude of current I1 provided by current source 140. For example, for a nominal current I1, VBIAS1 may be close to the threshold voltage of transistor 110, or somewhat different according to the application.
Transistor 120 is coupled to transistor 110 such that VBIAS1 is imposed from the source node to the gate node of transistor 120. As shown in
Circuit 100 has nodes 182 and 180 having a voltage differential of VBIAS1. For example, if a voltage is imposed on node 182 from an external source (shown as VREF1) then the voltage at 180 will be VREF1+VBIAS1. The voltage between nodes 180 and 182 is substantially equal to a threshold voltage of an NMOS transistor such as transistor 110 even though it appears across the source and gate terminals of a complementary source follower transistor such as transistor 130. This source follower bias circuit may be utilized as a low impedance bias circuit to bias other NMOS transistors. As shown in
In some embodiments, transistors 120 and 130 have different sizes such that the source-to-gate voltage across transistor 130 is different than transistor 120. For example, gate area, length, or width of transistor 130 may be a multiple or sub-multiple of the corresponding measure of transistor 120. In this manner, any bias voltage may be created across the source-to-gate junction of transistor 130, where that bias voltage is related to, and controlled by, the gate-to-source voltage of transistor 110.
The circuit of
In operation, transistors 352, 354, 362, and 364 are biased such that the gate-to-source of the n-channel transistors have a DC bias component substantially equal to VBIAS1, which is determined by transistor 110.
Passive auxiliary bias circuit 310 includes resistors 312, 314, 322, and 324, and capacitors 316 and 326. Resistors 322 and 324 and capacitor 326 form a low pass filter to provide the output common mode voltage VCM on node 182, which is coupled to the gate node of transistor 130. As described above with reference to
The LO and RF signals for the passive mixer are AC coupled. Therefore the drain and source voltages of transistors 352, 354, 362, and 364 are the DC voltages of IF+ and IF−, which are set by the next stage, which in some embodiments may be a transimpedance amplifier or a variable gain amplifier. Resistors 322 and 324, and capacitor 326 form a low pass filter and produce the common mode voltage VCM of IF+ and IF−. This sets the gate voltage of transistor 130. The source voltage of transistor 130 is low pass filtered by capacitor 316, and resistors 312 and 314 set the gate voltage of transistors 352, 354, 362, and 364. Therefore Vgs for transistors 352, 354, 362, and 364 is set by Vgs of transistor 130. However, because transistor 130 is a PMOS transistor and transistors 352, 354, 362, and 364 are NMOS, their threshold voltage will not track over process corners and temperature. This is alleviated by the addition of transistors 120, 110, and I1. In the example of FIG. 3, transistors 120 and 130 are PMOS of the same gate width-to-length ratio (W/L). Since the same amount of current pass through these two transistors, to the first order their Vgs have to be the same. This same Vgs also appears across the gate and source of transistor 110 due to the configuration shown in
When transistors 352, 354, 362, and 364 are on, they have a very low on resistance, and a voltage at the drain and source nodes are substantially equal. For this reason, providing the bias voltage between the gate and drain nodes is substantially equivalent to providing a bias voltage between the gate and source nodes. Further, depending on voltage values, what is referred to herein as the drain may actually function as a source and vice versa.
As shown in
Mixer 350 has low flicker noise since almost no low DC current flows through the mixer transistors 352, 354, 362, and 364. The bias voltage of the gates of transistors 352, 354, 362, and 364 affects the mixer performance in the following way. When Vgs is greater than the threshold voltage Vth, transistors pairs 352, 362 and 354, 364 will be simultaneously turned on in each LO cycle. This increases the gain of the mixer and also increases the output thermal noise. However if the Vgs is biased too low, for a fixed LO swing VLO, the overdrive voltage VLO−Vth is reduced and linearity will be degraded. Biasing at a different Vgs may fold 1/f noise from harmonics of the LO. The circuits shown in
Method 400 begins at 410 when a current is drawn drain-to-source through an NMOS transistor to produce an NMOS gate-to-source voltage (Vgs). For example, referring now to
At 420, the NMOS gate-to-source voltage is imposed across a PMOS source-to-gate junction. As shown in
At 430, current from the PMOS transistor is provided to a source node of a second PMOS transistor to replicate the Vgs of the MOS transistor as a source-to-gate voltage of the second PMOS transistor. Referring again to
Using method embodiments of the present invention, a bias voltage from one type of transistor may be replicated across a gate to source junction of a complementary transistor.
Antenna 550 may include one or more antennas. For example, antenna 550 may include a single directional antenna or an omni-directional antenna. As used herein, the term omni-directional antenna refers to any antenna having a substantially uniform pattern in at least one plane. For example, in some embodiments, antenna 550 may include a single omni-directional antenna such as a dipole antenna, or a quarter wave antenna. Also for example, in some embodiments, antenna 550 may include a single directional antenna such as a parabolic dish antenna or a Yagi antenna. In still further embodiments, antenna 550 may include multiple physical antennas. For example, in some embodiments, multiple antennas are utilized for multiple-input-multiple-output (MIMO) processing or spatial-division multiple access (SDMA) processing.
Physical layer (PHY) 540 is coupled to antenna 550 to interact with other wireless devices. PHY 540 may include circuitry to support the transmission and reception of radio frequency (RF) signals. For example, as shown in
PHY 540 may be adapted to transmit/receive and modulate/demodulate signals of various formats and at various frequencies. For example, PHY 540 may be adapted to receive time domain multiple access (TDMA) signals, code domain multiple access (CDMA) signals, global system for mobile communications (GSM) signals, orthogonal frequency division multiplexing (OFDM) signals, multiple-input-multiple-output (MIMO) signals, spatial-division multiple access (SDMA) signals, or any other type of communications signals. The various embodiments of the present invention are not limited in this regard.
Example systems represented by
Media access control (MAC) layer 530 may be any suitable media access control layer implementation. For example, MAC 530 may be implemented in software, or hardware or any combination thereof. In some embodiments, a portion of MAC 530 may be implemented in hardware, and a portion may be implemented in software that is executed by processor 510. Further, MAC 530 may include a processor separate from processor 510.
Processor 510 may be any type of processor capable of communicating with memory 520, MAC 530, and other functional blocks (not shown). For example, processor 510 may be a microprocessor, digital signal processor (DSP), microcontroller, or the like.
Memory 520 represents an article that includes a machine readable medium. For example, memory 520 represents a random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), flash memory, or any other type of article that includes a medium readable by processor 510. Memory 520 may store instructions for performing software driven tasks. Memory 520 may also store data associated with the operation of system 500.
Although the various elements of system 500 are shown separate in
Vgs replications circuits, bias circuits, biased transistor circuits, and other embodiments of the present invention can be implemented in many ways. In some embodiments, they are implemented in integrated circuits as part of electronic systems. In some embodiments, design descriptions of the various embodiments of the present invention are included in libraries that enable designers to include them in custom or semi-custom designs. For example, any of the disclosed embodiments can be implemented in a synthesizable hardware design language, such as VHDL or Verilog, and distributed to designers for inclusion in standard cell designs, gate arrays, or the like. Likewise, any embodiment of the present invention can also be represented as a hard macro targeted to a specific manufacturing process. For example, portions of Vgs replication circuit 100 (
Although the present invention has been described in conjunction with certain embodiments, it is to be understood that modifications and variations may be resorted to without departing from the spirit and scope of the invention as those skilled in the art readily understand. Such modifications and variations are considered to be within the scope of the invention and the appended claims.
Number | Name | Date | Kind |
---|---|---|---|
4686387 | Rumelhard | Aug 1987 | A |
4736153 | Kogan | Apr 1988 | A |
4970471 | Taylor | Nov 1990 | A |
5004971 | Fitzpatrick et al. | Apr 1991 | A |
5065043 | Bartling et al. | Nov 1991 | A |
5333093 | Krautschneider et al. | Jul 1994 | A |
6049445 | Gauthier et al. | Apr 2000 | A |
6194943 | Yoshizaki et al. | Feb 2001 | B1 |
6242963 | Su et al. | Jun 2001 | B1 |
6469568 | Toyoyama et al. | Oct 2002 | B2 |
6737909 | Jaussi et al. | May 2004 | B2 |
7161412 | Manganaro | Jan 2007 | B1 |
7202694 | Eberlein | Apr 2007 | B2 |
7202744 | Manganaro | Apr 2007 | B1 |
7256621 | Lih et al. | Aug 2007 | B2 |
7433656 | Kappes et al. | Oct 2008 | B2 |
7551017 | Felder | Jun 2009 | B2 |
20020030533 | De et al. | Mar 2002 | A1 |
20020075724 | Pekny | Jun 2002 | A1 |
Number | Date | Country | |
---|---|---|---|
20080150624 A1 | Jun 2008 | US |