Patent Application
20160027998
The disclosure herein relates generally to magnetoresistive devices and associated interconnect. More particularly, this disclosure relates to vias underlying magnetoresistive devices and the manufacture of such circuit elements.
Magnetoresistive memory devices store information by varying the resistance across the memory device such that a read current through a memory cell in the memory device will result in a voltage drop having a magnitude that is based on the information stored in the memory cell. For example, in certain magnetic memory devices, the voltage drop across a magnetic tunnel junction (MTJ) can be varied based on the relative magnetic states of the magnetic layers within the memory cell. In such memory devices, there is typically a portion of the memory cell that has a fixed magnetic state and another portion that has a free magnetic state that is controlled to be either parallel or antiparallel to the fixed magnetic state. Because the resistance through the memory cell changes based on whether the free portion is parallel or antiparallel to the fixed portion, information can be stored by setting the orientation of the free portion. The information is later retrieved by sensing the orientation of the free portion. Such magnetic memory devices are well known in the art.
Writing to magnetic memory cells can be accomplished by sending a spin-polarized write current through the memory device where the angular momentum carried by the spin-polarized current can change the magnetic state of the free portion. One of ordinary skill in the art understands that such a current can either be directly driven through the memory cell or can be the result of applying one or more voltages, where the applied voltages result in the desired current. Depending on the direction of the current through the memory cell, the resulting magnetization of the free portion will either be parallel or antiparallel to the fixed portion. If the parallel orientation represents a logic “0”, the antiparallel orientation may represent a logic “1”, or vice versa. Thus, the direction of write current flow through the memory cell determines whether the memory cell is written to a first state or a second state. Such memory devices are often referred to as spin torque transfer memory devices. In such memories, the magnitude of the write current is typically greater than the magnitude of a read current used to sense the information stored in the memory cells.
In an array of magnetoresistive memory cells, each memory cell is often coupled to a corresponding selection transistor that allows each memory cell to be individually selected for access. The selection transistor for each memory cell couples to one of the electrodes on either side of the magnetoresistive stack of the memory cell. The selection transistors are often formed underlying the layers in which the memory cells are formed, thereby requiring a via that extends through an interlayer dielectric to establish the electrical connection between each memory cell and its corresponding selection transistor.
Because an MRAM may include thousands or millions of memory cells, reducing the amount of area needed for each memory cell and the associated access circuitry for the memory cell can provide for increased memory cell density. Higher memory cell density allows for greater data storage capacity for the MRAM. Therefore, it is desirable to provide techniques for manufacturing such devices that support increased densities while still ensuring proper device operation and reliability.
The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations.
For simplicity and clarity of illustration, the figures depict the general structure and/or manner of construction of the various embodiments. Descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring other features. Elements in the figures are not necessarily drawn to scale: the dimensions of some features may be exaggerated relative to other elements to assist improve understanding of the example embodiments. For example, one of ordinary skill in the art appreciates that the cross-sectional views are not drawn to scale and should not be viewed as representing proportional relationships between different layers. The cross-sectional views are provided to help illustrate the processing steps performed by simplifying the various layers to show their relative positioning. Moreover, while certain layers and features are illustrated with straight 90-degree edges, in actuality or practice such layers may be more “rounded” and gradually sloping.
The terms “comprise,” “include,” “have” and any variations thereof are used synonymously to denote non-exclusive inclusion. The term “exemplary” is used in the sense of “example,” rather than “ideal.”
During the course of this description, like numbers may be used to identify like elements according to the different figures that illustrate the various exemplary embodiments.
For the sake of brevity, conventional techniques related to semiconductor processing may not be described in detail herein. The exemplary embodiments may be fabricated using known lithographic processes. The fabrication of integrated circuits, microelectronic devices, micro electro mechanical devices, microfluidic devices, and photonic devices involves the creation of several layers of materials that interact in some fashion. One or more of these layers may be patterned so various regions of the layer have different electrical or other characteristics, which may be interconnected within the layer or to other layers to create electrical components and circuits. These regions may be created by selectively introducing or removing various materials. The patterns that define such regions are often created by lithographic processes. For example, a layer of photoresist is applied onto a layer overlying a wafer substrate. A photo mask (containing clear and opaque areas) is used to selectively expose the photoresist by a form of radiation, such as ultraviolet light, electrons, or x-rays. Either the photoresist exposed to the radiation, or that not exposed to the radiation, is removed by the application of a developer. An etch may then be applied to the underlying layer not protected by the remaining resist such that the layer overlying the substrate is patterned. Alternatively, an additive process can be used in which a structure is built up using the photoresist as a template.
There are many inventions described and illustrated herein, as well as many aspects and embodiments of those inventions. In one aspect, the described embodiments relate to, among other things, methods of manufacturing a magnetoresistive-based device having one or more electrically conductive electrodes or conductors on either side of a magnetoresistive stack. As described in further detail below, the magnetoresistive stack may include many different layers of material, where some of the layers include magnetic materials, whereas others do not. In some embodiments, the methods of manufacturing include forming the layers for the magnetoresistive device and then masking and etching those layers to produce a magnetic tunnel junction (MTJ) device. Examples of MTJ devices include transducers such as electromagnetic sensors as well as memory cells.
Magnetoresistive devices are typically formed to include a top electrode and a bottom electrode that permit access to the device by allowing for connectivity to other circuit elements. In the example of a magnetic memory (MRAM) cell, one of the electrodes may be coupled to a bit line, whereas the other is coupled to a sense line. A selection transistor may be included between one of the electrodes and the bit or sense line to allow for selection/de-selection of the particular memory cell. The coupling to the electrodes may be accomplished using vias, which are interlayer holes within interlayer dielectric material of the device structure that are filled with conductive material, thereby allowing electrical current to pass between the layers joined by the via.
Within the magnetoresistive device, a set of layers is included between the electrodes, where the set of layers may be referred to as the “magnetoresistive stack.” In a magnetoresistive device that includes a magnetic tunnel junction (MTJ), the magnetoresistive stack includes a fixed layer and a free layer on either side of a dielectric layer that forms a tunnel junction. In some embodiments, the fixed layer achieves its fixed magnetization based on interaction with an antiferromagnetic material. In other embodiments, the fixed magnetization may be achieved through other means, including the manner in which the fixed layer was formed, shape anisotropy, etc. In manufacturing such magnetoresistive devices, a set of layers is first deposited on the wafer and then patterned and etched in multiple steps to define the electrodes, the various layers in the magnetoresistive stack, and any underlying and overlying connections and circuits.
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As disclosed herein, by only partially filling the via underlying the bottom electrode with conductive material such as copper and then filling the remaining portion with the material used to form the bottom electrode, problems associated with positioning the via directly under the magnetoresistive stack are avoided, thereby enabling placement of the via in vertical alignment with the stack and top electrode. By positioning the stack directly over the via, area requirements are reduced, thereby allowing for increased densities in applications such as MRAMs.
In addition to the barrier layer 130, a seed layer may also be formed within the hole 122. The seed layer includes seed material corresponding to the electrically conductive material that is used to partially fill the via hole 122. For example, if the lower portion of the via hole 122 is to be filled with copper, a seed layer of copper may be deposited after or with the barrier layer 130. The seed layer is intended to facilitate better deposition/plating of the conductive material within the via hole 122. In some embodiments a seed layer may not be required, and the via can be filled using electroless plating of material such as ruthenium.
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In some embodiments, the conductive layer 152 may be made up of a plurality of layers. For example, a first material may form a lower portion of conductive layer 152, while a second material overlying the first material forms an upper portion of the bottom electrode.
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The magnetoresistive stack may include a number of different layers of both magnetic and nonmagnetic material. For example, the layers of the stack may include multiple layers of magnetic material, dielectric layers that provide one or more tunnel barriers or diffusion barriers, coupling layers between layers of magnetic material that provide for ferromagnetic or antiferromagnetic coupling, one or more layers of anti-ferromagnetic material, as well as other layers utilized in magnetoresistive stacks as currently known or later developed. In one example, the magnetoresistive stack may include a lower layer of magnetic material, an upper layer of magnetic material, and a dielectric layer providing a tunnel barrier between the upper and lower layers of magnetic material. The lower layer of magnetic material may include a set of layers forming a synthetic antiferromagnetic structure (SAF), and the upper layer of magnetic material may include a set of layers corresponding to a synthetic ferromagnetic structure (SYF). In another embodiment, the lower layer of magnetic material may include a SAF structure as well as a layer of antiferromagnetic material that provides a reference magnetic field for the SAF structure. Notably, each of the layers included in the magnetoresistive device may be a composite layer that includes multiple sub-layers. In other embodiments, the magnetoresistive stack may include multiple SAFs, SYFs, and tunnel barriers in addition to the other layers, where the materials and structures are arranged in various combinations and permutations now known or later developed.
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At 204, a barrier layer is deposited in the hole formed at 202. The barrier layer is intended to prevent diffusion of later deposited materials. For example, a barrier layer or tantalum and/or tantalum nitride may be used to prevent diffusion of later-deposited copper used to partially fill the via, where diffusion of the copper into the surrounding materials may negatively impact device operation. As such, the barrier layer material may be selected based on the material first used to partially fill the via such that it serves a proper barrier to that material.
At 206 a seed layer is deposited over the barrier layer within the whole. The seed layer serves to facilitate subsequent deposition/plating of the conductive material that partially fills the via hole. For example, if copper is used to fill the lower portion of the via hole, a copper seed layer is deposited at 206. In some embodiments, the seed layer and barrier layer may be deposited together in a single step. In other embodiments, only the seed layer or only the barrier layer may be deposited.
At 208, the whole is partially filled with a first conductive material to form a partially filled via hole. The material selected to partially fill the hole may be a metal such as copper, ruthenium, tungsten, or various combinations or alloys thereof After partially filling the via hole at 208, a lower layer of conductive material is deposited at 210. The lower layer of conductive material fills in the remaining unfilled portion of the partially filled via hole. Deposition of the lower layer of conductive material can include chemical vapor deposition such that a good level of material uniformity is achieved. Materials included in the lower layer of conductive material can include one or more of tantalum, tantalum nitride, ruthenium, titanium, titanium nitride, and tungsten. The lower layer of conductive material may include alloys or composite layers where multiple materials are included. For example, the lower layer of electrically conductive material can include a layer of tantalum over a layer of tantalum nitride.
At 212, the lower layer of conductive material is polished to produce a generally planar upper surface of the lower layer of conductive material. The polishing may be done using chemical mechanical polishing. As noted above, a planar upper surface of the lower layer of conductive material provides a good base upon which to form subsequent layers corresponding to the magnetoresistive device. As also noted above, the polishing performed at 212 may include removal of all of the lower layer of conductive material outside of the via hole. In such embodiments, the generally planar upper surface of the lower layer of conductive material corresponds to an upper surface of the interlayer dielectric. An example of such an embodiment is shown in
At 214, a plurality of layers corresponding to the magnetoresistive stack are deposited over the lower layer of conductive material. At 216 an upper layer of conductive material is deposited over the plurality of layers corresponding to the magnetoresistive stack. At 218, the upper layer of conductive material is etched to form a top electrode. At 220, the plurality of layers corresponding to the magnetoresistive stack are etched to form the magnetoresistive stack. In some embodiments, the top electrode and magnetoresistive stack are patterned and defined through etching such that they lie directly over the via. By positioning the magnetoresistive stack directly above the via, the area required to support the magnetoresistive device and corresponding via is reduced in comparison to that required when the magnetoresistive stack is offset from the via as depicted and described with respect to
At 222, after the top electrode and magnetoresistive stack have been defined by etching, the lower layer of electrically conductive material is etched to form the bottom electrode. As noted above, depending on how much of the lower layer of conductive material is left behind during polishing at 212, the entirety of the bottom electrode may be included within the via, or, in other embodiments, some aspect of the bottom electrode may extend above the via. Including a portion of the bottom electrode within the via, the underlying material (e.g. copper) is protected during etching operations corresponding to formation of the magnetoresistive device. Additional advantages in terms of area reduction are realized by positioning the magnetoresistive device directly over the via.
Although the described exemplary embodiments disclosed herein are directed to various magnetoresistive-based devices and methods for making same, the present disclosure is not necessarily limited to the exemplary embodiments, which illustrate inventive aspects that are applicable to a wide variety of semiconductor processes and/or devices. Thus, the particular embodiments disclosed above are illustrative only and should not be taken as limitations, as the embodiments may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Accordingly, the foregoing description is not intended to limit the disclosure to the particular form set forth, but on the contrary, is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the inventions as defined by the appended claims so that those skilled in the art should understand that they can make various changes, substitutions and alterations without departing from the spirit and scope of the inventions in their broadest form.
