Patent Application
20150117536
Computing systems have made significant contributions toward the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous devices, such as desktop personal computers (PCs), laptop PCs, tablet PCs, netbooks, smart phones, servers, and the like have facilitated increased productivity and reduced costs in communicating and analyzing data in most areas of entertainment, education, business, and science. One common aspect of conventional computing, devices is the encoding and decoding of audio/video content.
In conventional audio/video encoders and decoders the data stream typically is processed by a number of processing stages. Some stages operate serially on various divisions/grouping of the hit streams, while other stages can operate on the bit stream in a parallel manner. In one or more processing stages, there is typically a high data dependence in the audio/video bit stream that cause one or more processing stages to be a bottleneck in the audio/video encoding and/or decoding process. Accordingly, there is a continuing need for improved audio/video encoding and/or decoding techniques.
The present technology may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the present technology directed toward Advanced Video Coding (AVC) decoding techniques.
In one embodiment, an AVC decoder includes a plurality of parsers, a plurality of parser buffers, and a decoder. Each parser buffer is communicatively coupled to a respective parser. Each parser parses a set of alternating slices of one or more frames of audio/video data, Each parser buffer buffers the set of alternating slices of the one or more frames of audio/video data from a respective one of the plurality of parsers. The decoder decodes the parsed slices of one or more frames of audio/video data alternatingly from the plurality of parser buffers.
In another embodiment, AVC decoding includes parsing a set of alternating slices of one or more picture frames. The other set of alternating slices of the one or more picture frames are parsed separately from the set of alternating slices. The parsed other set of alternating slices are buffered separately from the parsed set of alternating slices. The buffered parsed slices are alternatingly decoded from the buffered parsed set of alternating slices and the buffered parsed other set of alternating slices.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
Embodiments of the present technology are illustrated by way of example and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
Reference will now be made in detail to the embodiments of the present technology, examples of which are illustrated in the accompanying drawings. While the present technology will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. However, it is understood that the present technology may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present technology.
Some embodiments of the present technology which follow are presented in terms of routines, modules, logic blocks, and other symbolic representations of operations on data within one or more electronic devices. The descriptions and representations are the means used by those skilled in the art to most effectively convey the substance of their work to others skilled in the art. A routine, module, logic block and/or the like, is herein, and generally, conceived to be a self-consistent sequence of processes or instructions leading to a desired result. The processes are those including physical manipulations of physical quantities. Usually, though not necessarily, these physical manipulations take the form of electric or magnetic signals capable of being stored, transferred, compared and otherwise manipulated in an electronic device. For reasons of convenience, and with reference to common usage, these signals are referred to as data, bits, values, elements, symbols, characters, terms, numbers, strings, and/or the like with reference to embodiments of the present technology.
It should be borne in mind, however, that all of these terms are to be interpreted as referencing physical manipulations and quantities and are merely convenient labels and are to be interpreted further in view of terms commonly used in the art. Unless specifically stated otherwise as apparent from the following discussion, it is understood that through discussions of the present technology, discussions utilizing the terms such as “receiving,” and/or the like, refer to the actions and processes of an electronic device such as an electronic computing device that manipulates and transforms data. The data is represented as physical (e.g., electronic) quantities within the electronic device's logic circuits, registers, memories and/or the like, and is transformed into other data similarly represented as physical quantities within the electronic device.
In this application, the use of the disjunctive is intended to include the conjunctive. The use of definite or indefinite articles is not intended to indicate cardinality. In particular, a reference to “the” object or “a” object is intended to denote also one of a possible plurality of such objects. It is also to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.
Referring to
The AVC decoder includes an entropy decoder block 110, a reordering block 115, an inverse quantizer block 120, an inverse transform block 125, an adder block 130, switching block 135, an intra prediction block 140, a motion compensation block 145, and filter block 150. Each 4×4 block of residual data 105 is entropy decoded 110. After reordering 115, inverse quantization 120, and inverse transform 125, the decoder adds 130 each group of 4×4 residual data with the predicted pixel values of inter prediction 140 or intra prediction 145 to reconstruct the 4×4 block 160, in accordance with the switching block 135, from one or more reference frames 155 and the network abstraction layer (NAL) residual data 105. One or more previously encoded frames 155 may be utilized by the motion compensation block 145 to generate the inter prediction values. The macroblock is reconstructed by combining the reconstructed macroblock row by row, and the decoder 100 can obtain the reconstructed frame after performing loopfiltering 150.
Referring now to
The processes of the entropy decoding module 210 and MV module 215 have a strong data dependency. As a result of the strong data dependency, the decoding order is serial in a slice. However, the other modules can be treated as parallel. In the conventional art, most entropy decoder modules are the decoding bottleneck when decoding high bitrate video content.
To simplify the description, we refer to the entropy decoder (VLD) module 210, and optionally the MV module 215 as the parser stage, while the other modules 215-235 are referred to as the decoder stage. Referring now to
Referring now to
Referring now to
Referring now to
The AVC decoder 500 may parse a set of alternating slices of one or more picture frames by a first parser 510, at 610. Substantially in parallel to parsing the set of alternating slices, the other set of alternating slices of the one or more picture frames may be parsed by a second parser 520, at 620. For example, as illustrated in
Each slice of each frame parsed by the first parser 510 is buffered by the first parser buffer 530, at 630. Similarly, each slice of each frame parsed by the second parser 520 is buffered by the second parser buffer 540, at 640. The decoder 550 alternating decodes the slices buffered in the first and second parser buffers 530, 540, at 650. For example, the decoder 550 may decode the first slice of the given picture received in the first parser buffer 530, and then the second slice from the second parser buffer 540. The process is repeated by the decoder to decode the third slice in from the first parser buffer 530 and then the forth slice in the second parser buffer 540 as illustrated in
In the other example illustrated in
Embodiments of the present technology advantageously improve performance by isolating the data dependency of video decoding. Embodiments advantageously enable substantially parallel parsing of alternating slice of one or more frames of video or audio/video data. The parallel parsing advantageously reduces processing bottle necks in AVC decoders.
The foregoing descriptions of specific embodiments of the present technology have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the present technology and its practical application, to thereby enable others skilled in the art to best utilize the present technology and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.
