Claims
- 1. A video display processor comprising:
- a memory port for reading and writing a plurality of display data from an external memory, said external memory further storing data corresponding to a sprite horizontal location, a sprite vertical location, a sprite pattern and sprite color data for each of a plurality of mobile patterns of a predetermined size in pixels smaller than said video display, said sprite data including a single bit for each pixel of a horizontal extent of each horizontal line of said corresponding mobile pattern;
- a graphics processor connected to said memory port for sequentially reading display data from the external memory via said memory port corresponding to respective pixels of a raster scan video display;
- a plurality of N sprite registers, each of said sprite registers storing a sprite horizontal location, a sprite pattern and sprite color data for a corresponding mobile pattern, each of said sprite registers outputting said sprite color data if said sprite pattern bit corresponding to a current horizontal position of said raster scan of a current horizontal line of said video display has a first digital state, and not outputting said sprite color data if said sprite pattern bit corresponding to the current horizontal position of the current horizontal line of said raster scan of said video display has a second digital state;
- a sprite control logic connected to said memory port and said at least one sprite register for determining if a next horizontal line of said raster scan of said video display includes any mobile pattern and for reading a sprite horizontal location, a sprite pattern and sprite color data for each of up to N such mobile patterns from the external memory and storing said read sprite horizontal location, said read sprite pattern and said read sprite color data in a corresponding sprite register;
- an additional sprite status flag connected to said sprite control logic, said additional sprite status flag set to a predetermined state whenever said sprite control logic determines said next horizontal line of said raster scan video display includes more than N mobile patterns; and
- a display priority logic connected to said graphics processor and said plurality of sprite registers, said display priority logic outputting said display data from said graphics processor when none of said plurality of sprite registers output sprite display data and outputting said sprite display data from a sprite register having a highest priority in a predetermined priority of sprites when any of said plurality of sprite registers outputs sprite display data.
- 2. The video display processor of claim 1, wherein:
- said external memory further stores sprite group data for each of said plurality of mobile patterns;
- each of said plurality of sprite registers stores sprite group data for said corresponding mobile pattern; and
- said video display processor further comprises a sprite coincidence detector connected to said plurality of sprite registers for generating an indication of said sprite, group data of any of said plurality of sprite registers whose mobile pattern has at least one pixel overlapping with the mobile pattern of at least one pixel of another sprite register.
- 3. The video display processor of claim 2, further comprising:
- a sprite coincidence register having a bit corresponding to each sprite group; and
- said sprite coincidence detector is further connected to said sprite coincidence register and generates said indication of said sprite group data by setting said bit within said sprite coincidence register corresponding to said sprite group of each overlapping mobile pattern.
- 4. The video display processor of claim 3, further comprising:
- an external processor port connected to said sprite coincidence register, said external processor port transmitting contents of said sprite coincidence register to an external processor upon receipt of a sprite coincidence register read request.
- 5. The video display processor of claim 4, wherein:
- said external processor port resets each bit of said sprite coincidence register following transmission of said contents upon receipt of said sprite coincidence register read request.
- 6. The video display processor of claim 1, wherein:
- said display data recalled from the external memory by said graphics processor consists of color data indicative of a color to be displayed; and
- said sprite display data stored in each of said plurality of sprite registers consists of sprite color data indicative of a color to be displayed.
- 7. The video display processor of claim 1, further comprising:
- a color palette connected to said display priority logic, said color palette including an input receiving color data output from said display priority logic, a plurality of color palette registers each storing a color code wherein the number of colors specifiable by said color codes exceed the number of said color palette registers and an output, said color palette outputting a color code via said output corresponding to color data received at said input of said color palette; and
- a digital to analog converter having an input connected to said output of said color palette and an output, said digital to analog converter outputting at least one analog color signal corresponding to color codes received at said input of said digital to analog converter.
- 8. The video display processor of claim 7, further comprising:
- an external processor port connected to said sprite coincidence register and said color palette registers, said external processor port transmitting contents of said spite coincidence register to an external processor upon receipt of a sprite coincidence register read request and permitting an external processor to write color codes into each of said color palette registers.
- 9. The video display processor of claim 1, further comprising:
- an external processor port connected to said additional sprite status flag, said external processor port transmitting contents of said additional sprite status flag to an external processor upon receipt of a additional sprite status flag read request.
- 10. The video display processor of claim 9, wherein:
- said external processor port resets said additional sprite status flag to a state opposite said predetermined state following transmission of said contents upon receipt of said additional sprite status flag read request.
- 11. The video display processor of claim 1, further comprising:
- a sprite coincidence flag connected to said sprite coincidence detector, said sprite coincidence flag set to a predetermined state whenever said sprite coincidence detector indicates the mobile pattern of one of said plurality of sprite registers has at least one pixel overlapping with the mobile pattern of at least one pixel of another sprite register;
- a multiple bit status register, said additional sprite status flag and said sprite coincidence flag consisting of respective bits of said status register;
- an external processor port connected to said status register, said external processor port transmitting contents of said status register to an external processor upon receipt of a status register read request.
- 12. The video display processor of claim 11, wherein:
- said external processor port resets said bits of said status register corresponding to said additional sprite status flag and said sprite coincidence flag to a state opposite said predetermined state following transmission of said contents upon receipt of said status register read request.
- 13. The video display processor of claim 11, wherein:
- each of the mobile patterns has a predetermined sprite number, associated therewith;
- said sprite control logic reads said sprite horizontal location and said sprite color data for each of up to N such mobile patterns from the external memory for each horizontal line in order of respective horizontal locations;
- said video display processor further comprising an additional sprite number register connected to said sprite control logic, said additional sprite number register loaded with a number corresponding to the sprite number of the N+1st mobile pattern on said next horizontal line whenever said sprite control logic determines said next horizontal line of said raster scan video display includes more than N mobile patterns.
- 14. The video display processor of claim 13, wherein:
- there are thirty two possible mobile patterns; and
- said additional sprite number register consists of 5 bits.
- 15. The video display processor of claim 13, further comprising:
- an external processor port connected to said additional sprite number register, said external processor port transmitting contents of said additional sprite number register to an external processor upon receipt of a additional sprite number register read request.
- 16. The video display processor of claim 1, further comprising:
- a sprite coincidence flag connected to said sprite coincidence detector, said sprite coincidence flag set to a predetermined state whenever said sprite coincidence detector indicates the mobile pattern of one of said plurality of sprite registers has at least one pixel overlapping with the mobile pattern of at least one pixel of another sprite register;
- a multiple bit status register, said additional sprite status flag, said additional sprite number register and said sprite coincidence flag consisting of respective bits of said status register;
- an external processor port connected to said status register, said external processor port transmitting contents of said status register to an external processor upon receipt of a status register read request.
- 17. The video display processor of claim 16, wherein:
- said external processor port resets said bits of said status register corresponding to said additional sprite status flag and said sprite coincidence flag to a state opposite said predetermined state following transmission of said contents upon receipt of said status register read request.
- 18. The video display processor of claim 1, wherein:
- said plurality of N sprite registers consists of 10 sprite registers; and
- said additional sprite status flag being set to said predetermined state whenever said sprite control logic determines said next horizontal line of said raster scan video display includes 11 or more mobile patterns.
- 19. A video display system comprising:
- a host processor;
- a memory for storing display data and data corresponding to a sprite horizontal location, a sprite vertical location, a sprite pattern and sprite color data for each of a plurality of mobile patterns of a predetermined size in pixels smaller than said video display;
- a video display processor disposed on a single integrated circuit including
- a memory port for reading data from and writing data to said memory,
- a graphics processor connected to said memory port for sequentially reading display data from the external memory via said memory port corresponding to respective pixels of a raster scan video display,
- a plurality of N sprite registers, each of said sprite registers storing a sprite horizontal location, a sprite pattern, a sprite pattern and sprite color data for a corresponding mobile pattern, each of said sprite registers outputting said sprite color data if said sprite pattern bit corresponding to a current horizontal position of said raster scan of a current horizontal line of said video display has a first digital state, and not outputting said sprite color data if said sprite pattern bit corresponding to the current horizontal position of the current horizontal line of said raster scan of said video display has a second digital state,
- a sprite control logic connected to said memory and said at least one sprite register for determining if a next horizontal line of said raster scan of said video display includes any mobile pattern and for reading a sprite horizontal location, a sprite pattern and sprite color data for each of up to N such mobile patterns from the external memory and storing said read sprite horizontal location, said read sprite pattern and said read sprite color data in a corresponding sprite register,
- an additional sprite status flag connected to said sprite control logic, said additional sprite status flag set to a predetermined state whenever said sprite control logic determines said next horizontal line of said raster scan video display includes more than N mobile patterns,
- a display priority logic connected to said graphics processor and said plurality of sprite registers, said display priority logic outputting said display data from said graphics processor when none of said plurality of sprite registers output sprite display data and outputting said sprite display data from a sprite register having the highest priority in a predetermined priority of sprites when any of said plurality of sprite registers outputs sprite display data,
- a host processor port connected to said host processor and said sprite coincidence register, said host processor port transmitting contents of said additional sprite status flag to said host processor upon receipt of a additional sprite status flag read request; and
- a video display connected to said display priority logic for generating a visual display corresponding to said display data output by said display priority logic.
- 20. The video display system of claim 19, further comprising:
- said memory further stores sprite group data for each of said plurality of mobile patterns;
- said video display processor further including
- each of said sprite registers stores sprite group data for said corresponding mobile pattern,
- a sprite coincidence register having a bit corresponding to each sprite group,
- a sprite coincidence detector connected to said plurality of sprite registers and said sprite coincidence register, said sprite coincidence detector for generating an indication of said sprite group data of any of said plurality of sprite registers whose mobile pattern has at least one pixel overlapping with the mobile pattern of at least one pixel of another sprite register by setting said bit within said sprite coincidence register corresponding to said sprite group of each overlapping mobile pattern.
- 21. The video display system of claim 20, wherein:
- said host processor port resets each bit of said sprite coincidence register following transmission of said contents upon receipt of said sprite coincidence register read request.
- 22. The video display system of claim 19, wherein:
- said display data stored in said memory consists of color data indicative of a color to be displayed; and
- said sprite display data stored in each of said plurality of sprite registers consists of sprite color data indicative of a color to be displayed.
- 23. The video display system of claim 19, wherein:
- a color palette connected to said display priority logic, said color palette including an input receiving color data output from said display priority logic, a plurality of color palette registers each storing a color code wherein the number of colors specifiable by said color codes exceed the number of said color palette registers and an output, said color palette outputting a color code via said output corresponding to color data received at said input of said color palette, and
- a digital to analog converter having an input connected to said output of said color palette and an output, said digital to analog converter outputting at least one analog color signal corresponding to color codes received at said input of said digital to analog converter.
- 24. The video display system of claim 23, wherein:
- said host processor port further connected to said color palette registers permitting said host processor to write color codes into each of said color palette registers.
- 25. The video display system of claim 19, wherein:
- said video display processor further includes an external processor port connected to said additional sprite status flag, said external processor port transmitting contents of said additional sprite status flag to an external processor upon receipt of a additional sprite status flag read request.
- 26. The video display system of claim 25, wherein:
- said external processor port resets said additional sprite status flag to a state opposite said predetermined state following transmission of said contents upon receipt of said additional sprite status flag read request.
- 27. The video display system of claim 19, wherein:
- said video display processor further includes
- a sprite coincidence flag connected to said sprite coincidence detector, said sprite coincidence flag set to a predetermined state whenever said sprite coincidence detector indicates the mobile pattern of one of said plurality of sprite registers has at least one pixel overlapping with the mobile pattern of at least one pixel of another sprite register,
- a multiple bit status register, said additional sprite status flag and said sprite coincidence flag consisting of respective bits of said status register,
- an external processor port connected to said status register, said external processor port transmitting contents of said status register to an external processor upon receipt of a status register read request.
- 28. The video display system of claim 27, wherein:
- said external processor port resets said bits of said status register corresponding to said additional sprite status flag and said sprite coincidence flag to a state opposite said predetermined state following transmission of said contents upon receipt of said status register read request.
- 29. The video display system of claim 27, wherein:
- each of the mobile patterns has a predetermined sprite number associated therewith;
- said sprite control logic reads said sprite horizontal location and said sprite color data for each of up to N such mobile patterns from the external memory for each horizontal line in order of respective horizontal locations;
- said video display processor further including an additional sprite number register connected to said sprite control logic, said additional sprite number register loaded with a number corresponding to the sprite number of the N+1st mobile pattern on said next horizontal line whenever said sprite control logic determines said next horizontal line of said raster scan video display includes more than N mobile patterns.
- 30. The video display system of claim 29, wherein:
- there are thirty two possible mobile patterns; and
- said additional sprite number register consists of 5 bits.
- 31. The video display system of claim 29, wherein:
- said host processor port connected to said additional sprite number register, said host processor port transmitting contents of said additional sprite number register to said host processor upon receipt of a additional sprite number register read request.
- 32. The video display system of claim 31, wherein:
- said video display processor further includes
- a sprite coincidence flag connected to said sprite coincidence detector, said sprite coincidence flag set to a predetermined state whenever said sprite coincidence detector indicates the mobile pattern of one of said plurality of sprite registers has at least one pixel overlapping with the mobile pattern of at least one pixel of another sprite register,
- a multiple bit status register, said additional sprite status flag, said additional sprite number register and said sprite coincidence flag consisting of respective bits of said status register,
- said host processor port connected to said status register, said host processor port transmitting contents of said status register to said host processor upon receipt of a status register read request.
- 33. The video display system of claim 32, wherein:
- said host processor port resets said bits of said status register corresponding to said additional sprite status flag and said sprite coincidence flag to a state opposite said predetermined state following transmission of said contents upon receipt of said status register read request.
- 34. The video display system of claim 19, wherein:
- said plurality of N sprite registers consists of 10 sprite registers; and
- said additional sprite status flag being set to said predetermined state whenever said sprite control logic determines said next horizontal line of said raster scan video display includes 11 or more mobile patterns.
RELATED APPLICATIONS
This application is a continuation of application Ser. No. 08/103,498 filed Aug. 6, 1993, now U.S. Pat. No. 5,552,804, which is a divisional of application Ser. No. 07/803,236 filed Dec. 5, 1991 now U.S. Pat. No. 5,379,049, which is a continuation of application Ser. No. 07/455,869 filed Dec. 18, 1989 now U.S. Pat. No. 5,089,811, which is a continuation of application Ser. No. 07/262,176 filed Oct. 20, 1988 now abandoned, which is a continuation of application Ser. No. 07/38,476 filed Apr. 13, 1987 now abandoned, which is a continuation of Ser. No. 06/600,921 filed Apr. 16, 1984 now abandoned.
US Referenced Citations (3)
Divisions (1)
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803236 |
Dec 1991 |
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Continuations (5)
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103498 |
Aug 1993 |
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455869 |
Dec 1989 |
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262176 |
Oct 1988 |
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38476 |
Apr 1987 |
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600921 |
Apr 1984 |
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