Patent Application
20100061696
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2008-232389, filed on Sep. 10, 2008, the entire contents of which are incorporated herein by reference.
This invention relates to a video recording and playback apparatus which records and plays back video contents with reference to external synchronizing signal, such as a black burst signal (hereinafter referred to as “BB signal”).
As for a video recording and playback apparatus which uses a hard disk drive unit, a flash memory, or another type of readable/writable medium as a storage unit, it is common to acquire an external synchronizing signal, such as a BB signal, from an external source and to operate the whole apparatus with reference to the external synchronizing signal. This technique is used more frequently, when the video recording and playback apparatus has a plurality of recording channels and playback channels (see JP, P2006-301748A).
This kind of video recording and playback apparatus has a recording unit and a playback unit. The recording unit receives a video data and records the received video data on the storage unit. The playback unit plays back the video data read out from the storage unit to output the video data which is played back. The video recording and playback apparatus operates the recording unit and the playback unit according to a cycle of the external synchronizing signal. At this time, the video recording and playback apparatus transmits the video data from the recording unit to the storage unit and a transmission of the video data from the storage unit to the playback unit in one frame with reference to the frame synchronizing signal of the external synchronizing signal. Thereby, both operations of the recording and the playback in the video recording and playback apparatus are guaranteed.
When the recording unit receives the video data asynchronous with the external synchronizing signal or an internal synchronizing signal, the recording unit and the playback unit become asynchronous with each other and there is a possibility that a breakdown may arise in data transmission due to any differences in synchronizing frequencies. Accordingly, a conventional video recording and playback apparatus installs a synchronous conversion circuit (frame synchronizer) in the recording unit and makes the synchronizing frequency of the recording unit coincide with the synchronizing frequency of the playback unit.
However, the synchronous conversion circuit is expensive and large.
As mentioned above, in a conventional video recording and playback apparatus, when the recording unit and the playback unit are asynchronous, the synchronous conversion circuit must be installed in the recording unit in order to perform recording and playback normally. Accordingly, the video recording and playback apparatus has an increase in cost and volume.
A purpose of the present invention is to provide a video recording and playback apparatus which can perform recording operation and playback operation without installing a synchronous conversion circuit even if the recording unit and the playback unit are asynchronous with each other.
The video recording and playback apparatus concerning the embodiment has an input processing unit, an input buffer, an storage processing unit, an output buffer, and an output processing unit. The input processing unit is configured to receive data containing video data which is inputted at a 1st rate and has a 1st synchronizing signal, and an input processing unit is configured to code the video data received and to output the video data coded. The input buffer is configured to temporarily hold the coded video data outputted by the input processing unit and to output the video data at a 2nd rate which is faster than the 1st rate. The storage processing unit is configured to store the coded video data which is outputted from the input buffer and to read out coded other video data stored at a 3rd rate which is faster than the 1st rate. The output buffer is configured to hold temporarily the coded other video data read from the storage processing unit and to output the coded other video data held. The output processing unit is configured to decode the coded other video data outputted from the output buffer according to a cycle of the 2nd synchronizing signal and to output the other video data.
Hereafter, the video recording and playback apparatus according to the embodiments of the present invention is described in detail with reference to the drawings.
Video recording and playback apparatus 1 has synchronizing signal unit 10, recording unit 14, storage processing unit 15, and playback unit 16.
Synchronizing signal unit 10 chooses either a synchronizing signal of the SDI signal which is detected by input synchronizing signal detector 11 or a synchronizing signal which is generated by synchronizing signal generator unit 12 using switch 13 and outputs it to recording unit 14. Hereinafter, the synchronizing signal outputted from input synchronizing signal detector 11 is called an input synchronizing signal. The synchronizing signal outputted from synchronizing signal generator unit 12 is also called an output synchronizing signal.
Recording unit 14 receives the SDI signal and the synchronizing signal outputted from switch 13, separates video data from the SDI signal, and codes the separated video data with reference to the synchronizing signal. Recording unit 14 supplies the coded video data to storage processing unit 15 via bus 19 based on the output synchronizing signal.
Storage processing unit 15 stores the coded video data, reads a coded video data stored and outputs the coded video data to playback unit 16 via bus 19 based on the output synchronizing signal.
Playback unit 16 receives the coded video data and the output synchronizing signal and it then decodes the coded video data based on the output synchronizing signal to play back the video data.
Next, each unit is explained.
Synchronizing signal unit 10 has input synchronizing signal detector 11, synchronizing signal generator unit 12, and synchronizing signal switching unit 20. Synchronizing signal switching unit 20 has switch 13.
Input synchronizing signal detector 11 detects the synchronizing signal from the SDI signal received and outputs the synchronizing signal to switch 13. The synchronizing signal (hereinafter referred to as “input synchronizing signal”) outputted from input synchronizing signal detector 11 includes clock CLK-R and frame synchronizing signal FRAME-R.
Synchronizing signal generator unit 12 has external synchronizing signal detector 121 and internal synchronizing signal generator 122, as shown in
Synchronizing signal switching unit 20 outputs either the input synchronizing signal or the output synchronizing signal selectively selected by switch 13. Selection operation of switch 13 is performed by a user of the video recording and playback apparatus 1. When the input synchronizing signal and the output synchronizing signal synchronize, switch 13 outputs the output synchronizing signal. When the input synchronizing signal and the output synchronizing signal do not synchronize, switch 13 selects to output the input synchronizing signal.
Recording unit 14 has input processing unit 141 and input buffer 142.
Input processing unit 141 receives the SDI signal and the synchronizing signal outputted from switch 13. Input processing unit 141 separates video data, voice data, etc from the SDI signal and extracts only the necessary parts from the data using the synchronizing signal outputted from switch 13.
Input processing unit 141 further codes the effective part according to a predetermined compression standards such as MPEG (Moving Picture Experts Group) and outputs the coded video data. The coded video data is held temporarily in input buffer 142 with reference to the clock (CLK-R or CLK-P) of the synchronizing signal outputted from switch 13. Holding of the data in input buffer 142 is delayed several frames to coding by input processing unit 141. As for holding in input buffer 142, one frame of coded video data is written within one frame using the clock of the synchronizing signal outputted from switch 13. During this writing, a counter (not shown in the Figs.) counts the number of the video data stored in input buffer 142 within 1 frame of frame synchronizing signal FRAME-P of the output synchronizing signal. The video data number is obtained by counting the number of valid data of the clock of the synchronizing signal outputted from switch 13 within 1 frame of frame synchronizing signal FRAME-P.
Input buffer 142 reads out the held coded video data in about one-fourth time of 1 frame time utilizing a clock of a clock frequency 4 times the frequency of clock CLK-P, for example. The coded video data which is read out this time is the video data stored in input buffer 142 within one cycle of FRAME-P (not FRAME-R) of the output synchronizing signal, and the video data of the number counted by the counter is read. The coded video data which is read out is outputted to storage processing unit 15 via bus 19. Although the clock used for read out of the coded video data from input buffer 142 is generated based on clock CLK-P, the clock may not be restricted to this, as it may also be a clock asynchronous to clock CLK-P.
Storage processing unit 15 has a storage unit (not shown) which comprises a hard disk drive, a flash memory, or other medium used as a storage unit inside.
Storage processing unit 15 stores the coded video data which is outputted from input buffer 142 in the storage unit. Storage processing unit 15 reads out other coded video data stored in the storage unit and transfers the read coded video data to output buffer 161 via bus 19. Writing the coded video data to the storage unit is performed at the rate which the coded video data is read out from input buffer 142. In reading-out the coded video data from the storage unit, the coded video data corresponding to one frame of frame synchronizing signal FRAME-P is read out with a clock frequency which is 4 times the frequency of clock CLK-P.
Writing and reading-out to storage processing unit 15 are performed within one frame in accordance with the cycle of frame synchronizing signal FRAME-P, and writing is performed after reading-out. At this time, storage processing unit 15 performs writing and reading-out at a rate higher than the transmission rate of the SDI signal inputted into input processing unit 141. Since writing and reading-out are performed at a clock frequency 4 times the frequency of clock CLK-P as mentioned above, writing and read out can be performed at about half of one the frame time of frame synchronizing signal FRAME-P. Writing and reading-out are preformed at predetermined position in one frame of frame synchronizing signal FRAME-P, respectively, so that writing data and reading data do not collide on bus 19.
Transmission of the coded video data from input buffer 142 to storage processing unit 15 does not need to be performed per one frame of frame synchronizing signal FRAME-P, it can be performed per multiple frames.
Playback unit 16 has output buffer 161 and output processing unit 162.
Output buffer 161 holds temporarily the coded video data which is read out from storage processing unit 15 with reference to the clock which reads the video data coded from the storage unit. Output buffer 161 outputs the coded video data held to output processing unit 162 with reference to clock CLK-P of the output synchronizing signal. Output processing unit 162 decodes the coded video data based on clock CLK-P and frame synchronizing signal FRAME-P of the output synchronizing signal to generate the video data, changes the video data into the SDI signal, and outputs the SDI signal externally.
Next, recording and playback operation of video recording and playback apparatus 1 in the above-mentioned constitution is explained.
In the recording operation, input data I1-I5 are inputted into input processing unit 141 in series. Input data I1-I5 are coded one by one by input processing unit 141 with clock CLK-P and frame synchronizing signal FRAME-P. Coded input data I1-I5 is held with a frame period of frame synchronizing signal FRAME-P in input buffer 142 using clock CLK-P. The number of the input data held in input buffer 142 within 1 frame of frame synchronizing signal FRAME-P is counted by the counter. As mentioned above, a frame in which the coded input data is held in input buffer 142 is several frames behind a frame in which the input data is inputted in input processing unit 141.
Coded input data I1-I5 which is held in input buffer 142 within each frame period of frame synchronizing signal FRAME-P is read out and transmitted to storage processing unit 15 via bus 19, using a clock of a clock frequency 4 times the clock frequency of clock CLK-P in each immediately following frame period of frame synchronizing signal FRAME-P. The coded input data which is read out within each frame period is the amount of input data counted by the counter. For example, a frame in which input data I1 coded is read out from input buffer 142 is one frame behind a frame in which input data I1 is held in input buffer 142. Storage processing unit 15 stores transmitted and coded input data I1 in the storage unit.
Thereby, coding of input data I1-I5 in input processing unit 141, holding of coded input data I1-I5 in input buffer 142, reading-out of compressed input data I1-I5 from input buffer 142, and storing of compressed input data I1-I5 to storage processing unit 15 are performed.
In the playback operation, in the frame period of frame synchronizing signal FRAME-P, output data O1 stored in the storage unit is read out from storage processing unit 15 using a clock of a clock frequency 4 times the frequency of clock CLK-P, and output data O1 read out is held in output buffer 161 via bus 19. The held output data I1 is outputted from output buffer 161 to output processing unit 142 in the next frame period using clock CLK-P. Output data O1 is decoded and outputted by output processing unit 162 using clock CLK-P and frame synchronizing signal FRAME-P.
Hereafter, repeating these, output data O1, O2, . . . are read out from storage processing unit 15, are held in output buffer 161, are read out from output buffer 161, are further decoded by output processing unit 162, and decoded output data O1, O2, . . . are outputted from playback unit 16.
When the recording and the playback are performed simultaneously, both writing and reading to storage processing unit 15 are performed within one frame of frame synchronizing signal FRAME-P. Reading-out is performed in the first portion of one frame, and writing is performed continuously. For example, both the reading-out of output data O3 and the writing of coded input data I1 are performed in one frame, and both output data and the coded input data flow in bus 19 during a signal frame period. For this reason, storage processing unit 15 performs writing and reading-out at a rate higher than the transmission rate of the input signal inputted to input processing unit 141. In the embodiment, writing and reading-out are performed by utilizing a clock of a clock frequency 4 times the frequency of clock CLK-P.
Next,
In the recording processing, input data I1-I5 are first inputted into input processing unit 141 one by one. Input data I1-I5 are coded and outputted to input buffer 142 one by one by input processing unit 141 with clock CLK-R of the input synchronizing signal and the frame period of frame synchronizing signal FRAME-R. Coded input data I1-I5 is held temporarily in input buffer 142 with the frame cycle of frame synchronizing signal FRAME-R. The number of the input data held in 1 frame period of frame synchronizing signal FRAME-P in input buffer 142 is counted by the counter.
The input data stored in input buffer 142 in one frame period of frame synchronized signal FRAME-P is read out at clock frequency 4 times the frequency of clock CLK-P according to a cycle of FRAME-P and is transmitted to storage processing unit 15 via bus 19 in series. The coded input data which is read out is the amount of the coded input data counted by the counter. Thereby, the data coded in one frame period of frame synchronizing signal FRAME-P can be taken out. For example, in one frame period of frame synchronizing signal FRAME-P, from input buffer 142, coded input data I1 and a part of coded input data I2 are read out and transmitted to storage processing unit 15 via bus 19. In a following frame period, a remainder of coded input data I2 and a part of coded input data I3 are read out and transmitted to storage processing unit 15.
Thereby, input data IL I2, I3, . . . inputted in input processing unit 141 are coded and coded input data I1, I2, I3, . . . are stored in storage processing unit 15.
In the playback processing, according to the frame cycle of frame synchronizing signal FRAME-P, coded output data O1 which is stored in the storage unit is read out from storage processing unit 15 with a clock frequency 4 times the frequency of clock CLK-P is transmitted to output buffer 161 via bus 19, and is held temporarily in output buffer 161. Output data O1 is outputted from output buffer 161 to output processing unit 162 by clock CLK-P in a subsequent frame period and is decoded and outputted by output processing unit 162 using clock CLK-P and frame synchronizing signal FRAME-P.
Hereafter, repeating these, output data O1, O2, . . . are read out from storage processing unit 15, are held in output buffer 161, are read out from output buffer 161, are further decoded by output processing unit 162, and decoded output data O1, O2, . . . are outputted from playback unit 16.
In this case, since the frame cycle of the input synchronizing signal is smaller than the frame cycle of the output synchronizing signal, reading-out from input buffer 142 is performed in larger amounts of data than that of one frame of the input signal. For this reason, even if the input signal and the output signal are asynchronous, overflow of input buffer 142 dose not occur. Writing and reading-out to storage processing unit 15 are performed at a speed higher than the transmission rate of the input signal, for example 4 times higher, and writing and reading-out are performed at different times in one frame of frame synchronized signal FRAME-P. For this reason, write data and read data do not collide on bus 19.
Next,
In the recording processing, input data I1-I5 are first inputted into input processing unit 14 one by one. Input data I1-I5 are coded and outputted to input buffer 142 one by one by input processing unit 141 with clock CLK-R and the frame period of frame synchronizing signal FRAME-R of the input synchronizing signal. Coded input data I1-I5 are held temporarily in input buffer 142 with the frame cycle of frame synchronizing signal FRAME-R. The number of the input data held in input buffer 142 in 1 frame period of frame synchronizing signal FRAME-P is counted by the counter.
According to the period of frame synchronizing signal FRAME-P of the output synchronizing signal, the input data stored in input buffer 142 in 1 frame period of frame synchronized signal FRAME-P is read out at a clock frequency 4 times the frequency of clock CLK-P one by one and is transmitted to storage processing unit 15 via bus 19. The coded input data which is read out is the amount of the coded input data counted by the counter. Thereby, the data coded in 1 frame period of frame synchronizing signal FRAME-P can be taken out. For example, in one frame of frame synchronizing signal FRAME-P, from input buffer 142, a part of coded input data I1 is read out and is transmitted to storage processing unit 15 via bus 19. In a following frame, a remainder of coded input data I1 and a part of coded input data I2 are read out and are transmitted to storage processing unit 15.
Thereby, input data I1, I2, I3, . . . inputted into input processing unit 141 are coded and coded input data IL I2, I3, . . . are stored in storage processing unit 15.
In the playback processing, according to the frame cycle of frame synchronizing signal FRAME-P, coded output data O1 which is stored in the storage unit is read out from storage processing unit 15 at a clock frequency 4 times the frequency of clock CLK-P and is transmitted to output buffer 161 via bus 19, and is held temporarily in output buffer 161. Output data O1 is outputted from output buffer 161 to output processing unit 162 by clock CLK-P in a following frame period and is decoded and outputted by output processing unit 162 using clock CLK-P and frame synchronizing signal FRAME-P.
Hereafter, repeating these, output data I1, O2, . . . are read out from storage processing unit 15, are held in output buffer 161, are read out from output buffer 161, are further decoded by output processing unit 162, and decoded output data O1, O2, . . . are outputted from playback unit 16.
In this case, since the frame cycle of the input synchronizing signal is larger than the frame cycle of the output synchronizing signal, reading-out from input buffer 142 is performed on data that is smaller than one frame of the input signal. For this reason, even if the input signal and the output signal are asynchronous, underflow of input buffer 142 does not occur. Writing and reading-out to storage processing unit 15 are performed at a speed, for example, 4 times higher than the rate of the input signal. Under these circumstances writing and reading-out are performed at different times during one frame of frame synchronized signal FRAME-P. For this reason, write data and read data do not collide on bus 19.
As mentioned above, in the 1st embodiment, the input data stored in input buffer 142 in the frame period of frame synchronizing signal FRAME-P of the output synchronizing signal which does not relate the input synchronizing signal, is transferred to storage processing unit 15 via bus 19 according to the frame period of the output synchronizing signal. Thereby, since bus 19 transmits the data in an approximately fixed amount according to the transmission rate of the input signal, recording operation and playback operation can be performed simultaneously without causing the breakdown of the data transmission because of the difference in synchronizing frequency.
Therefore, according to the constitution of the 1st embodiment, even if the recording unit and the playback unit are asynchronous, the video recording and playback apparatus can perform recording operation and playback operation without the need of a synchronous conversion circuit.
The video recording and playback apparatus of the present invention is premised on the case where the input signal inputted into recording unit 14 differs from the video data which is read out from storage processing unit 15 to be played back by the playback unit. However, the frequency of the input signal inputted into recording unit 14 is higher than or equal to the frequency of the video data outputted from playback unit 16, the video data can be played back from the recording unit immediately after storing.
Input synchronizing signal detector 11 detects the synchronizing signal of the SDI signal inputted and outputs the synchronizing signal to synchronizing signal switching unit 20. The synchronizing signal outputted includes clock CLK-R and frame synchronizing signal FRAME-R. The synchronizing signal is given to switch 13 and judgment unit 17.
Synchronizing signal generator unit 12 outputs the synchronizing signal synchronized with the synchronizing signal of the BB signal inputted from the outside source when synchronizing signal generator unit 12 detects the BB signal as explained in 1st embodiment. Synchronizing signal generator unit 12 outputs the synchronizing signal generated inside which is asynchronous to the synchronizing signal of the BB signal when synchronizing signal generator unit 12 can not detect the BB signal. Synchronizing signal generator unit 12 outputs the synchronizing signal to synchronizing signal switching unit 20, recording unit 14, storage processing unit 15, and playback unit 16. The synchronizing signal is given to switch 13 and judgment unit 17 in synchronizing signal switching unit 20. The synchronizing signal outputted (output synchronizing signal) includes clock CLK-P and frame synchronizing signal FRAME-P.
Judgment unit 17 receives the input synchronizing signal and the output synchronizing signal and judges whether both signals synchronize. Judgment unit 17 outputs a decision result to control unit 18.
Control unit 18 receives the decision result. When the decision result shows that the input synchronizing signal and the output synchronizing signal do not synchronize, control unit 18 directs switching unit to output the input synchronizing signal. When the decision result shows that the input synchronizing signal and the output synchronizing signal synchronize, control unit 18 directs switch 13 to output the output synchronizing signal.
As for video recording and playback apparatus 1 according to the embodiment 2, the constitution other than synchronizing signal part 10 is the same as that of video recording and playback apparatus 1 shown in embodiment 1.
According to the embodiment 2, like embodiment 1, even if the recording unit and the playback unit are asynchronous, the video recording and playback apparatus which can perform the recording operation and the playback operation without a synchronous conversion circuit. In the 2nd embodiment, control unit 18 controls the change of switch 13 based on the decision result of judgment unit 17. Thereby, when the input synchronizing signal and the output synchronizing signal become asynchronous, switch 13 is automatically changed to output the input synchronizing signal. Therefore, a video recording and playback apparatus with easy operation is provided.
This invention is not limited to the above embodiments. For example, although it is explained in terms where the SDI signal includes the information of the video contents, the information included in the SDI signal is not limited to the information of video content. Even if the SDI signal includes information of voice contents, the video recording and playback apparatus can perform similarly.
Although the above-mentioned embodiment explains the example which uses the BB signal as the external synchronizing signal (the reference signal), the external synchronizing signal is not limited to the BB signal. For example, a tri-level synchronizing signal may be used.
In the above-mentioned embodiment, the internal synchronizing signal generator of the synchronizing signal generator unit synchronizes with the external synchronizing signal the synchronizing signal to generate when the external synchronizing signal exists. However, the synchronizing signal generator unit may be provided with an internal synchronizing generator for exclusive use and a circuit which generates a synchronizing signal directly from the external synchronizing signal, and may change the output from both.
The above-mentioned embodiment explains a situation where the number of input channel and the number of output channel is one each. However, the present invention is not limited to one channel each. The present invention can be applied to a video recording and playback apparatus having two or more input channels and output channels.
Other embodiments or modifications of the present invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and example embodiments be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-232389 | Sep 2008 | JP | national |
