Patent Application
20180308443
The present invention relates to a display device and more particularly to a video signal line drive circuit that drives video signal lines of particularly a display device having a display panel especially having a shape other than a rectangle.
A liquid crystal display device generally includes a liquid crystal panel composed of two insulating glass substrates facing each other. One of the glass substrates is called an array substrate and the other is called a counter substrate. The array substrate has thin film transistors (TFTs), pixel electrodes, etc., formed thereon, and the counter substrate has a counter electrode, color filters, etc., formed thereon. Such a conventional general liquid crystal panel has a rectangular display unit (display region). In the display unit there are formed a plurality of source bus lines (video signal lines), a plurality of gate bus lines (scanning signal lines), and a plurality of pixel formation portions provided at the respective intersections of the plurality of source bus lines and the plurality of gate bus lines. Each pixel formation portion includes a TFT connected at its gate electrode to a gate bus line passing through a corresponding intersection, and connected at its source electrode to a source bus line passing through the intersection; a pixel electrode connected to a drain electrode of the TFT; a counter electrode and an auxiliary capacitance electrode which are provided so as to be shared by the plurality of pixel formation portions; a liquid crystal capacitance formed by the pixel electrode and the counter electrode; and an auxiliary capacitance formed by the pixel electrode and the auxiliary capacitance electrode. By the liquid crystal capacitance and the auxiliary capacitance, a pixel capacitance is formed. In a configuration such as that described above, a pixel capacitance is charged based on a data voltage (video signal) which is received from a source bus line by the source electrode of a TFT when the gate electrode of the TFT receives an active scanning signal from a gate bus line. By thus charging the pixel capacitances in the plurality of pixel formation portions, a desired image is displayed on the display unit.
In a liquid crystal display device such as that described above, luminance non-uniformity may occur due to, for example, the placement of light sources forming a backlight. Hence, conventionally, in order to suppress the occurrence of luminance non-uniformity, a data voltage corresponding to a target display gradation is corrected and the corrected data voltage is applied to a source bus line. An invention of a liquid crystal display device that performs such correction is disclosed in, for example, Japanese Laid-Open Patent Publication No. 2008-70404.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2008-70404
As described above, the conventional general liquid crystal panel has a rectangular display unit (display region). However, in recent years, the development of liquid crystal display devices including a display unit having a shape other than a rectangle, such as a liquid crystal display device for clock application and a liquid crystal display device for in-vehicle application, has progressed. Note that in the following a display device including a display unit having a shape other than a rectangle and including a display panel whose outer shape is also other than a rectangle is referred to as “oddly shaped display”.
Meanwhile, in the oddly shaped display, despite the fact that a target display image is so-called a “solid image” (an image that provides the same color and the same gradation in the entire display unit), the actual display image is an image called vertical gradation (an image whose gradation gradually changes in a horizontal direction). Such abnormal display will be described with reference to
It can be grasped from
An object of the present invention is therefore to provide a source driver (video signal line drive circuit) capable of suppressing the occurrence of abnormal display caused by “the difference in the settling time of a data voltage (to be applied to a source bus line)” depending on location of the source bus lines (video signal lines), and a display device including the source driver.
A first aspect of the present invention is directed to a video signal line drive circuit for driving video signal lines, the video signal line drive circuit including:
a data voltage generating unit configured to generate data voltages corresponding to display gradations;
a number of output amplifiers equal to a number of the video signal lines, the output amplifiers being configured to output the data voltages to the video signal lines;
a storage unit configured to store control values for adjusting settling time of outputs of the data voltages from the output amplifiers; and
a bias current control unit configured to control magnitudes of bias currents of the output amplifiers based on the control values stored in the storage unit.
According to a second aspect of the present invention, in the first aspect of the present invention,
the storage unit stores a number of the control values equal to the number of the video signal lines, and
the bias current control unit controls, on a per video signal line basis, a magnitude of a bias current of a corresponding output amplifier based on a corresponding one of the plurality of control values stored in the storage unit.
A third aspect of the present invention is directed to a display device including:
a display panel having video signal lines; and
a video signal line drive circuit according to a third aspect of the present invention.
According to a fourth aspect of the present invention, in the third aspect of the present invention,
a shape of the display panel is non-rectangular, and
control values are stored in the storage unit such that a bias current control unit increases a magnitude of a bias current more for an output amplifier provided for a video signal line with a longer length.
According to a fifth aspect of the present invention, in the fourth aspect of the present invention,
the shape of the display panel is circular.
According to a sixth aspect of the present invention, in the fourth aspect of the present invention,
the shape of the display panel is circular.
According to a seventh aspect of the present invention, in the fourth aspect of the present invention,
the shape of the display panel is rectangular, and
the control values are stored in the storage unit such that the bias current control unit increases a magnitude of a bias current more for an output amplifier provided for a video signal line whose charging rate is lower when it is assumed that data voltages of a same magnitude are applied to all the video signal lines without controlling magnitudes of bias currents of output amplifiers.
An eighth aspect of the present invention is directed to a method for driving video signal lines by a video signal line drive circuit having a number of output amplifiers equal to a number of video signal lines, the method comprising:
a data voltage generating step of generating data voltages corresponding to display gradations;
a data voltage outputting step of outputting the data voltages to the video signal lines from the output amplifiers; and
a bias current controlling step of controlling magnitudes of bias currents of the output amplifiers based on control values set in advance to adjust settling time of outputs of the data voltages from the output amplifiers.
According to the first aspect of the present invention, the video signal line drive circuit is provided with a storage unit that stores control values for adjusting settling time of outputs of data voltages from the output amplifiers, and a bias current control unit that controls the magnitudes of bias currents of the output amplifiers based on the control values stored in the storage unit, in addition to conventional components. Hence, by suitably storing control values in the storage unit taking into account the load on each video signal line, the magnitude of a bias current of each output amplifier is controlled so as to reduce the difference in the settling time of an output of a data voltage from each output amplifier between the plurality of video signal lines. By this, in a display device including the video signal line drive circuit, the charging rate becomes uniform across the display unit, and the occurrence of abnormal display (display of an image called vertical gradation) is suppressed. As such, the video signal line drive circuit is implemented that can suppress the occurrence of abnormal display caused by “the difference in the settling time of a data voltage (to be applied to a video signal line)” depending on location of the video signal lines.
According to the second aspect of the present invention, on a per video signal line basis, the magnitude of bias current of a corresponding output amplifier is controlled. Hence, the occurrence of abnormal display (display of an image called vertical gradation) is effectively suppressed.
According to the third aspect of the present invention, a display device is implemented that includes a video signal line drive circuit that can suppress the occurrence of abnormal display caused by “the difference in the settling time of a data voltage (to be applied to a video signal line)” depending on location of the video signal lines.
According to the fourth aspect of the present invention, in a display device including a non-rectangular display panel, control values are stored in the storage unit such that a larger bias current flows through an output amplifier provided for a video signal line with a larger load. Hence, the difference in the settling time of an output of a data voltage from each output amplifier between the plurality of video signal lines is reduced. By this, in the display device including a non-rectangular display panel, the charging rate becomes uniform across the display unit, and the occurrence of abnormal display (display of an image called vertical gradation) is suppressed.
According to the fifth aspect of the present invention, in a display device having a circular display panel, the same effect as that of the fourth aspect of the present invention can be obtained.
According to the sixth aspect of the present invention, in a display device for in-vehicle use, the same effect as that of the fourth aspect of the present invention can be obtained.
According to the seventh aspect of the present invention, in a display device including a rectangular display panel, control values are stored in the storage unit such that a larger bias current flows through an output amplifier provided for a video signal line whose charging rate is lower in a case where the magnitudes of bias currents are not controlled. By this, in the display device including a rectangular display panel, the occurrence of luminance non-uniformity is suppressed.
According to the eighth aspect of the present invention, the same effect as that of the first aspect of the present invention can be obtained in the video signal line drive method.
One embodiment of the present invention will be described below with reference to the accompanying drawings.
<1. Overall Configuration and Operation Overview>
As for the TFT 41 in the pixel formation portion 4, typically, an oxide TFT (a thin film transistor having an oxide semiconductor layer) is adopted. The oxide semiconductor layer includes, for example, an In—Ga—Zn—O-based semiconductor such as indium gallium zinc oxide. The In—Ga—Zn—O-based semiconductor is a ternary oxide of In, Ga, and Zn. Note that TFTs other than an oxide TFT can also be used as the TFT 41 in the pixel formation portion 4.
In addition, in the present embodiment, gate drivers (scanning signal line drive circuits) 500 that drive the gate bus lines GL are formed in the display unit 410 as shown in
An operation overview of the components shown in
The source driver 300 receives the digital video signals DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS which are outputted from the display control circuit 200, and applies data voltages V(1) to V(j) corresponding to display gradations indicated by the digital video signals DV to the source bus lines SL (1) to SL (j) (see
The gate drivers 500 repeat the application of active scanning signals to the respective gate bus lines GL (1) to GL (i), based on the gate start pulse signal GSP and the gate clock signal GCK which are outputted from the display control circuit 200, with one vertical scanning period being a cycle.
In the above-described manner, the data voltages V are applied to the source bus lines SL(1) to SL(j), respectively, and the scanning signals are applied to the gate bus lines GL (1) to GL(i), respectively, by which an image based on the image signal DAT transmitted from the external source is displayed on the display unit 410.
<2. Configuration and Operation of the Source Driver>
Next, the source driver 300 of the present embodiment will be described in detail.
<2.1 Overall Configuration of the Source Driver>
A source start pulse signal SSP and a source clock signal SCK are inputted to the shift register circuit 310. The shift register circuit 310 sequentially transfers a pulse included in the source start pulse signal SSP from an input terminal to an output terminal, based on the source clock signal SCK. Sampling pulses SMP for the respective source bus lines SL(1) to SL(j) are sequentially outputted from the shift register circuit 310 according to this pulse transfer, and the sampling pulses SMP are sequentially inputted to the sampling circuit 312.
The sampling circuit 312 samples digital video signals DV transmitted from the display control circuit 200, at the timing of sampling pulses SMP outputted from the shift register circuit 310, and outputs the digital video signals DV as internal image signals d. The latch circuit 314 captures the internal image signals d outputted from the sampling circuit 312, at the timing of a pulse of a latch strobe signal LS, and outputs the internal image signals d.
The gradation voltage generating circuit 316 generates voltages (gradation voltages) corresponding to respective gradation levels, based on a plurality of reference voltages provided from the power supply 100, and outputs the voltages as a gradation voltage group. For example, voltages (gradation voltages) Vk(0) to Vk(255) corresponding to 256 gradation levels are outputted as a gradation voltage group from the gradation voltage generating circuit 316.
The selection circuit 318 selects anyone of the voltages included in the gradation voltage group outputted from the gradation voltage generating circuit 316, based on the internal image signals d outputted from the latch circuit 314, and outputs the selected voltages. The output amplifier 32 performs impedance transformation on the voltages outputted from the selection circuit 318, and outputs the transformed voltages as data voltages V to source bus lines SL. At that time, as will be described later, the magnitude of a bias current of each output amplifier 32 is controlled by the bias current control unit 34.
In the register 33 there are stored in advance control values C for adjusting the settling time of outputs of the data voltages V from the output amplifier 32. In the present embodiment, as shown in
The bias current control unit 34 outputs, on a per source bus line SL basis, a bias current control signal SC based on a control value C stored in the register 33. By this bias current control signal SC, the magnitude of a bias current of an output amplifier 32 is controlled on a per source bus line SL basis.
<2.2 Configuration of the Output Amplifier>
Next, with reference to
The operational amplifier 320 includes, for example, a differential amplifier 321 having a configuration such as that shown in
<3. Specific Example of Control of a Bias Current of the Output Amplifier>
Next, the control of a bias current of the output amplifier 32 will be more specifically described. Note that here it is assumed that the bias current control unit 34 is implemented by a D/A converter that can output voltages of eight levels. Note also that it is assumed that the magnitude of a bias current is controlled within a range of 20% to 150% with reference to 0.15 mA.
In the register 33 there is stored in advance a 3-bit value as a control value C, depending on a target magnitude of a bias current. The control value C stored in the register 33 is provided to the D/A converter (bias current control unit 34). The D/A converter outputs any one of the voltages of eight levels (eight voltages corresponding to “the magnitude of a bias current: 20%” to “the magnitude of a bias current: 150%”) as a bias current control signal SC, depending on the 3-bit value which is the control value C stored in the register 33. The voltage (the bias current control signal SC) outputted from the D/A converter is provided to the variable constant-current source 322 in the output amplifier 32 (see
Meanwhile, focusing attention on one source bus line SL, the signal waveform of a data voltage V changes as shown in
In addition, for example, regarding source bus lines shown in
Hence, in the present embodiment, the magnitude of a bias current is controlled such that a larger bias current flows through an output amplifier 32 provided for a source bus line SL disposed at a location closer to the central portion of the display unit 410 (i.e., a source bus line SL with a larger load). In other words, control values C are stored in the register 33 in advance such that a larger bias current flows through an output amplifier 32 provided for a source bus line SL disposed at a location closer to the central portion of the display unit 410. For example, as shown in
<4. Effect>
According to the present embodiment, the source driver 300 is provided with the register 33 that stores control values C for adjusting the settling time of outputs of data voltages V from the output amplifiers 32; and the bias current control unit 34 that controls the magnitudes of bias currents of the output amplifiers 32 based on the control values C stored in the register 33. In such a configuration, in the register 33 there are stored control values C in advance such that a larger bias current flows through an output amplifier 32 provided for a source bus line SL with a larger load. By this, the difference in the settling time of the data voltage V between the plurality of source bus lines SL is reduced. As a result, the charging rate becomes uniform across the display unit 410, and the occurrence of abnormal display (display of an image called vertical gradation) is suppressed. As described above, according to the present embodiment, the source driver 300 that can suppress the occurrence of abnormal display caused by “the difference in the settling time of a data voltage V (to be applied to a source bus line SL)” depending on location of the source bus lines SL, and a liquid crystal display device including the source driver 300 are implemented.
Note that it is also possible to achieve a uniform charging rate by uniformly increasing the magnitudes of bias currents of all output amplifiers 32 regardless of the magnitude of the load on the source bus lines SL. However, by controlling the magnitudes of bias currents depending on the magnitude of the load on the source bus lines SL as in the present embodiment, the effect of a reduction in power consumption can also be obtained.
<5. Variants>
<5.1 First Variant>
In the above-described embodiment, the shapes of the liquid crystal panel 400 and the display unit 410 are circular. However, the shapes of the liquid crystal panel 400 and the display unit 410 are not particularly limited. Now, an example in which the present invention is applied to a liquid crystal display device for in-vehicle use will be described as a first variant.
<5.2 Second Variant>
In addition, although it is premised that the liquid crystal display device is an oddly shaped display in the above-described embodiment, the present invention is not limited thereto. Now, an example in which the present invention is applied to a liquid crystal display device having a general rectangular display unit will be described as a second variant.
Note that the present invention can also be applied to a case in which a gate driver 500 is formed in a picture-frame region in an oddly shaped display.
<6. Others>
This application claims priority to Japanese Patent Application No. 2015-208591 titled “Video Signal Line Drive Circuit and Display Device Provided with Same” filed Oct. 23, 2015, the content of which is included herein by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-208591 | Oct 2015 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2016/080644 | 10/17/2016 | WO | 00 |
