Patent Application
20090046176
The present invention relates to a video signal processing apparatus for performing an electronic zooming process on a video signal.
The conventional video signal processing apparatus, such as for example a video camera, is adapted to zoom in, and to zoom out a video image taken by a solid-state image sensing device such as for example Charge-Coupled Device (CCD), by processing a video signal indicative of the video image (see, for example, a patent document 1).
As shown in
In the conventional imaging apparatus thus constructed, the frame memory 55, the write address controller 60, the read address controller 61, the interpolation circuit 56, the magnification generating circuit 63 collectively perform an electronic zooming function.
In this imaging apparatus, the signal from the A/D converter 54 is stored in the frame memory 55 on the basis of the write address designated by the write address controller 60. When the signal from the A/D converter 54 is stored in the frame memory 55 in each frame, the read address controller 61 generates read address on the basis of the magnification generated by the magnification generating circuit 63. The signal is read from the frame memory 55 on the basis of the generated read address.
The imaging apparatus can output an image signal indicative of an image zoomed at a designated magnification by reason that the signal read from the frame memory 55 is processed by the interpolation circuit 56 on the basis of the magnification designated by the magnification generating circuit 63.
patent document 1: Jpn. unexamined patent publication No. H07-170461
The conventional imaging apparatus, however, encounters such a problem that it is necessary to use a frame memory for storing an image for each frame. This leads to the fact that the conventional imaging apparatus is increased in production cost by reason that the frame memory is generally expensive, and increased in size by reason that the number of its components is increased.
It is, therefore, an object of the present invention to provide a video signal processing apparatus that can be improved in production cost, and perform an electronic zooming function.
The video signal processing apparatus according to the present invention, comprising: line delay means for delaying a video signal by a period of a horizontal scan; and interpolating means for performing a vertical interpolation by using the video signal and the video signal delayed by the line delay means, performing a horizontal interpolation by using pixels adjacent to each other, and outputting an effective flag indicating an effective section of a signal to be outputted.
The video signal processing apparatus thus constructed as previously mentioned according to the present invention can perform an electronic zooming function without using a frame memory by reason that the horizontal and vertical interpolations are separately performed by the interpolating means, and the vertical interpolation is performed in each line.
The video signal processing apparatus according to the present invention further comprises signal processing means for performing a vertical interpolation by using at least two lines including a relevant line and an adjacent line, performing a horizontal interpolation by using pixels including a relevant pixel and an adjacent pixel, and outputting an effective flag indicating an effective section of a signal to be outputted.
The video signal processing apparatus thus constructed as previously mentioned according to the present invention can zoom in, and zoom out an image by performing an electronic zooming operation at a designated magnification, and by performing through an interpolating process and a signal process.
The video signal processing apparatus, comprising: video signal outputting means for outputting a video signal in synchronization with vertical and horizontal synchronization signals; line delay means for delaying the video signal by a period of the horizontal synchronization signal; interpolating means for performing a vertical pixel interpolation by comparing the video signal outputted by the video signal outputting means and the video signal delayed by the line delay means; and zooming control means for controlling the interpolating means on the basis of a vertical magnification ratio to have the interpolating means perform the vertical pixel interpolation by using pixels vertically-adjacent in each pixel.
The video signal processing apparatus thus constructed as previously mentioned according to the present invention can performing the vertical interpolation in each pixel without using a frame memory.
In the video signal processing apparatus according to the present invention, the interpolating means is adapted to perform, for an image interpolated in the vertical direction, a horizontal pixel interpolation by using pixels horizontally-adjacent to each other, and the zooming control means is adapted to control the interpolating means on the basis of a horizontal magnification to have the interpolating means perform the horizontal pixel interpolation by using two pixels horizontally-adjacent to each other.
The video signal processing apparatus thus constructed as previously mentioned according to the present invention can performing the horizontal pixel interpolation without using a frame memory.
In the video signal processing apparatus according to the present invention, the zooming control means is adapted to have the interpolating means perform the horizontal pixel interpolation by using pixels horizontally-adjacent to each other before the video signal is delayed by the line delay means.
The video signal processing apparatus thus constructed as previously mentioned according to the present invention can performing the vertical pixel interpolation after performing the horizontal pixel interpolation.
In the video signal processing apparatus according to the present invention, the interpolating means includes vertical interpolation means for producing a video signal indicative of the image interpolated in the vertical direction, and horizontal interpolation means for producing a video signal indicative of the image interpolated in the horizontal direction, and the zooming control means includes vertical zooming control means for allowing a vertical line effective flag to indicate whether or not each of sample points of the video signal produced by the vertical interpolation means is within an active period, horizontal zooming control means for allow a horizontal line effective flag to indicate whether or not each of sample points of the video signal produced by the horizontal interpolation means is within an active period, and a logical product circuit for outputting, in synchronization with video signal produced by the horizontal interpolation means, an effective flag signal indicative of the logical product of the vertical and horizontal line effective flags.
The video signal processing apparatus thus constructed as previously mentioned according to the present invention can performing independently the vertical and horizontal pixel interpolations.
In the video signal processing apparatus according to the present invention, the vertical zooming control means is adapted to calculate a vertical interpolation coefficient from the vertical magnification ratio, the vertical interpolation means includes a first multiplier for multiplying the video signal delayed by the line delay means by the vertical interpolation coefficient, a second multiplier for multiplying the video signal outputted by the video signal outputting means by a complement number of the vertical interpolation coefficient, and an adder for producing a video signal indicative of the sum of the video signal multiplied by the vertical interpolation coefficient and the video signal multiplied by the complement number of the vertical interpolation coefficient, and the vertical zooming control means is adapted to allow the vertical interpolation means to output, in synchronization with the vertical and horizontal sync signals, the video signal produced by the adder to the horizontal interpolation means.
The video signal processing apparatus thus constructed as previously mentioned according to the present invention can performing simply the vertical interpolation by using the vertical interpolation coefficient calculated from the vertical magnification.
In the video signal processing apparatus, the horizontal zooming control means is adapted to calculate a horizontal interpolation coefficient from the horizontal magnification, the horizontal interpolation means includes pixel delay means for delay the video signal received from the vertical interpolation means, a first multiplier for multiplying the video signal received from the vertical interpolation means by the horizontal magnification coefficient, a second multiplier for multiplying the video signal delayed by the pixel delay means by a complement number of the horizontal magnification coefficient, and an adder for producing a video signal indicative of the sum of the video signal multiplied by the horizontal magnification coefficient and the video signal multiplied by the complement number of the horizontal magnification coefficient, and the vertical zooming control means is adapted to allow the horizontal interpolation means to output, in synchronization with the vertical and horizontal sync signals, the video signal produced by the adder of the horizontal interpolation means.
The video signal processing apparatus thus constructed as previously mentioned according to the present invention can performing simply the horizontal interpolation by using the horizontal interpolation coefficient calculated from the horizontal magnification.
In the video signal processing means according to the present invention, the line delay means is constituted by line memory means having three banks, each of which stores one line of an image to be represented by the video signal, the line memory means is adapted to store the image in the three banks through steps of writing sequentially three lines of the image in the respective banks before overwriting sequentially the next three lines of the image in the respective banks, and overwriting repeatedly in each frame until writing the last line of the image is any one of the banks, the line memory means is adapted to read, when writing one line of the image in any one of the banks, two lines from the remaining two banks, and to output the two lines to the interpolating means, and the interpolating means is adapted to the vertical pixel interpolation by using two pixels of the two lines read by the line memory means.
The video signal processing apparatus thus constructed as previously mentioned according to the present invention can performing simply the horizontal pixel interpolation by using pixels adjacent to each other by reason that the line memory means is adapted to store the image in the three banks through steps of writing sequentially three lines of the image in the respective banks before overwriting sequentially the next three lines of the image in the respective banks, and overwriting repeatedly in each frame until writing the last line of the image is any one of the banks.
In the video signal processing apparatus according to the present invention, the zooming control means is adapted to have the line memory means store the video signal after having the interpolating means perform the horizontal pixel interpolation by using pixels adjacent to each other.
The video signal processing apparatus thus constructed as previously mentioned according to the present invention can change the order of the horizontal and vertical interpolations.
The present invention provides a video signal processing apparatus that can be improved in production cost, and perform an electronic zooming function, without using a frame memory, by performing the vertical interpolation by using the inputted line and the line delayed by the line delay means, and perform performing the horizontal interpolation by using pixels adjacent to each other.
The embodiments of the video signal processing apparatus according to the present invention will be described hereinafter with reference to accompanying drawings.
As shown in
Here, the analog preprocessing means 13, the A/D converter 14, the Y/C signal processing means 15, and the imaging element driving means 19 collectively function as video signal outputting means for outputting a video signal to the line delay means 16 and the interpolating means 18 in synchronization with the vertical and horizontal sync signals.
In this embodiment, the predetermined delay time of the line delay means 16 is the same as the period of the horizontal sync signal (the period of the horizontal scan).
As shown in
The interpolating means 18 is adapted to receive the luminance and color difference signals processed and outputted by the Y/C signal processing means 15 in synchronization with the vertical and horizontal sync signals, and to receive the luminance and color difference signals delayed by the line delay means 16 in synchronization with the vertical and horizontal sync signals. From the foregoing description, it will be understood that the interpolating means 18 can compare, in luminance and color, two pixels adjacent to each other in a vertical direction by receiving the luminance and color difference signals outputted by the Y/C signal processing means 15, and receiving the luminance and color difference signals delayed by a time equal to a period of the horizontal synchronization signal by the line delay means 16.
In this embodiment, the Y/C signal processing means 15 is adapted to produce luminance and color difference signals from the digital video signal of the A/D converter 14. However, the Y/C signal processing means 15 may be adapted to produce red-green-blue signals. The interpolating means 18 may be adapted to perform the interpolation of the red-green-blue signals.
The construction of the zooming control means 17 and the interpolating means 18 of the video signal processing apparatus according to the first embodiment of the present invention will be then described hereinafter with reference to
In order to perform independently the vertical and horizontal interpolations, the zooming control means 17, as shown in
The vertical zooming control means 171 and the vertical interpolation means 181 will be described hereinafter as means for performing the vertical interpolation of the image.
In
The vertical interpolation means 181 is adapted to produce an output signal W(j) (j=0, 1, 2, . . . , 7) from the input signal V(i) (i=0, 1, 2, . . . , 11) by using a following arithmetic expression.
W(j)=(1−αv)×V(int(βv))+αv×V(int(βv)+1)
Here, βv=j/vertical magnification=j×3/2
αv=βv-int(βv)
int(βv) is intended to indicate a function of truncating and outputting an integer.
In this embodiment, the interpolating means 18 is adapted to perform the linear interpolation by using the above-mentioned arithmetic expression. The interpolating means 18 may be adapted to perform the higher-order interpolation of the image.
In order to calculate the output signal W(j), the vertical interpolation means 181 needs to receive the input signal V(int(j/vertical magnification)+1). Therefore, the vertical interpolation means 181 is adapted to calculate the output signal W(j) in response to the input signal V(int(j/vertical magnification)+1). More specifically, it is only necessary to have the vertical interpolation means 181 calculate the output signal W(j) corresponding to a line designated by the input signal V(int(j/vertical magnification)+1). Additionally, it is necessary to have the vertical interpolation means 181 calculate the output signal W(j) in every pixel of the designated line.
It is necessary to indicate whether or not the output signal W(j) of the vertical interpolation means 181 is effective in each line. The vertical zooming control means 171 is adapted to produce a vertical effective flag for indicating whether or not the output signal W(j) of the vertical interpolation means 181 is effective.
The vertical zooming control means 171 is adapted to receive a vertical magnification, to calculate values αv and βv on the basis of the vertical magnification, to produce timing information on whether or not to have the vertical interpolation means 181 perform the calculation of the output signal W(j), and to output the vertical interpolation coefficient αv to the vertical interpolation means 181. When the vertical effective flag is in high level “H”, the vertical effective flag indicates that the relevant line is recognized as an effective line. When, on the other hand, the vertical effective flag is in low level “L”, the relevant line is recognized as an ineffective line.
The horizontal zooming control means 172 and the horizontal interpolation means 182 will be then described hereinafter as means for performing the horizontal interpolation.
In
The horizontal interpolation means 182 is adapted to produce, on the basis of a following formula, the input signal x(i) (i=o, 1, 2, . . . , 14) from the output signal y(0) (j=0, 1, 2, . . . , 9).
y(j)=(1−αh)×x(int(βh))+αh×x(int(βh)+1)
Here, βh=j/horizontal magnification=j×3/2
αh=βh−int(βh)
In this embodiment, the horizontal interpolation means is adapted to perform the linear interpolating calculation by using two pixels. However, the horizontal interpolation means may be adapted to perform the high order interpolating calculation.
In this embodiment, the horizontal interpolation means 182 is adapted to receive the input signal x(int (j/horizontal magnification)+1) before computing the output signal y(i) in synchronization with the input signal x(int (j/horizontal magnification)+1). More specifically, it is not necessary to perform the horizontal interpolation over a period designated by the input signal x(int (j/horizontal magnification)+1).
It is necessary to indicate whether or not the output signal of the horizontal interpolation means 182 is effective. The horizontal zooming control means 172 is adapted to produce a horizontal effective flag for indicating whether or not the output signal W(j) of the vertical interpolation means 181 is effective.
The horizontal zooming control means 172 is adapted to receive a horizontal magnification, to calculate horizontal interpolation coefficients αh and βh on the basis of the horizontal magnification, to produce timing information on whether or not to have the horizontal interpolation means 182 perform the calculation of the output signal y(j), and to output the horizontal interpolation coefficient αv to the horizontal interpolation means 182. When the horizontal effective flag is in high level “H”, the horizontal effective flag indicates that the relevant pixel is recognized as an effective pixel. When, on the other hand, the horizontal effective flag is in low level “L”, the relevant pixel is recognized as an ineffective pixel.
The logical product circuit 173 of the zooming control means 17 is adapted to produce an effective flag signal by calculating the logical product of the vertical and horizontal effective flags.
From the foregoing description, it will be understood that the video signal processing apparatus according to the first embodiment can be simple in construction, and can perform the electronic zooming function, without using a frame memory, by using a line memory by performing separately the horizontal and vertical electronic zooming functions, and performing the vertical interpolation process in each line.
Even if the horizontal and vertical magnifications are different from each other, the video signal processing apparatus can perform the electronic zooming process.
In this embodiment, the video signal processing apparatus is adapted to perform the horizontal interpolation after performing the vertical interpolation. However, the present invention is not limited to the order of the horizontal and vertical interpolations. Therefore the video signal processing apparatus may be adapted to perform the vertical interpolation after performing the horizontal interpolation. In this case, the line delay means 16 is defined between the vertical and horizontal interpolation computing means 181 and 182.
The line delay means may be constituted by line memory means having three banks, each of which writes a horizontal line forming part of an image represented by the video signal. In this case, the line memory means is adapted to write one horizontal line of the image in a bank selected in a predetermined order from among the banks. After the line memory means finishes writing one horizontal line in the third bank, the line memory means selects the first bank from among the banks, and overwrites the previously saved horizontal line of the first bank. The line memory means continues to perform the writing operation until writing all of the horizontal lines of the image in the banks. When the line memory means stores one horizontal line in any one of the banks, the line memory means is adapted to read out the previously saved horizontal lines from the remaining banks, and to output two horizontal lines read out from the remaining banks to the interpolating means. The interpolating means is adapted to perform, in each pixel, the vertical interpolation by using two horizontal line received from the line memory means.
The video signal processing apparatus according to the second embodiment further comprises signal processing means 21 for performing the interpolation process on the electronically zoomed output signal of the interpolating means 18.
The signal processing means 21 includes line memory means 211 for storing the electronically zoomed output signal of the interpolating means 18 in response to write address banks, and reading out the output signals at the same time from two banks in response to read address banks, vertical interpolation computing means 212 for computing, on the basis of the vertical interpolation coefficient, the interpolation by using two output signals read from the line memory means 211, pixel memory means 213 for storing, one by one, each pixel of the output signal from the vertical interpolation computing means 212, horizontal interpolation computing means 214 for computing, on the basis of the vertical interpolation coefficient, the interpolation by using the output of the vertical interpolation computing means 212 and the output of the pixel memory means 213, vertical interpolation control means 215 for controlling the line memory means 211 and the vertical interpolation computing means 212 to have the vertical interpolation computing means 212 compute the interpolation, and horizontal interpolation control means 216 for controlling the horizontal interpolation computing means 214 to have the horizontal interpolation computing means 214 compute the interpolation.
The following description will be directed to the case that the interpolation is performed at double multiplication in the vertical direction by the signal processing means 21.
In
The electronically zoomed outputs inputted into the signal processing means 21 is stored in the line memory means 211 in response to the write address banks outputted by the vertical interpolation control means 215.
The line memory means 211 has three banks that are selectively designated in each line. Each bank is adapted to output the signal before overwriting new signal.
When the interpolation is performed at a designated magnification of Nv (which is equal to 2 in
When the video data is repeatedly read out, in each line, from two of the banks Nv times a line, the i-th horizontal interpolation coefficient γv is defined by the following expression.
γv=(i−1)/Nv (i=1, 2, . . . , Nv)
The horizontal interpolation computing means 212 generates, on the basis of the following expression, the data L(0), L(1), L(2), . . . from two lines Z(j) and Z(j+1) (j=1, 2, . . . ) repeatedly read at the speed of Nv and the i-th horizontal interpolation coefficient γv.
L(j×Nv+i−1)=(1−γv)×Z(j)+γv×Z(j+1)
When the interpolation is performed at double multiplication as shown in
Further, the effective flag is also stored in the line memory means 211. When the video data is read out at a speed of Nv, the effective flag is read out from the line memory means 211 as vertical interpolation effective flag.
The following description will be then directed to the case that the interpolation is performed at double magnification in a horizontal direction by the signal processing means 21.
In
The vertically interpolated output of the vertical interpolation computing means 212 is inputted into the horizontal interpolation computing means 214 and the pixel memory means 213, and delayed by one pixel by the pixel memory means 213. The delayed output is inputted into the horizontal interpolation computing means 214.
When the interpolation is performed at a designated magnification of Nh (which is equal to 2 in
When the computation (interpolation) is repeatedly performed Nh times a pixel, the i-th horizontal interpolation coefficient γh is defined by the following expression.
γh=(i−1)/Nh (i=1, 2, . . . , Nh)
The horizontal interpolation computing means 214 generates, on the basis of the following expression, the data M(0), M(1), M(2), . . . from two pixels K(j) and K(j+1) (j=1, 2, . . . ) repeatedly read at the speed of Nh and the i-th horizontal interpolation coefficient γh.
M(j×Nh+i−1)=(1−γh)×K(j)+γh×K(j+1)
As shown in
From the foregoing description, it will be understood that the video signal processing apparatus according to the second embodiment can set an inputted magnification so as to zoom in and zoom out the image by reason that the signal processing means 21 is adapted to process the output of the interpolating means 18, the magnification of the apparatus being defined by the product of the magnification of the interpolating means and the magnification of the signal processing means.
As will be seen from the foregoing description, the video signal processing apparatus according to the present invention can be reduced in production cost, has an advantageous effect of performing the electronic zooming function, and useful as an apparatus for carrying out the electronic zooming process on the video signal.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-302747 | Oct 2004 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP05/18968 | 10/14/2005 | WO | 00 | 4/16/2007 |
