Patent Application
20100033621
1. Field of the Invention
The invention relates to a video system, and in particular relates to a plurality of processing units in the video system sharing memory.
2. Description of the Related Art
A video system is designed to be capable of receiving and processing video signals complying with different standards, such as an S-video (separate video) signal, an HDMI (high definition multimedia interface) signal, an AV (composite video) signal, a turner signal, a DVI (digital visual interface) signal, an HDTV (high definition television) signal and a VGA (video graphics array) signal, and display corresponding images on a display panel. However, different signals are not processed in the same way by the video system, for example, some of the mentioned signals require comb filtering and deinterlacing, some only requires deinterlacing, and some other signals are processed without comb filtering and deinterlacing. Furthermore, the size of the display panel also influences the video processing operation of the input signal, for example, the signal are scaled down or scaled up based on the display dimension.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
An embodiment of a memory sharing method for a video system is provided. The method comprises determining a type of an input video signal, sharing an SRAM (static random access memory) pool among at least two different processing units of the video system, wherein the SRAM pool comprises a plurality of SRAM units having different sizes, and an SRAM unit size is determined as a common factor of memory sizes required by at least two processing units, and allocating a combination of SRAM units in the SRAM pool to each processing unit processing the input video signal according to the type of the input video signal.
Another embodiment of a video system is provided. The video system comprises a plurality of processing units, an SRAM pool and a controller. The SRAM pool comprises a plurality of SRAM units having different sizes for sharing among at least two different processing units, wherein an SRAM unit size is determined as a common factor of memory sizes required by at least two processing units. The controller determines a type of an input video signal, and allocates a combination of SRAM units to each processing unit processing the input video signal according to the type of the input video signal.
Another embodiment of a video system is provided. The video system comprises a main source selection unit, a sub source selection unit, a plurality of processing units, an SRAM pool, a controller, and a mixer. The main source selection unit receives and selects input video signals for a main path. The sub source selection unit receives and selects input video signals for a sub path. The set of the processing units processes the input video signal of the main path, and another set processes the input video signal of the sub path. The SRAM pool comprises a plurality of SRAM units having different sizes for sharing among at least two different processing units. An SRAM unit size is determined as a common factor of memory sizes required by at least two processing units. The controller determines a type of the input video signal selected by the main source selection unit and the sub source selection unit, and allocates a combination of SRAM units to each processing unit processing the input video signal of the main path or sub path according to the type of the input video signal processed in the main path or sub path. The mixer blends processed main video signal and processed sub video signal for output display.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description includes the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
The video system 200 is capable of processing different kinds of image signals, such as a tuner signal S201 received by a tuner, an AV signal S202 received through a composite video connector, an S-video signal S203, an HDTV signal S204, a VGA signal S205, a DVI signal S206 and an HDMI signal S207 for displaying images on the display panel. However, the invention is not limited to the mentioned image signals, and it is also not limited to the number of types of image signals supported by the video system.
The TV decoder unit 220 is for decoding the tuner signal S201, AV signal S202 or S-video signal S203 to output the decoded signal to the main source selection unit 231 and/or the sub-source selection unit 232. In this embodiment, the main source selection unit 231 and the sub-source selection unit 232 act like a multiplexer for selecting an output from the decoded tuner signal, decoded AV signal, decoded S-video signal, HDTV signal S204, VGA signal S205, DVI signal S206 and HDMI signal S207 according to the controller 295. The main source selection unit 231 and the sub-source selection unit 232 respectively output video signals S1 and S2 to perform post-processing such as noise reduction units 241 and 242 according to a user setting or default setting. The controller 295 detects types of the video signals S1 and S2 to determine sharing of the SRAM among various processing units and allocation of SRAM units among the processing units. The signals S1 and S2 may be the same or different type of image signal. The signal S1 is processed through one or a combination of the noise deduction unit 241, the deinterlace unit 251, the scalar down unit 261 and the scalar up unit 271, and then outputted to the mixer 290. The signal S2 is processed through one or a combination of the noise deduction unit 242, the deinterlace unit 252, the scalar down unit 262 and the scalar up unit 272, and then outputted to the mixer 290. The mixer 290 blends the processed signal S1 and the processed signal S2 when the display mode indicates displaying two signal sources simultaneously, for example, when the display mode belongs to a PIP (picture in picture) or POP (picture of picture) mode, otherwise, the mixer 290 is bypassed. In an embodiment, the maximum size for displaying the processed signal S2 (sub video input) is a quarter of the entire displaying area.
As shown in
Table 1 shows SRAM sizes required for processing different types of main video input through different post-processing stages to be displayed on a display panel with 1440*768 pixels. For example, when the main video input is a 480i/576i video signal received from a TV tuner, the TV decoder 220 requires an SRAM size of (Nt2+Nt3)*1135*10 bits, the noise reduction unit 241 required an SRAM size of Nmn*720*10 bits, the deinterlace unit 251 required an SRAM size of Nmd*720*10 bits, the scalar down unit 261 did not require any SRAM because the image size of the 480i/576i video input signal is smaller than that of the panel resolution (1440*768), and the scalar up unit 271 required an SRAM size of Nmsu*720*10 bits. Nt2 is the number of lines required for a two-dimensional comb filter, Nt3 is the number of lines required for a three-dimensional comb filter, Nmn is the line length required for noise reduction in the main path, Nmd is the line length required for deinterlace, Nmsd is the line length required for scale down, and Nmsu is the line length required for scale up (“m” denotes main path). In this example, the number of bits in a pixel is 10 bits. SRAM sizes required at each stage for processing various types of main video inputs such as Ypbpr 1080i, VGA 800*600 and VGA 1920*1200, are shown in Table 1.
Table 2 shows SRAM sizes required for processing different types of sub video input through different post-processing stages to be displayed on a display panel with 1920*1080 pixels. For example, if the sub video input is a 480i/576i video signal, the TV decoder 220 requires an SRAM size of (Nt2+Nt3)*1135*10 bits, the noise reduction unit 242 requires an SRAM size of Nsn*720*10 bits, the deinterlace unit 252 requires an SRAM size of Nsd*720*10 bits, the scalar down unit 262 did not require any SRAM because the image size of the 480i/576i video signal is smaller than that of the panel resolution (1440*768), and the scalar up unit 272 requires an SRAM size of Nssu*720*10 bits. Similar notations are used in Table 1 and Table 2, where “s” in Nsn, Nsd, Nssd, Nssu denotes sub path. The rest of Table 2 illustrates the SRAM sizes required for some other types of sub video input such as Ypbpr 1080i, VGA 800*600 and VGA 1920*1200.
Since the size of the maximum second images (sub path) is assumed as a quarter of the entire display panel area, the length of the maximum second image is half length of the maximum panel resolution, 1920/2=960. Therefore, if the sub video input is YPbPr or VGA 1920*1200, the noise reduction unit 242 only requires an SRAM size of Nsn*960*10 bits, not Nsn*1920*10 bits.
The above parameters Nt2, Nt3, Nmn, Nmd, Nmsd, Nmsu, Nsn, Nsd, Nssd and Nssu are positive integers. In the following embodiments, it is assumed that Nt2=4, Nt3=6, Nmn=4, Nmd=8, Nmsd=3, Nmsu=9, Nsn=4, Nsd=8, Nssd=3 and Nssu=3.
Table 3 shows that the display panel is 1440*768 pixels, the main path processes a 480i/576i TV signal and the sub path processes a Ypbpr signal with 480i/576i, 720i or 1080i resolution. The maximum SRAM size required is 10*1135*10+42*360*10 bits (main path)+30*360*10 bits (sub path). In this embodiment, the SRAM pool is composed of SRAM units with two different sizes, 1135*10 bits and 360*10 bits. In some other embodiments, the SRAM unit size of 720*10 bits can be used instead of 360*10 bits, or the SRAM pool comprises both 720*10 bits and 360*10 bits.
Table 4 shows that the display panel is a 1920*1080 panel, the main path processes a 480i/576i TV signal and the sub path processes a Ypbpr signal with 480i/576i, 720i or 1080i resolution. The maximum SRAM size required is the summation of (E) and (G), which is 10*1135*10+42*360*10 bits (main path)+45*320*10 bits (sub path). In this embodiment, three sizes of SRAM units, 1135*10 bits, 360*10 bits, and 320*10 bits are shared by various processing units for processing the main video and sub video inputs.
Table 5 shows that the display panel is a 1440*768 panel, the sub path processes a 480i/576i TV signal and the main path processes a Ypbpr signal with 480i/576i, 720i or 1080i resolution. The maximum SRAM size required is the summation of (K) and (L), which is 72*320*10+12*360*10 bits (main path)+10*1135*10+30*360*10 bits (sub path).
Table 6 shows that the display panel is a 1920*1080 panel, the sub path processes a 480i/576i TV signal and the main path processes a Ypbpr signal with 480i/576i, 720i or 1080i resolution. The maximum SRAM size required is the summation of (N) and (P), which is 84*320*10 bits (main path)+10*1135*10+30*360*10 bits (sub path).
Table 7 shows that the display panel is a 1440*768 panel, the main path processes a YPbPr signal with 720i or 1080i resolution and the sub path also processes a Ypbpr signal with the 720i or 1080i resolution. The maximum SRAM size required is the summation of (S) and (T) or (S) and (U), which is 72*320*10+12*360*10 bits (main path)+30*360*10 bits (sub path).
Table 8 shows that the display panel is a 1920*1080 panel, the main path processes a YPbPr signal with 720i or 1080i resolution and the sub path processes a Ypbpr signal with 720i or 1080i resolution. The maximum SRAM size required is the summation of (W) and (Y), which is 84*320*10 bits (main path)+45*320*10 bits (sub path).
As seen in Tables 1˜8, not all processing units are operated at the same time. For example, the scalar up unit and the scalar down unit are typically not operated at the same time. The deinterlace unit is not enabled for progressive signals, such as the VGA signal 800*600 or 1920*1200. The TV decoder is not enabled if the processed signal is not a TV signal. Thus, the SRAM pool 210 of the video system comprises SRAM units with various sizes are shared by different processing units to reduce the required memory size. According to an embodiment of the invention, one size of the SRAM unit is a common factor of SRAM size required for two or more processing units. In addition, small size SRAM units are easily shared between a plurality of processing units, however, control of small size SRAM units is more complicated than control of large size SRAM units.
Table 9 shows an exemplary arrangement of the SRAM pool 210 according to the above Cases 1˜6 corresponding to Tables 3˜8 respectively. There are three sizes of SRAM units, 360*10 bits units, 320*10 bits units and 1135*10 bits units in this embodiment. Some of the SRAM units allocated to a processing unit are not exactly equal to the amount of SRAM required, for example, SRAM units of 360*10 are used for applications which need SRAM units of 320*10. According to the arrangement in Table 9, the minimum size of the SRAM pool 210 is 42*360*10+72*320*10+10*1135*10 bits, which is 495100 bits. The SRAM pool 210 can be shared by the TV decoder (TV) 220, noise reduction units (NR) 241 and 242, deinterlace units (DI) 251 and 252, scalar up units (SU) 261 and 262, and scalar down units (SD) 271 and 272. The SRAM size for a main video input of YPbPr 1080i and a sub video input of TV 480i/576i can be expressed as (Nt2+Nt3)*1135*10+(Nmn+Nmd)*1920*10+Nmsd*1440*10+(Nsn+Nsd+Nssu)*720*10. Compared to the dedicated SRAM implementation, the total SRAM needed can be expressed as (Nt2+Nt3)*1135*10+(Nmn+Nmd+Nmsd+Nmsu)*1920*10+(Nsn+Nsd+Nssd+Nssu)*10. The size of SRAM saved by using the SRAM pool is Nmsd*480*10+Nmsu*1920*10+Nssd*960*10+(Nsn+Nsd+Nssu)*240*10, which is 25200 bits if substituting the numerical assumptions used in the previous embodiments. This reduction of SRAM size significant since 25200 bits is approximately one third of the original SRAM size required.
The size of the SRAM pool can be designed to be a maximum amount of memory required at a time by a plurality of processing units that share the SRAM pool, or it can be designed to be slightly larger than this maximum value. The number of processing units that share the SRAM pool and which processing units share the SRAM pool should not be limitations to the invention, sharing the SRAM pool by two processing units can even gain some advantage of SRAM size and cost reduction.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited to thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
