Virtual addressing in a storage system

Information

  • Patent Grant
  • 11188476
  • Patent Number
    11,188,476
  • Date Filed
    Monday, December 2, 2019
    4 years ago
  • Date Issued
    Tuesday, November 30, 2021
    3 years ago
Abstract
A method for preserving a media access control (MAC) address of a virtual server is provided. The method includes assigning a physical computing resource to a virtual server, assigning a physical storage memory resource to the virtual server, and assigning a physical network resource to the virtual server. The method includes assigning a virtual MAC address to the virtual server, the virtual MAC address to remain with the virtual server despite reassignment of one or more of the physical computing resource, the physical storage memory resource or the physical network resource, wherein at least one method operation is performed by a processor. A computing and storage system is also provided.
Description
BACKGROUND

Setting up a file server may be done according to policies of a client and may include specifying a MAC (media access control) address, an IP (Internet Protocol) address and a LAN (local area network) configuration. Changes to hardware, such as for an upgrade, can be problematic and involve changes to the MAC address, as well as various routing rules that have been set up and that reference MAC addresses. These disruptions can affect file servers using various types of memory. Solid-state memory, such as flash, is currently in use in solid-state drives (SSD) to augment or replace conventional hard disk drives (HDD), writable CD (compact disk) or writable DVD (digital versatile disk) drives, collectively known as spinning media, and tape drives, for storage of large amounts of data. Flash and other solid-state memories have characteristics that differ from spinning media. Yet, many solid-state drives are designed to conform to hard disk drive standards for compatibility reasons, which makes it difficult to provide enhanced features or take advantage of unique aspects of flash and other solid-state memory.


It is within this context that the embodiments arise.


SUMMARY

In some embodiments, a method for preserving a media access control (MAC) address of a virtual server is provided. The method includes assigning a physical computing resource to a virtual server, assigning a physical storage memory resource to the virtual server, and assigning a physical network resource to the virtual server. The method includes assigning a virtual MAC address to the virtual server, the virtual MAC address to remain with the virtual server despite reassignment of one or more of the physical computing resource, the physical storage memory resource or the physical network resource, wherein at least one method operation is performed by a processor.


Other aspects and advantages of the embodiments will become apparent from the following detailed description taken in conjunction with the accompanying drawings which illustrate, by way of example, the principles of the described embodiments.





BRIEF DESCRIPTION OF THE DRAWINGS

The described embodiments and the advantages thereof may best be understood by reference to the following description taken in conjunction with the accompanying drawings. These drawings in no way limit any changes in form and detail that may be made to the described embodiments by one skilled in the art without departing from the spirit and scope of the described embodiments.



FIG. 1 is a perspective view of a storage cluster with multiple storage nodes and internal storage coupled to each storage node to provide network attached storage, in accordance with some embodiments.



FIG. 2 is a system diagram of an enterprise computing system, which can use one or more of the storage clusters of FIG. 1 as a storage resource in some embodiments.



FIG. 3 is a block diagram showing a communications interconnect coupling multiple storage nodes in accordance with some embodiments.



FIG. 4 is a block diagram showing a computing and storage system creating a virtual file server with a preserved MAC address, in accordance with some embodiments.



FIG. 5 is a multiple level block diagram, showing contents of a storage node and contents of one of the non-volatile solid-state storages in accordance with some embodiments.



FIG. 6 is a flow diagram of a method for assigning a media access control address in a computing and storage system, which can be practiced on or by embodiments of the storage cluster, storage nodes and/or non-volatile solid-state storages in accordance with some embodiments.



FIG. 7 is an illustration showing an exemplary computing device which may implement the embodiments described herein.





DETAILED DESCRIPTION

The embodiments below describe a storage cluster that stores user data, such as user data originating from one or more user or client systems or other sources external to the storage cluster. The storage cluster distributes user data across storage nodes housed within a chassis, using erasure coding and redundant copies of metadata. Erasure coding refers to a method of data protection in which data is broken into fragments, expanded and encoded with redundant data pieces and stored across a set of different locations, such as disks, storage nodes or geographic locations. Flash memory is one type of solid-state memory that may be integrated with the embodiments, although the embodiments may be extended to other types of solid-state memory or other storage medium, including non-solid state memory. Control of storage locations and workloads are distributed across the storage locations in a clustered peer-to-peer system. Tasks such as mediating communications between the various storage nodes, detecting when a storage node has become unavailable, and balancing I/Os (inputs and outputs) across the various storage nodes, are all handled on a distributed basis. Data is laid out or distributed across multiple storage nodes in data fragments or stripes that support data recovery in some embodiments. Ownership of data can be reassigned within a cluster, independent of input and output patterns. This architecture described in more detail below allows a storage node in the cluster to fail, with the system remaining operational, since the data can be reconstructed from other storage nodes and thus remain available for input and output operations. In various embodiments, a storage node may be referred to as a cluster node, a blade, or a server.


The storage cluster is contained within a chassis, i.e., an enclosure housing one or more storage nodes. A mechanism to provide power to each storage node, such as a power distribution bus, and a communication mechanism, such as a communication bus that enables communication between the storage nodes are included within the chassis. The storage cluster can run as an independent system in one location according to some embodiments. In one embodiment, a chassis contains at least two instances of both the power distribution and the communication bus which may be enabled or disabled independently. The internal communication bus may be an Ethernet bus, however, other technologies such as Peripheral Component Interconnect (PCI) Express, InfiniBand, and others, are equally suitable. The chassis provides a port for an external communication bus for enabling communication between multiple chassis, directly or through a switch, and with client systems. The external communication may use a technology such as Ethernet, InfiniBand, Fibre Channel, etc. In some embodiments, the external communication bus uses different communication bus technologies for inter-chassis and client communication. If a switch is deployed within or between chassis, the switch may act as a translation between multiple protocols or technologies. When multiple chassis are connected to define a storage cluster, the storage cluster may be accessed by a client using either proprietary interfaces or standard interfaces such as network file system (NFS), common internet file system (CIFS), small computer system interface (SCSI) or hypertext transfer protocol (HTTP). Translation from the client protocol may occur at the switch, chassis external communication bus or within each storage node.


Each storage node may be one or more storage servers and each storage server is connected to one or more non-volatile solid state memory units, which may be referred to as storage units. One embodiment includes a single storage server in each storage node and between one to eight non-volatile solid state memory units, however this one example is not meant to be limiting. The storage server may include a processor, dynamic random access memory (DRAM) and interfaces for the internal communication bus and power distribution for each of the power buses. Inside the storage node, the interfaces and storage unit share a communication bus, e.g., PCI Express, in some embodiments. The non-volatile solid state memory units may directly access the internal communication bus interface through a storage node communication bus, or request the storage node to access the bus interface. The non-volatile solid state memory unit contains an embedded central processing unit (CPU), solid state storage controller, and a quantity of solid state mass storage, e.g., between 2-32 terabytes (TB) in some embodiments. An embedded volatile storage medium, such as DRAM, and an energy reserve apparatus are included in the non-volatile solid state memory unit. In some embodiments, the energy reserve apparatus is a capacitor, super-capacitor, or battery that enables transferring a subset of DRAM contents to a stable storage medium in the case of power loss. In some embodiments, the non-volatile solid state memory unit is constructed with a storage class memory, such as phase change or magnetoresistive random access memory (MRAM) that substitutes for DRAM and enables a reduced power hold-up apparatus.


One of many features of the storage cluster, storage nodes and non-volatile solid-state storages disclosed herein is the ability to create virtual file servers with preserved MAC (media access control) addresses. By assigning virtual MAC addresses to virtual file servers, a computing and storage system or cluster can create Internet Protocol (IP) addresses, MAC addresses and VLAN (virtual local area network) configurations that remain permanent or persistent while hardware underneath can change.



FIG. 1 is a perspective view of a storage cluster 160, with multiple storage nodes 150 and internal solid-state memory coupled to each storage node to provide network attached storage or storage area network, in accordance with some embodiments. A network attached storage, storage area network, or a storage cluster, or other storage memory, could include one or more storage clusters 160, each having one or more storage nodes 150, in a flexible and reconfigurable arrangement of both the physical components and the amount of storage memory provided thereby. The storage cluster 160 is designed to fit in a rack, and one or more racks can be set up and populated as desired for the storage memory. The storage cluster 160 has a chassis 138 having multiple slots 142. It should be appreciated that chassis 138 may be referred to as a housing, enclosure, or rack unit. In one embodiment, the chassis 138 has fourteen slots 142, although other numbers of slots are readily devised. For example, some embodiments have four slots, eight slots, sixteen slots, thirty-two slots, or other suitable number of slots. Each slot 142 can accommodate one storage node 150 in some embodiments. Chassis 138 includes flaps 148 that can be utilized to mount the chassis 138 on a rack. Fans 144 provide air circulation for cooling of the storage nodes 150 and components thereof, although other cooling components could be used, or an embodiment could be devised without cooling components. A switch fabric 146 couples storage nodes 150 within chassis 138 together and to a network for communication to the memory. In an embodiment depicted in FIG. 1, the slots 142 to the left of the switch fabric 146 and fans 144 are shown occupied by storage nodes 150, while the slots 142 to the right of the switch fabric 146 and fans 144 are empty and available for insertion of storage node 150 for illustrative purposes. This configuration is one example, and one or more storage nodes 150 could occupy the slots 142 in various further arrangements. The storage node arrangements need not be sequential or adjacent in some embodiments. Storage nodes 150 are hot pluggable, meaning that a storage node 150 can be inserted into a slot 142 in the chassis 138, or removed from a slot 142, without stopping or powering down the system. Upon insertion or removal of storage node 150 from slot 142, the system automatically reconfigures in order to recognize and adapt to the change. Reconfiguration, in some embodiments, includes restoring redundancy and/or rebalancing data or load.


Each storage node 150 can have multiple components. In the embodiment shown here, the storage node 150 includes a printed circuit board 158 populated by a CPU 156, i.e., processor, a memory 154 coupled to the CPU 156, and a non-volatile solid state storage 152 coupled to the CPU 156, although other mountings and/or components could be used in further embodiments. The memory 154 has instructions which are executed by the CPU 156 and/or data operated on by the CPU 156. As further explained below, the non-volatile solid state storage 152 includes flash or, in further embodiments, other types of solid-state memory.


Storage cluster 160 is scalable, meaning that storage capacity with non-uniform storage sizes is readily added, as described above. One or more storage nodes 150 can be plugged into or removed from each chassis and the storage cluster self-configures in some embodiments. Plug-in storage nodes 150, whether installed in a chassis as delivered or later added, can have different sizes. For example, in one embodiment a storage node 150 can have any multiple of 4 TB, e.g., 8 TB, 12 TB, 16 TB, 32 TB, etc. In further embodiments, a storage node 150 could have any multiple of other storage amounts or capacities. Storage capacity of each storage node 150 is broadcast, and influences decisions of how to stripe the data. For maximum storage efficiency, an embodiment can self-configure as wide as possible in the stripe, subject to a predetermined requirement of continued operation with loss of up to one, or up to two, non-volatile solid state storage units 152 or storage nodes 150 within the chassis.



FIG. 2 is a block diagram showing a communications interconnect 170 and power distribution bus 172 coupling multiple storage nodes 150. Referring back to FIG. 1, the communications interconnect 170 can be included in or implemented with the switch fabric 146 in some embodiments. Where multiple storage clusters 160 occupy a rack, the communications interconnect 170 can be included in or implemented with a top of rack switch, in some embodiments. As illustrated in FIG. 2, storage cluster 160 is enclosed within a single chassis 138. External port 176 is coupled to storage nodes 150 through communications interconnect 170, while external port 174 is coupled directly to a storage node. External power port 178 is coupled to power distribution bus 172. Storage nodes 150 may include varying amounts and differing capacities of non-volatile solid state storage 152. In addition, one or more storage nodes 150 may be a compute only storage node. Authorities 168 are implemented on the non-volatile solid state storages 152, for example as lists or other data structures stored in memory. In some embodiments the authorities are stored within the non-volatile solid state storage 152 and supported by software executing on a controller or other processor of the non-volatile solid state storage 152. In a further embodiment, authorities 168 are implemented on the storage nodes 150, for example as lists or other data structures stored in the memory 154 and supported by software executing on the CPU 156 of the storage node 150. Authorities 168 control how and where data is stored in the non-volatile solid state storages 152 in some embodiments. This control assists in determining which type of erasure coding scheme is applied to the data, and which storage nodes 150 have which portions of the data. Each authority 168 may be assigned to a non-volatile solid state storage 152. Each authority may control a range of inode numbers, segment numbers, or other data identifiers which are assigned to data by a file system, by the storage nodes 150, or by the non-volatile solid state storage 152, in various embodiments.


Every piece of data, and every piece of metadata, has redundancy in the system in some embodiments. In addition, every piece of data and every piece of metadata has an owner, which may be referred to as an authority. If that authority is unreachable, for example through failure of a storage node, there is a plan of succession for how to find that data or that metadata. In various embodiments, there are redundant copies of authorities 168. Authorities 168 have a relationship to storage nodes 150 and non-volatile solid state storage 152 in some embodiments. Each authority 168, covering a range of data segment numbers or other identifiers of the data, may be assigned to a specific non-volatile solid state storage 152. In some embodiments the authorities 168 for all of such ranges are distributed over the non-volatile solid state storages 152 of a storage cluster. Each storage node 150 has a network port that provides access to the non-volatile solid state storage(s) 152 of that storage node 150. Data can be stored in a segment, which is associated with a segment number and that segment number is an indirection for a configuration of a RAID (redundant array of independent disks) stripe in some embodiments. The assignment and use of the authorities 168 thus establishes an indirection to data. Indirection may be referred to as the ability to reference data indirectly, in this case via an authority 168, in accordance with some embodiments. A segment identifies a set of non-volatile solid state storage 152 and a local identifier into the set of non-volatile solid state storage 152 that may contain data. In some embodiments, the local identifier is an offset into the device and may be reused sequentially by multiple segments. In other embodiments the local identifier is unique for a specific segment and never reused. The offsets in the non-volatile solid state storage 152 are applied to locating data for writing to or reading from the non-volatile solid state storage 152 (in the form of a RAID stripe). Data is striped across multiple units of non-volatile solid state storage 152, which may include or be different from the non-volatile solid state storage 152 having the authority 168 for a particular data segment.


If there is a change in where a particular segment of data is located, e.g., during a data move or a data reconstruction, the authority 168 for that data segment should be consulted, at that non-volatile solid state storage 152 or storage node 150 having that authority 168. In order to locate a particular piece of data, embodiments calculate a hash value for a data segment or apply an inode number or a data segment number. The output of this operation points to a non-volatile solid state storage 152 having the authority 168 for that particular piece of data. In some embodiments there are two stages to this operation. The first stage maps an entity identifier (ID), e.g., a segment number, inode number, or directory number to an authority identifier. This mapping may include a calculation such as a hash or a bit mask. The second stage is mapping the authority identifier to a particular non-volatile solid state storage 152, which may be done through an explicit mapping. The operation is repeatable, so that when the calculation is performed, the result of the calculation repeatably and reliably points to a particular non-volatile solid state storage 152 having that authority 168. The operation may include the set of reachable storage nodes as input. If the set of reachable non-volatile solid state storage units changes the optimal set changes. In some embodiments, the persisted value is the current assignment (which is always true) and the calculated value is the target assignment the cluster will attempt to reconfigure towards. This calculation may be used to determine the optimal non-volatile solid state storage 152 for an authority in the presence of a set of non-volatile solid state storage 152 that are reachable and constitute the same cluster. The calculation also determines an ordered set of peer non-volatile solid state storage 152 that will also record the authority to non-volatile solid state storage mapping so that the authority may be determined even if the assigned non-volatile solid state storage is unreachable. A duplicate or substitute authority 168 may be consulted if a specific authority 168 is unavailable in some embodiments.


Two of the many tasks of the CPU 156 on a storage node 150 are to break up write data, and reassemble read data. When the system has determined that data is to be written, the authority 168 for that data is located as above. When the segment ID for data is already determined the request to write is forwarded to the non-volatile solid state storage 152 currently determined to be the host of the authority 168 determined from the segment. The host CPU 156 of the storage node 150, on which the non-volatile solid state storage 152 and corresponding authority 168 reside, then breaks up or shards the data and transmits the data out to various non-volatile solid state storage 152. The transmitted data is written as a data stripe in accordance with an erasure coding scheme. In some embodiments, data is requested to be pulled, and in other embodiments, data is pushed. In reverse, when data is read, the authority 168 for the segment ID containing the data is located as described above. The host CPU 156 of the storage node 150 on which the non-volatile solid state storage 152 and corresponding authority 168 reside requests the data from the non-volatile solid state storage and corresponding storage nodes pointed to by the authority. In some embodiments the data is read from flash storage as a data stripe. The host CPU 156 of storage node 150 then reassembles the read data, correcting any errors (if present) according to the appropriate erasure coding scheme, and forwards the reassembled data to the network. In further embodiments, some or all of these tasks can be handled in the non-volatile solid state storage 152. In some embodiments, the segment host requests the data be sent to storage node 150 by requesting pages from storage and then sending the data to the storage node making the original request.


In some systems, for example in UNIX-style file systems, data is handled with an index node or inode, which specifies a data structure that represents an object in a file system. The object could be a file or a directory, for example. Metadata may accompany the object, as attributes such as permission data and a creation timestamp, among other attributes. A segment number could be assigned to all or a portion of such an object in a file system. In other systems, data segments are handled with a segment number assigned elsewhere. For purposes of discussion, the unit of distribution is an entity, and an entity can be a file, a directory or a segment. That is, entities are units of data or metadata stored by a storage system. Entities are grouped into sets called authorities. Each authority has an authority owner, which is a storage node that has the exclusive right to update the entities in the authority. In other words, a storage node contains the authority, and that the authority, in turn, contains entities.


A segment is a logical container of data in accordance with some embodiments. A segment is an address space between medium address space and physical flash locations, i.e., the data segment number, are in this address space. Segments may also contain metadata, which enable data redundancy to be restored (rewritten to different flash locations or devices) without the involvement of higher level software. In one embodiment, an internal format of a segment contains client data and medium mappings to determine the position of that data. Each data segment is protected, e.g., from memory and other failures, by breaking the segment into a number of data and parity shards, where applicable. The data and parity shards are distributed, i.e., striped, across non-volatile solid state storage 152 coupled to the host CPUs 156 in accordance with an erasure coding scheme. Usage of the term segments refers to the container and its place in the address space of segments in some embodiments. Usage of the term stripe refers to the same set of shards as a segment and includes how the shards are distributed along with redundancy or parity information in accordance with some embodiments.


A series of address-space transformations takes place across an entire storage system. At the top is the directory entries (file names) which link to an inode. Inodes point into medium address space, where data is logically stored. Medium addresses may be mapped through a series of indirect mediums to spread the load of large files, or implement data services like deduplication or snapshots. Medium addresses may be mapped through a series of indirect mediums to spread the load of large files, or implement data services like deduplication or snapshots. Segment addresses are then translated into physical flash locations. Physical flash locations have an address range bounded by the amount of flash in the system in accordance with some embodiments. Medium addresses and segment addresses are logical containers, and in some embodiments use a 128 bit or larger identifier so as to be practically infinite, with a likelihood of reuse calculated as longer than the expected life of the system. Addresses from logical containers are allocated in a hierarchical fashion in some embodiments. Initially, each non-volatile solid state storage 152 may be assigned a range of address space. Within this assigned range, the non-volatile solid state storage 152 is able to allocate addresses without synchronization with other non-volatile solid state storage 152.


Data and metadata is stored by a set of underlying storage layouts that are optimized for varying workload patterns and storage devices. These layouts incorporate multiple redundancy schemes, compression formats and index algorithms. Some of these layouts store information about authorities and authority masters, while others store file metadata and file data. The redundancy schemes include error correction codes that tolerate corrupted bits within a single storage device (such as a NAND flash chip), erasure codes that tolerate the failure of multiple storage nodes, and replication schemes that tolerate data center or regional failures. In some embodiments, low density parity check (LDPC) code is used within a single storage unit. Reed-Solomon encoding is used within a storage cluster, and mirroring is used within a storage grid in some embodiments. Metadata may be stored using an ordered log structured index (such as a Log Structured Merge Tree), and large data may not be stored in a log structured layout.


In order to maintain consistency across multiple copies of an entity, the storage nodes agree implicitly on two things through calculations: (1) the authority that contains the entity, and (2) the storage node that contains the authority. The assignment of entities to authorities can be done by pseudorandomly assigning entities to authorities, by splitting entities into ranges based upon an externally produced key, or by placing a single entity into each authority. Examples of pseudorandom schemes are linear hashing and the Replication Under Scalable Hashing (RUSH) family of hashes, including Controlled Replication Under Scalable Hashing (CRUSH). In some embodiments, pseudo-random assignment is utilized only for assigning authorities to nodes because the set of nodes can change. The set of authorities cannot change so any subjective function may be applied in these embodiments. Some placement schemes automatically place authorities on storage nodes, while other placement schemes rely on an explicit mapping of authorities to storage nodes. In some embodiments, a pseudorandom scheme is utilized to map from each authority to a set of candidate authority owners. A pseudorandom data distribution function related to CRUSH may assign authorities to storage nodes and create a list of where the authorities are assigned. Each storage node has a copy of the pseudorandom data distribution function, and can arrive at the same calculation for distributing, and later finding or locating an authority. Each of the pseudorandom schemes requires the reachable set of storage nodes as input in some embodiments in order to conclude the same target nodes. Once an entity has been placed in an authority, the entity may be stored on physical devices so that no expected failure will lead to unexpected data loss. In some embodiments, rebalancing algorithms attempt to store the copies of all entities within an authority in the same layout and on the same set of machines.


Examples of expected failures include device failures, stolen machines, datacenter fires, and regional disasters, such as nuclear or geological events. Different failures lead to different levels of acceptable data loss. In some embodiments, a stolen storage node impacts neither the security nor the reliability of the system, while depending on system configuration, a regional event could lead to no loss of data, a few seconds or minutes of lost updates, or even complete data loss.


In the embodiments, the placement of data for storage redundancy is independent of the placement of authorities for data consistency. In some embodiments, storage nodes that contain authorities do not contain any persistent storage. Instead, the storage nodes are connected to non-volatile solid state storage units that do not contain authorities. The communications interconnect between storage nodes and non-volatile solid state storage units consists of multiple communication technologies and has non-uniform performance and fault tolerance characteristics. In some embodiments, as mentioned above, non-volatile solid state storage units are connected to storage nodes via PCI express, storage nodes are connected together within a single chassis using an Ethernet backplane, and chassis are connected together to form a storage cluster. Storage clusters are connected to clients using Ethernet or fiber channel in some embodiments. If multiple storage clusters are configured into a storage grid, the multiple storage clusters are connected using the Internet or other long-distance networking links, such as a “metro scale” link or private link that does not traverse the internet.


Authority owners have the exclusive right to modify entities, to migrate entities from one non-volatile solid state storage unit to another non-volatile solid state storage unit, and to add and remove copies of entities. This allows for maintaining the redundancy of the underlying data. When an authority owner fails, is going to be decommissioned, or is overloaded, the authority is transferred to a new storage node. Transient failures make it non-trivial to ensure that all non-faulty machines agree upon the new authority location. The ambiguity that arises due to transient failures can be achieved automatically by a consensus protocol such as Paxos, hot-warm failover schemes, via manual intervention by a remote system administrator, or by a local hardware administrator (such as by physically removing the failed machine from the cluster, or pressing a button on the failed machine). In some embodiments, a consensus protocol is used, and failover is automatic. If too many failures or replication events occur in too short a time period, the system goes into a self-preservation mode and halts replication and data movement activities until an administrator intervenes in accordance with some embodiments.


As authorities are transferred between storage nodes and authority owners update entities in their authorities, the system transfers messages between the storage nodes and non-volatile solid state storage units. With regard to persistent messages, messages that have different purposes are of different types. Depending on the type of the message, the system maintains different ordering and durability guarantees. As the persistent messages are being processed, the messages are temporarily stored in multiple durable and non-durable storage hardware technologies. In some embodiments, messages are stored in RAM, NVRAM and on NAND flash devices, and a variety of protocols are used in order to make efficient use of each storage medium. Latency-sensitive client requests may be persisted in replicated NVRAM, and then later NAND, while background rebalancing operations are persisted directly to NAND.


Persistent messages are persistently stored prior to being replicated. This allows the system to continue to serve client requests despite failures and component replacement. Although many hardware components contain unique identifiers that are visible to system administrators, manufacturer, hardware supply chain and ongoing monitoring quality control infrastructure, applications running on top of the infrastructure address virtualize addresses. These virtualized addresses do not change over the lifetime of the storage system, regardless of component failures and replacements. This allows each component of the storage system to be replaced over time without reconfiguration or disruptions of client request processing.


In some embodiments, the virtualized addresses are stored with sufficient redundancy. A continuous monitoring system correlates hardware and software status and the hardware identifiers. This allows detection and prediction of failures due to faulty components and manufacturing details. The monitoring system also enables the proactive transfer of authorities and entities away from impacted devices before failure occurs by removing the component from the critical path in some embodiments.


In addition to component redundancy in the communication channel, storage cluster 160 is configured to allow for the loss of one or more storage nodes 150. In some embodiments this cluster redundancy level may be one for relatively small storage clusters 160 (less than 8 storage nodes 150) and two for relatively larger storage clusters 160 (8 or more storage nodes 150) although any number would be suitable for the cluster redundancy level. In some embodiments, where more storage nodes 150 than the redundancy level are lost, the storage cluster 160 cannot guarantee availability of data or integrity of future updates. As mentioned above, data redundancy is implemented via segments. A segment is formed by selecting equal sized shards from a subset of the non-volatile solid state storage 152, each within a different storage node 150. Shards are reserved to establish the redundancy level, e.g., one or two, and then a remainder constitutes the data (the data shards). The shards are encoded using an ECC scheme such as parity or Reed-Soloman (RAID 6), so that any subset of the shards equal in count to the data shards may be used to reconstruct the complete data. The storage cluster redundancy represents a minimum level of redundancy and it may be exceeded for any individual data element. Segments are stored as a set of non-volatile solid state storage units, roles (data position or parity) and allocation unit local to each non-volatile solid state storage unit. The allocation units may be a physical address or an indirection determined within the non-volatile solid state storage 152. Each shard may be portioned into pages and each page into code words. In some embodiments, the pages are between about 4 kilobytes (kB) and 64 kB, e.g., 16 kB, while the code words are between about 512 bytes to 4 kB, e.g., 1 kB. These sizes are one example and not meant to be limiting as any suitable size for the code words and the pages may be utilized. The code words contain local error correction and a checksum to verify the error correction was successful. This checksum is “salted” with the logical address of the contents meaning that a failure to match the checksum may occur if the data is uncorrectable or misplaced. In some embodiments, when a code word fails a checksum it is converted to an “erasure” for purpose of the error correction algorithm so that the code word may be rebuilt.



FIG. 3 is a multiple level block diagram, showing contents of a storage node 150 and contents of a non-volatile solid state storage 152 of the storage node 150. Data is communicated to and from the storage node 150 by a network interface controller (NIC) 202 in some embodiments. Each storage node 150 has a CPU 156, and one or more non-volatile solid state storage 152, as discussed above. Moving down one level in FIG. 3, each non-volatile solid state storage 152 has a relatively fast non-volatile solid state memory, such as nonvolatile random access memory (NVRAM) 204, and flash memory 206. In some embodiments, NVRAM 204 may be a component that does not require program/erase cycles (DRAM, MRAM, PCM), and can be a memory that can support being written vastly more often than the memory is read from. Moving down another level in FIG. 3, the NVRAM 204 is implemented in one embodiment as high speed volatile memory, such as dynamic random access memory (DRAM) 216, backed up by energy reserve 218. Energy reserve 218 provides sufficient electrical power to keep the DRAM 216 powered long enough for contents to be transferred to the flash memory 206 in the event of power failure. In some embodiments, energy reserve 218 is a capacitor, super-capacitor, battery, or other device, that supplies a suitable supply of energy sufficient to enable the transfer of the contents of DRAM 216 to a stable storage medium in the case of power loss. The flash memory 206 is implemented as multiple flash dies 222, which may be referred to as packages of flash dies 222 or an array of flash dies 222. It should be appreciated that the flash dies 222 could be packaged in any number of ways, with a single die per package, multiple dies per package (i.e. multichip packages), in hybrid packages, as bare dies on a printed circuit board or other substrate, as encapsulated dies, etc. In the embodiment shown, the non-volatile solid state storage 152 has a controller 212 or other processor, and an input output (I/O) port 210 coupled to the controller 212. I/O port 210 is coupled to the CPU 156 and/or the network interface controller 202 of the flash storage node 150. Flash input output (I/O) port 220 is coupled to the flash dies 222, and a direct memory access unit (DMA) 214 is coupled to the controller 212, the DRAM 216 and the flash dies 222. In the embodiment shown, the I/O port 210, controller 212, DMA unit 214 and flash I/O port 220 are implemented on a programmable logic device (PLD) 208, e.g., a field programmable gate array (FPGA). In this embodiment, each flash die 222 has pages, organized as sixteen kB (kilobyte) pages 224, and a register 226 through which data can be written to or read from the flash die 222. In further embodiments, other types of solid-state memory are used in place of, or in addition to flash memory illustrated within flash die 222.



FIG. 4 is a block diagram showing a computing and storage system creating a virtual file server, e.g., virtual server 184, with a preserved MAC (media access control) address, in accordance with some embodiments. The embodiment depicted in FIG. 4 can create one or more virtual servers 184, and for each virtual server 184 assign a MAC address, and assign an IP (Internet Protocol) address to the MAC address. Assignments of various pieces of physical hardware to the virtual server 184 can be changed while the MAC address remains fixed or is preserved. By contrast, when a physical file server is assigned an IP address, the IP address is assigned to a portion of, or one or more actual file servers with hardware resources. This is accomplished using hardware identifiers, including the MAC address(es) of the hardware. The MAC address is used for communication on a physical network segment, e.g., as a network address. In the OSI (Open Systems Interconnect) model, MAC addresses are applied in the media access control protocol sub layer. With physical hardware, the MAC address is usually assigned by the manufacturer. For example the manufacturer of a network interface controller (NIC) places a registered identification number in the network interface controller, which remains unchanged for the life of the product. If a file server is replaced, e.g., in an upgrade, the new file server will have a new network interface controller and a new MAC address. System upgrades, then, usually require propagating the new MAC address throughout the system.


Still referring to FIG. 4, in order to avoid such disruption, the embodiments preserve the MAC address. In creating a virtual file server (e.g., virtual server 184), MAC addresses, IP addresses, and VLAN (virtual local area network) configurations can remain permanent, while the hardware underneath can change. For example, a storage node 150 can be swapped out, and a new storage node 150 can be swapped in, one or more storage nodes 150 can be added or removed, a non-volatile solid-state storage 152 can be swapped, or one or more non-volatile solid-state storages 152 added or removed, without changing the MAC address, IP address and VLAN configuration of a virtual server 184. Storage nodes 150, as physical computing and storage devices, can have actual MAC addresses, and that the virtual server 184 can have a differing MAC address which the system preserves. The outside world, i.e., network accesses from outside of a computing and storage system, sees an IP address and a MAC address of the virtual server 184 as unchanging, and does not see changes to underlying hardware. The assigned MAC address of the virtual server 184 is thus a virtual MAC address.


A virtual server 184 of FIG. 4 has physical resources which are assigned to the virtual server. The processing controller 110, the networking controller 112, and the storage controller 114 (see FIG. 2) cooperate to assign computing resources (e.g., one or more processors, local memory), and storage resources (e.g., storage memory) of one or more storage nodes 150 to each of one or more virtual servers 184. Each storage node 150 may have one or more non-volatile solid-state storages 152. Network resources, e.g., as arranged through switching and routing to and from various storage nodes 150, are also assigned to each of the one or more virtual servers 184. An IP address, a MAC address, a VLAN configuration, and/or a filesystem (e.g., with directory structure, file namespace, permissions, etc.) are assigned to and configured in the computing and storage resources of the storage nodes 150 and non-volatile solid-state storages 152, for each virtual server 184. In order to do so, the processing controller 110, the networking controller 112, and the storage controller 114 keep track of the physical resources, including the physical MAC address(es) of hardware assigned to each virtual server 184. Particularly, the correspondence between the virtual MAC address and one or more physical MAC addresses of physical resources assigned to the virtual server 184 is tracked. This can be accomplished with tables, lists, maps, or other data structures 180 as are readily devised in accordance with the teachings herein. For example, a data structure 180 could be coupled to or included in one or more of the storage nodes 150 or non-volatile solid-state storages 152. Redundant copies of the data structures 180 could be distributed throughout the storage nodes 150 or non-volatile solid-state storages 152. The data structure 180 may be coupled to the networking controller 112, in order to track an IP address, a virtual MAC address, and a physical MAC address.


The processing controller 110 can assign physical computing resources to the virtual server 17, while networking controller 112 can assign network resources to the virtual server 184, and assign a virtual MAC address to the virtual server 184. The storage controller 114 assigns storage memory resources to the virtual server 184. For example, an IP address and a MAC address for a virtual server 184 could be assigned to one or more storage nodes 150 having associated MAC addresses of physical hardware. A network access to a file stored on the virtual server 184 is via the IP address corresponding to the virtual MAC address in some embodiments. A storage node 150 may be swapped out, or the virtual server 184 may be reconfigured for a differing amount of resources. In these instances one or more differing storage nodes 150 with associated MAC addresses of physical hardware could be assigned to the virtual server 184, which would retain the IP address and the MAC address originally assigned to the virtual server 184. A virtual server 184 can include an assignment of physical resources for a virtual Ethernet adapter 182, which could be associated with the virtual MAC address assigned to the virtual server 184 even though the actual hardware could include an actual (physical) Ethernet adapter with a differing MAC address. Alternatively, a virtual Ethernet adapter 182 could be configured from other hardware such as a programmable logic device (PLD), or firmware. The MAC address is preserved when storage nodes 150 and/or non-volatile solid-state storages 152 self-configure or self-reconfigure, and when physical changes are made to a computing and storage system in the above embodiments. In other words, changes to the physical computing resources, the network resources and/or the storage memory resources assigned to a virtual server 184 leave the virtual MAC address of the virtual server 184 unchanged. The virtual MAC address is thus a virtual entity that hides the underlying physical structure in a virtualized environment, which can change during operation.


In various scenarios, each of the processing controller 110, the networking controller 112 and the storage controller 114 could be dedicated physical servers or portions of one or more physical servers, or could be allocated as virtual servers 184 or other virtual resources from physical computing resources. For example, one, two or all three of these controllers 110, 112, 114 could be allocated as one or more virtual servers 184 using the resources of a storage cluster 160. Or, the roles of the processing controller 110, the networking controller 112 in the storage controller 114 could be flexibly allocated among the storage nodes 150 in a storage cluster 160, so that the responsibilities for some of the virtual servers 184 are performed by some of the storage nodes 150, and the responsibilities for others of the virtual servers 184 are performed by others of the storage nodes 150, and these may change during operation. The same storage cluster 160, or another storage cluster 160, could allocate resources for one or more virtual servers 184, as shown in FIG. 4. A MAC address could then be allocated and preserved for a specified virtual server 184. During operation, user data is sent to that virtual MAC address, and the physical resources underlying the virtual server 184 can change during operation as storage needs change, while the MAC address is preserved. Storage requests could be received by a physical server or a virtual server 184 and forwarded to potentially any of the storage nodes 150 in the storage cluster 160. The storage node 150, to which the storage request is forwarded, could have a physical MAC address that differs from the virtual MAC address. In some embodiments, there is a one-to-many mapping, in which the virtual MAC address is mapped to multiple physical MAC addresses corresponding to multiple storage nodes 150. This mapping can change over time, as physical computing resources are reallocated in the virtual computing environment. In other words, the virtual server 184 is provisioned as an addressing point (the preserved MAC address), but each storage request can be distributed flexibly among the storage nodes 150, none, some, many, or each of which could have its own physical MAC address that differs from the virtual MAC address. The one-to-many mapping decouples the physical layer from the virtual layer.



FIG. 5 is a multiple level block diagram, showing contents of a storage node 150 and contents of a non-volatile solid-state storage 152 of the storage node 150. Data is communicated to and from the storage node 150 by a network interface controller (NIC) 202 in some embodiments. The network interface controller 202 has a physical MAC address. Each storage node 150 has a CPU 156, and one or more non-volatile solid-state storage 152, as discussed above. Moving down one level in FIG. 5, each non-volatile solid-state storage 152 has a relatively fast non-volatile solid-state memory, such as non-volatile random access memory (NVRAM) 204, and flash memory 206. In some embodiments, NVRAM 204 may be a component that does not require program/erase cycles (DRAM, MRAM, PCM), and can be a memory that can support being written vastly more often than the memory is read from. Moving down another level in FIG. 5, the NVRAM 204 is implemented in one embodiment as high speed volatile memory, such as dynamic random access memory (DRAM) 216, backed up by energy reserve 218. Energy reserve 218 provides sufficient electrical power to keep the DRAM 216 powered long enough for contents to be transferred to the flash memory 206 in the event of power failure. In some embodiments, energy reserve 218 is a capacitor, super-capacitor, battery, or other device, that supplies a suitable supply of energy sufficient to enable the transfer of the contents of DRAM 216 to a stable storage medium in the case of power loss. The flash memory 206 is implemented as multiple flash dies 222, which may be referred to as packages of flash dies 222 or an array of flash dies 222. It should be appreciated that the flash dies 222 could be packaged in any number of ways, with a single die per package, multiple dies per package (i.e. multichip packages), in hybrid packages, as bare dies on a printed circuit board or other substrate, as encapsulated dies, etc. In the embodiment shown, the non-volatile solid-state storage 152 has a controller 212 or other processor, and an input output (I/O) port 210 coupled to the controller 212. I/O port 210 is coupled to the CPU 156 and/or the network interface controller 202 of the flash storage node 150. Flash input output (I/O) port 220 is coupled to the flash dies 222, and a direct memory access unit (DMA) 214 is coupled to the controller 212, the DRAM 216 and the flash dies 222. In the embodiment shown, the I/O port 210, controller 212, DMA unit 214 and flash I/O port 220 are implemented on a programmable logic device (PLD) 208, e.g., a field programmable gate array (FPGA). In this embodiment, each flash die 222 has pages, organized as sixteen kB (kilobyte) pages 224, and a register 226 through which data can be written to or read from the flash die 222. In further embodiments, other types of solid-state memory are used in place of, or in addition to flash memory illustrated within flash die 222.


With reference to FIG. 4, and FIG. 5, the assignment of the preserved MAC address is stored in the storage nodes 150, in various embodiments, with a similar level of redundancy and error recovery capability as that of the user data. For example, the assignment of the preserved MAC address could be stored (e.g., in a data structure) as metadata in the flash memory 206, or in the DRAM 216, of one of the storage nodes 150, with one or more redundant copies in one or more of the other storage nodes 150. Alternatively, the assignment of the preserved MAC address could be stored in the storage nodes 150 as system data, in a manner similar to user data, with error correction code or other erasure coding comparable to that of user data in some embodiments. Assignment of the virtual MAC address is then recoverable despite loss of one or two of the storage nodes 150.



FIG. 6 is a flow diagram of a method for assigning a media access control address in a computing and storage system, which can be practiced on or by embodiments of the storage cluster, storage nodes and/or non-volatile solid-state storages in accordance with some embodiments. In action 602, physical computing resources are assigned to a virtual server. The assignment could include assigning one or more processors and local memory from a pool of resources to the virtual server. In action 604, physical storage memory resources are assigned to the virtual server where one or more non-volatile solid-state storages or storage nodes to the virtual server in some embodiments. In action 606, physical network resources are assigned to the virtual server. In a similar manner, this could include assigning a configuration of network resources as a virtual local area network.


In decision action 608, it is determined if the virtual server is previously assigned. If the answer is no, the virtual server is not previously assigned and may be a new virtual server, flow continues to action 610. If the answer is yes, the virtual server is previously assigned, flow continues to action 614. In action 610, a new virtual MAC address is assigned to the virtual server. This could include tracking the correspondence between the virtual MAC address and one or more physical MAC addresses of hardware resources assigned to the virtual server. In action 612, a new IP address is assigned to the virtual server and may include tracking the correspondence between the IP address and the hardware resources assigned to the virtual server, or tracking the correspondence between the IP address and one or more physical MAC addresses of hardware resources assigned to the virtual server. Flow continues to decision action 618.


Flow arrives at action 614 if the determination from the decision action 608 is that the virtual server is previously assigned. In action 614, the same virtual MAC address is assigned to the virtual server. The same IP address is assigned to the virtual server, in action 616. Flow continues to decision action 618. In decision action 618, it is determined if there are changes to the physical resources. If the answer is no, there are no changes to the physical resources, the flow continues to decision action 620. If the answer is yes, there are changes to the physical resources, flow continues to action 602, in order to assign physical computing resources, physical storage memory resources, and physical network resources to the virtual server. In turn, the virtual server will have the same virtual MAC address and the same IP address reassigned to it. In decision action 620, it is determined if there are changes to the configuration of the virtual server. If the answer is no, there are no changes to the configuration of the virtual sever, the flow continues to decision action 622. If the answer is yes, there are changes to the configuration of the virtual sever, flow continues to action 602, in order to assign physical computing resources, physical storage memory resources, and physical network resources to the virtual server, which maintains the same virtual MAC address and the same IP address. In decision action 622, it is determined if an additional virtual server is created. If the answer is no, there is no additional virtual server created, the flow proceeds back to decision action 618, and repeats a loop until or unless there is a change to physical resources, a change to a configuration of a virtual server, or the creation of an additional virtual server. If the answer in decision action 622 is yes, there is an additional virtual server created, the flow branches back to action 602, in order to assign physical resources to the new virtual server, and repeats as described above. In variations to the method, the decision actions 618, 620, 622 could be performed in various differing orders or in parallel, with exits to the decision actions 618, 620, 622 branching the flow accordingly. Assigning physical resources to a new virtual server might affect the assignment of physical resources to the virtual server previously configured. However, the previously created virtual server retains the previously assigned MAC address, and the new virtual server would get a new, differing MAC address which is retained over time.


It should be appreciated that the methods described herein may be performed with a digital processing system, such as a conventional, general-purpose computer system. Special purpose computers, which are designed or programmed to perform only one function may be used in the alternative. FIG. 7 is an illustration showing an exemplary computing device which may implement the embodiments described herein. The computing device of FIG. 7 may be used to perform embodiments of the functionality for a storage node or a non-volatile solid-state storage in accordance with some embodiments. The computing device includes a central processing unit (CPU) 701, which is coupled through a bus 705 to a memory 703, and mass storage device 707. Mass storage device 707 represents a persistent data storage device such as a disc drive, which may be local or remote in some embodiments. The mass storage device 707 could implement a backup storage, in some embodiments. Memory 703 may include read only memory, random access memory, etc. Applications resident on the computing device may be stored on or accessed via a computer readable medium such as memory 703 or mass storage device 707 in some embodiments. Applications may also be in the form of modulated electronic signals modulated accessed via a network modem or other network interface of the computing device. It should be appreciated that CPU 701 may be embodied in a general-purpose processor, a special purpose processor, or a specially programmed logic device in some embodiments.


Display 711 is in communication with CPU 701, memory 703, and mass storage device 707, through bus 705. Display 711 is configured to display any visualization tools or reports associated with the system described herein. Input/output device 709 is coupled to bus 705 in order to communicate information in command selections to CPU 701. It should be appreciated that data to and from external devices may be communicated through the input/output device 709. CPU 701 can be defined to execute the functionality described herein to enable the functionality described with reference to FIGS. 1-6. The code embodying this functionality may be stored within memory 703 or mass storage device 707 for execution by a processor such as CPU 701 in some embodiments. The operating system on the computing device may be MS-WINDOWS™, UNIX™, LINUX™, iOS™, CentOS™, Android™, Redhat Linux™, z/OS™, or other known operating systems. It should be appreciated that the embodiments described herein may be integrated with virtualized computing system also.


Detailed illustrative embodiments are disclosed herein. However, specific functional details disclosed herein are merely representative for purposes of describing embodiments. Embodiments may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.


It should be understood that although the terms first, second, etc. may be used herein to describe various steps or calculations, these steps or calculations should not be limited by these terms. These terms are only used to distinguish one step or calculation from another. For example, a first calculation could be termed a second calculation, and, similarly, a second step could be termed a first step, without departing from the scope of this disclosure. As used herein, the term “and/or” and the “/” symbol includes any and all combinations of one or more of the associated listed items.


As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes”, and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Therefore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.


It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.


With the above embodiments in mind, it should be understood that the embodiments might employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. Further, the manipulations performed are often referred to in terms, such as producing, identifying, determining, or comparing. Any of the operations described herein that form part of the embodiments are useful machine operations. The embodiments also relate to a device or an apparatus for performing these operations. The apparatus can be specially constructed for the required purpose, or the apparatus can be a general-purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general-purpose machines can be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations.


A module, an application, a layer, an agent or other method-operable entity could be implemented as hardware, firmware, or a processor executing software, or combinations thereof. It should be appreciated that, where a software-based embodiment is disclosed herein, the software can be embodied in a physical machine such as a controller. For example, a controller could include a first module and a second module. A controller could be configured to perform various actions, e.g., of a method, an application, a layer or an agent.


The embodiments can also be embodied as computer readable code on a non-transitory computer readable medium. The computer readable medium is any data storage device that can store data, which can be thereafter read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical data storage devices. The computer readable medium can also be distributed over a network coupled computer system so that the computer readable code is stored and executed in a distributed fashion. Embodiments described herein may be practiced with various computer system configurations including hand-held devices, tablets, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a wire-based or wireless network.


Although the method operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or the described operations may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing.


In various embodiments, one or more portions of the methods and mechanisms described herein may form part of a cloud-computing environment. In such embodiments, resources may be provided over the Internet as services according to one or more various models. Such models may include Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and Software as a Service (SaaS). In IaaS, computer infrastructure is delivered as a service. In such a case, the computing equipment is generally owned and operated by the service provider. In the PaaS model, software tools and underlying equipment used by developers to develop software solutions may be provided as a service and hosted by the service provider. SaaS typically includes a service provider licensing software as a service on demand. The service provider may host the software, or may deploy the software to a customer for a given period of time. Numerous combinations of the above models are possible and are contemplated.


Various units, circuits, or other components may be described or claimed as “configured to” perform a task or tasks. In such contexts, the phrase “configured to” is used to connote structure by indicating that the units/circuits/components include structure (e.g., circuitry) that performs the task or tasks during operation. As such, the unit/circuit/component can be said to be configured to perform the task even when the specified unit/circuit/component is not currently operational (e.g., is not on). The units/circuits/components used with the “configured to” language include hardware—for example, circuits, memory storing program instructions executable to implement the operation, etc. Reciting that a unit/circuit/component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. 112, sixth paragraph, for that unit/circuit/component. Additionally, “configured to” can include generic structure (e.g., generic circuitry) that is manipulated by software and/or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in manner that is capable of performing the task(s) at issue. “Configured to” may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks.


The foregoing description, for the purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the embodiments and its practical applications, to thereby enable others skilled in the art to best utilize the embodiments and various modifications as may be suited to the particular use contemplated. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims
  • 1. A method, comprising: assigning a physical resource to a virtual server associated with a storage system;assigning a virtual MAC address to the virtual server;storing the virtual MAC address in a plurality of the storage nodes according to a redundancy scheme associated with data stored within the storage system;mapping the virtual MAC address, in a one-to-many mapping, to multiple physical MAC addresses corresponding to physical resources of the storage system;replacing the physical resource; andmaintaining the virtual MAC address with the virtual server while replacing the physical resource, the replaced physical resource having a differing physical MAC address than the physical resource.
  • 2. The method of claim 1, wherein the physical resource is one of a physical computing resource, a physical storage memory resource or a physical network resource.
  • 3. The method of claim 1, further comprising: assigning an Internet Protocol (IP) address to the virtual MAC address and reconfiguring the virtual server as to a differing physical MAC address, wherein the IP address and the virtual MAC address remain assigned to the virtual server.
  • 4. The method of claim 1, further comprising: tracking the virtual MAC address and a physical MAC address of the physical resource, via application of a data structure, wherein assignment of the virtual MAC address is preserved and recoverable despite loss of two of the plurality of storage nodes.
  • 5. The method of claim 1, further comprising: forwarding a storage request, addressed to the virtual MAC address to a storage node of a plurality of storage nodes assigned to the virtual server, the storage node having one of no physical MAC address, or a physical MAC address differing from the virtual MAC address.
  • 6. The method of claim 1, further comprising: assigning the virtual MAC address to a virtual Ethernet adapter, wherein the virtual Ethernet adapter is configured from a physical resource having a physical MAC address differing from the virtual MAC address.
  • 7. The method of claim 1, further comprising: accessing a file stored on the virtual server, via an IP address corresponding to the virtual MAC address.
  • 8. A storage system, comprising: a plurality of storage nodes having physical resources for storage of data, the plurality of storage nodes coupled as a storage cluster;the plurality of storage nodes configurable to distribute the data and metadata associated with the data throughout the plurality of storage nodes such that the plurality of storage nodes maintain ability to read the data, using erasure coding, despite a loss of two of the plurality of storage nodes; andthe physical resources configurable as a virtual server having a virtual media access control (MAC) address that is mapped in a one-to-many mapping to multiple physical MAC addresses corresponding to multiple ones of the plurality of storage nodes, the virtual MAC address preserved across changes to underlying hardware including removal from the virtual server of hardware having a physical MAC address, wherein the storage system stores the virtual MAC address in the plurality of the storage nodes in accordance with a redundancy scheme associated with the storage of the data.
  • 9. The computing and storage system of claim 8, further comprising: each of the plurality of storage nodes has a network interface controller with a physical MAC address differing from the virtual MAC address.
  • 10. The computing and storage system of claim 8, further comprising: a data structure configurable to track a correspondence of the virtual MAC address to at least one physical MAC address.
  • 11. The computing and storage system of claim 8, further comprising: the plurality of storage nodes configurable to couple to a network, and configured to support network access to a file in the plurality of storage nodes via an Internet Protocol (IP) address associated with the virtual MAC address.
  • 12. The computing and storage system of claim 8, further comprising: the plurality of storage nodes configurable to couple to a further one or more storage nodes and to reconfigure the physical resources, while the virtual server retains the virtual MAC address.
  • 13. The computing and storage system of claim 8, further comprising: a non-volatile solid-state memory having non-volatile random access memory (NVRAM) and flash, wherein data that tracks the virtual MAC address is stored in the NVRAM or the flash of more than one of the plurality of storage nodes.
  • 14. A storage system, comprising: a plurality of storage nodes coupled as a storage cluster, each storage node of the plurality of storage nodes having a non-volatile solid-state storage for storage of data, each storage node of the plurality of storage nodes configurable to couple to a network;the plurality of storage nodes configurable to distribute the data and metadata associated with the data throughout the plurality of storage nodes;physical resources configurable to assign the physical resources to a virtual server, wherein changes to the physical resources assigned to the virtual server leave a virtual MAC address of the virtual server unchanged, and wherein the virtual MAC address is stored across the plurality of the storage nodes so that the virtual MAC address is recoverable despite loss of one or more of the storage nodes; anda controller further configurable to map the virtual MAC address, in a one-to-many mapping, to multiple physical MAC addresses corresponding to multiple ones of the plurality of storage nodes.
  • 15. The computing and storage system of claim 14, further comprising: each storage node of the plurality of storage nodes having a network interface controller (NIC), wherein a MAC address of the NIC differs from the virtual MAC address.
  • 16. The computing and storage system of claim 14, further comprising: a data structure stored within the plurality of storage nodes, configurable to track the virtual MAC address and a plurality of physical MAC addresses of the plurality of storage nodes, the data structure recoverable from the plurality of storage nodes with the failure of the two of the plurality of storage nodes.
  • 17. The computing and storage system of claim 14, further comprising: a networking controller configurable to assign a virtual Ethernet adapter to the virtual server, from network resources, and configurable to assign the virtual MAC address to the virtual Ethernet adapter.
  • 18. The computing and storage system of claim 14, further comprising: a networking controller configurable to assign an Internet Protocol (IP) address to the virtual server, via application of the virtual MAC address.
  • 19. The computing and storage system of claim 14, further comprising: multiple controllers included associated with one or more virtual machines allocated from the plurality of storage nodes.
  • 20. The computing and storage system of claim 14, wherein the plurality of storage nodes is configured to support network access to a file in the plurality of storage nodes via an Internet Protocol (IP) address associated with the virtual MAC address.
US Referenced Citations (457)
Number Name Date Kind
5390327 Lubbers et al. Feb 1995 A
5450581 Bergen et al. Sep 1995 A
5479653 Jones Dec 1995 A
5488731 Mendelsohn Jan 1996 A
5504858 Ellis et al. Apr 1996 A
5564113 Bergen et al. Oct 1996 A
5574882 Menon et al. Nov 1996 A
5649093 Hanke et al. Jul 1997 A
5883909 Dekoning et al. Mar 1999 A
6000010 Legg Dec 1999 A
6260156 Garvin et al. Jul 2001 B1
6269453 Krantz Jul 2001 B1
6275898 DeKoning Aug 2001 B1
6453428 Stephenson Sep 2002 B1
6523087 Busser Feb 2003 B2
6535417 Tsuda Mar 2003 B2
6643748 Wieland Nov 2003 B1
6725392 Frey et al. Apr 2004 B1
6763455 Hall Jul 2004 B2
6836816 Kendall Dec 2004 B2
6985995 Holland et al. Jan 2006 B2
7032125 Holt et al. Apr 2006 B2
7047358 Lee et al. May 2006 B2
7051155 Talagala et al. May 2006 B2
7055058 Lee et al. May 2006 B2
7065617 Wang Jun 2006 B2
7069383 Yamamoto et al. Jun 2006 B2
7076606 Orsley Jul 2006 B2
7107480 Moshayedi et al. Sep 2006 B1
7159150 Kenchammana-Hosekote et al. Jan 2007 B2
7162575 Dalal et al. Jan 2007 B2
7164608 Lee Jan 2007 B2
7188270 Nanda et al. Mar 2007 B1
7334156 Land et al. Feb 2008 B2
7370220 Nguyen et al. May 2008 B1
7386666 Beauchamp et al. Jun 2008 B1
7398285 Kisley Jul 2008 B2
7424498 Patterson Sep 2008 B1
7424592 Karr Sep 2008 B1
7444532 Masuyama et al. Oct 2008 B2
7480658 Heinla et al. Jan 2009 B2
7484056 Madnani et al. Jan 2009 B2
7484057 Madnani et al. Jan 2009 B1
7484059 Ofer et al. Jan 2009 B1
7536506 Ashmore et al. May 2009 B2
7558859 Kasiolas Jul 2009 B2
7565446 Talagala et al. Jul 2009 B2
7613947 Coatney Nov 2009 B1
7634617 Misra Dec 2009 B2
7634618 Misra Dec 2009 B2
7681104 Sim-Tang et al. Mar 2010 B1
7681105 Sim-Tang et al. Mar 2010 B1
7681109 Yang et al. Mar 2010 B2
7730257 Franklin Jun 2010 B2
7730258 Smith Jun 2010 B1
7730274 Usgaonkar Jun 2010 B1
7743276 Jacobsen et al. Jun 2010 B2
7752489 Deenadhayalan et al. Jul 2010 B2
7757038 Kitahara Jul 2010 B2
7757059 Ofer et al. Jul 2010 B1
7778960 Chatterjee et al. Aug 2010 B1
7783955 Haratsch et al. Aug 2010 B2
7814272 Barrail et al. Oct 2010 B2
7814273 Barrail Oct 2010 B2
7818531 Barrail Oct 2010 B2
7827351 Suetsugu et al. Nov 2010 B2
7827439 Matthew et al. Nov 2010 B2
7831768 Ananthamurthy et al. Nov 2010 B2
7856583 Smith Dec 2010 B1
7870105 Arakawa et al. Jan 2011 B2
7873878 Belluomini et al. Jan 2011 B2
7885938 Greene et al. Feb 2011 B1
7886111 Klemm et al. Feb 2011 B2
7908448 Chatterjee et al. Mar 2011 B1
7916538 Jeon et al. Mar 2011 B2
7921268 Jakob Apr 2011 B2
7930499 Duchesne Apr 2011 B2
7941697 Mathew et al. May 2011 B2
7958303 Shuster Jun 2011 B2
7971129 Watson Jun 2011 B2
7984016 Kisley Jul 2011 B2
7991822 Bish et al. Aug 2011 B2
8006126 Deenadhayalan et al. Aug 2011 B2
8010485 Chatterjee et al. Aug 2011 B1
8010829 Chatterjee et al. Aug 2011 B1
8020047 Courtney Sep 2011 B2
8046548 Chatterjee et al. Oct 2011 B1
8051361 Sim-Tang et al. Nov 2011 B2
8051362 Li et al. Nov 2011 B2
8074038 Lionetti et al. Dec 2011 B2
8082393 Galloway et al. Dec 2011 B2
8086603 Nasre et al. Dec 2011 B2
8086634 Mimatsu Dec 2011 B2
8086911 Taylor Dec 2011 B1
8090837 Shin et al. Jan 2012 B2
8108502 Tabbara et al. Jan 2012 B2
8117388 Jernigan, IV Feb 2012 B2
8117521 Yang et al. Feb 2012 B2
8140821 Raizen et al. Mar 2012 B1
8145838 Miller et al. Mar 2012 B1
8145840 Koul et al. Mar 2012 B2
8175012 Haratsch et al. May 2012 B2
8176360 Frost et al. May 2012 B2
8176405 Hafner et al. May 2012 B2
8180855 Aiello et al. May 2012 B2
8200922 McKean et al. Jun 2012 B2
8209469 Carpenter et al. Jun 2012 B2
8225006 Karamcheti Jul 2012 B1
8239618 Kotzur et al. Aug 2012 B2
8244999 Chatterjee et al. Aug 2012 B1
8261016 Goel Sep 2012 B1
8271455 Kesselman Sep 2012 B2
8285686 Kesselman Oct 2012 B2
8305811 Jeon Nov 2012 B2
8315999 Chatley et al. Nov 2012 B2
8327080 Der Dec 2012 B1
8335769 Kesselman Dec 2012 B2
8341118 Drobychev et al. Dec 2012 B2
8351290 Huang et al. Jan 2013 B1
8364920 Parkison et al. Jan 2013 B1
8365041 Chu et al. Jan 2013 B2
8375146 Sinclair Feb 2013 B2
8397016 Talagala et al. Mar 2013 B2
8402152 Duran Mar 2013 B2
8412880 Leibowitz et al. Apr 2013 B2
8423739 Ash et al. Apr 2013 B2
8429436 Filingim et al. Apr 2013 B2
8452928 Ofer et al. May 2013 B1
8473698 Lionetti et al. Jun 2013 B2
8473778 Simitci Jun 2013 B2
8473815 Yu et al. Jun 2013 B2
8479037 Chatterjee et al. Jul 2013 B1
8484414 Sugimoto et al. Jul 2013 B2
8498967 Chatterjee et al. Jul 2013 B1
8522073 Cohen Aug 2013 B2
8533408 Madnani et al. Sep 2013 B1
8533527 Daikokuya et al. Sep 2013 B2
8539177 Ofer et al. Sep 2013 B1
8544029 Bakke et al. Sep 2013 B2
8549224 Zeryck et al. Oct 2013 B1
8583861 Ofer et al. Nov 2013 B1
8589625 Colgrove et al. Nov 2013 B2
8595455 Chatterjee et al. Nov 2013 B2
8615599 Takefman et al. Dec 2013 B1
8627136 Shankar et al. Jan 2014 B2
8627138 Clark Jan 2014 B1
8639669 Douglis et al. Jan 2014 B1
8639863 Kanapathippillai et al. Jan 2014 B1
8640000 Cypher Jan 2014 B1
8650343 Kanapathippillai et al. Feb 2014 B1
8660131 Vermont et al. Feb 2014 B2
8661218 Piszczek et al. Feb 2014 B1
8671072 Shah et al. Mar 2014 B1
8689042 Kanapathippillai et al. Apr 2014 B1
8700875 Barron et al. Apr 2014 B1
8706694 Chatterjee et al. Apr 2014 B2
8706914 Duchesneau Apr 2014 B2
8706932 Kanapathippillai et al. Apr 2014 B1
8712963 Douglis et al. Apr 2014 B1
8713405 Healey et al. Apr 2014 B2
8719621 Karmarkar May 2014 B1
8725730 Keeton et al. May 2014 B2
8751859 Becker-szendy et al. Jun 2014 B2
8756387 Frost et al. Jun 2014 B2
8762793 Grube et al. Jun 2014 B2
8838541 Camble et al. Jun 2014 B2
8769232 Suryabudi et al. Jul 2014 B2
8775858 Gower et al. Jul 2014 B2
8775868 Colgrove et al. Jul 2014 B2
8788913 Xin et al. Jul 2014 B1
8793447 Usgaonkar et al. Jul 2014 B2
8799746 Baker et al. Aug 2014 B2
8819311 Liao Aug 2014 B2
8819383 Jobanputra et al. Aug 2014 B1
8824261 Miller et al. Sep 2014 B1
8832528 Thatcher et al. Sep 2014 B2
8838892 Li Sep 2014 B2
8843700 Salessi et al. Sep 2014 B1
8850108 Hayes et al. Sep 2014 B1
8850288 Lazier et al. Sep 2014 B1
8856593 Eckhardt et al. Oct 2014 B2
8856619 Cypher Oct 2014 B1
8862617 Kesselman Oct 2014 B2
8862847 Feng et al. Oct 2014 B2
8862928 Xavier et al. Oct 2014 B2
8868825 Hayes Oct 2014 B1
8874836 Hayes Oct 2014 B1
8880793 Nagineni Nov 2014 B2
8880825 Lionetti et al. Nov 2014 B2
8886778 Nedved et al. Nov 2014 B2
8898383 Yamamoto et al. Nov 2014 B2
8898388 Kimmel Nov 2014 B1
8904231 Coatney et al. Dec 2014 B2
8918478 Ozzie et al. Dec 2014 B2
8930307 Colgrove et al. Jan 2015 B2
8930633 Amit et al. Jan 2015 B2
8943357 Atzmony Jan 2015 B2
8949502 McKnight et al. Feb 2015 B2
8959110 Smith et al. Feb 2015 B2
8959388 Kuang et al. Feb 2015 B1
8972478 Storer et al. Mar 2015 B1
8972779 Lee et al. Mar 2015 B2
8977597 Ganesh et al. Mar 2015 B2
8996828 Kalos et al. Mar 2015 B2
9003144 Hayes et al. Apr 2015 B1
9009724 Gold et al. Apr 2015 B2
9021053 Bernbo et al. Apr 2015 B2
9021215 Meir et al. Apr 2015 B2
9025393 Wu May 2015 B2
9043372 Makkar et al. May 2015 B2
9047214 Sharon et al. Jun 2015 B1
9053808 Sprouse Jun 2015 B2
9058155 Cepulis et al. Jun 2015 B2
9063895 Madnani et al. Jun 2015 B1
9063896 Madnani et al. Jun 2015 B1
9098211 Madnani et al. Aug 2015 B1
9110898 Chamness et al. Aug 2015 B1
9110964 Shilane et al. Aug 2015 B1
9116819 Cope et al. Aug 2015 B2
9117536 Yoon Aug 2015 B2
9122401 Zaltsman et al. Sep 2015 B2
9123422 Sharon et al. Sep 2015 B2
9124300 Olbrich et al. Sep 2015 B2
9134908 Hom et al. Sep 2015 B2
9153337 Sutardja Oct 2015 B2
9158472 Kesselman et al. Oct 2015 B2
9159422 Lee et al. Oct 2015 B1
9164891 Karamcheti et al. Oct 2015 B2
9183136 Kawamura et al. Nov 2015 B2
9189650 Jaye et al. Nov 2015 B2
9201733 Verma Dec 2015 B2
9207876 Shu et al. Dec 2015 B2
9229656 Contreras et al. Jan 2016 B1
9229810 He et al. Jan 2016 B2
9235475 Shilane et al. Jan 2016 B1
9244626 Shah et al. Jan 2016 B2
9250999 Barroso Feb 2016 B1
9251066 Colgrove et al. Feb 2016 B2
9268648 Barash et al. Feb 2016 B1
9268806 Kesselman et al. Feb 2016 B1
9286002 Karamcheti et al. Mar 2016 B1
9292214 Kalos et al. Mar 2016 B2
9298760 Li et al. Mar 2016 B1
9304908 Karamcheti et al. Apr 2016 B1
9311969 Murin Apr 2016 B2
9311970 Sharon et al. Apr 2016 B2
9323663 Karamcheti et al. Apr 2016 B2
9323667 Bennett Apr 2016 B2
9323681 Apostolides et al. Apr 2016 B2
9335942 Kumar et al. May 2016 B2
9348538 Mallaiah et al. May 2016 B2
9355022 Ravimohan et al. May 2016 B2
9384082 Lee et al. Jul 2016 B1
9384252 Akirav et al. Jul 2016 B2
9389958 Sundaram et al. Jul 2016 B2
9390019 Patterson et al. Jul 2016 B2
9396202 Drobychev et al. Jul 2016 B1
9400828 Kesselman et al. Jul 2016 B2
9405478 Koseki et al. Aug 2016 B2
9411685 Lee Aug 2016 B2
9417960 Klein Aug 2016 B2
9417963 He et al. Aug 2016 B2
9430250 Hamid et al. Aug 2016 B2
9430542 Akirav et al. Aug 2016 B2
9432541 Ishida Aug 2016 B2
9454434 Sundaram et al. Sep 2016 B2
9471579 Natanzon Oct 2016 B1
9477554 Chamness et al. Oct 2016 B2
9477632 Du Oct 2016 B2
9501398 George et al. Nov 2016 B2
9525737 Friedman Dec 2016 B2
9529542 Friedman et al. Dec 2016 B2
9535631 Fu et al. Jan 2017 B2
9552248 Miller et al. Jan 2017 B2
9552291 Munetoh et al. Jan 2017 B2
9552299 Stalzer Jan 2017 B2
9563517 Natanzon et al. Feb 2017 B1
9588698 Karamcheti et al. Mar 2017 B1
9588712 Kalos et al. Mar 2017 B2
9594652 Sathiamoorthy et al. Mar 2017 B1
9600193 Ahrens et al. Mar 2017 B2
9619321 Sharon et al. Apr 2017 B1
9619430 Kannan et al. Apr 2017 B2
9645754 Li et al. May 2017 B2
9667720 Bent et al. May 2017 B1
9710535 Aizman et al. Jul 2017 B2
9733840 Karamcheti et al. Aug 2017 B2
9734225 Akirav et al. Aug 2017 B2
9740403 Storer et al. Aug 2017 B2
9740700 Chopra et al. Aug 2017 B1
9740762 Horowitz et al. Aug 2017 B2
9747319 Bestler et al. Aug 2017 B2
9747320 Kesselman Aug 2017 B2
9767130 Bestler et al. Sep 2017 B2
9781227 Friedman et al. Oct 2017 B2
9785498 Misra et al. Oct 2017 B2
9798486 Singh Oct 2017 B1
9804925 Carmi et al. Oct 2017 B1
9811285 Karamcheti et al. Nov 2017 B1
9811546 Bent et al. Nov 2017 B1
9818478 Chung Nov 2017 B2
9829066 Thomas et al. Nov 2017 B2
9836245 Hayes et al. Dec 2017 B2
9891854 Munetoh et al. Feb 2018 B2
9891860 Delgado et al. Feb 2018 B1
9892005 Kedem et al. Feb 2018 B2
9892186 Akirav et al. Feb 2018 B2
9904589 Donlan et al. Feb 2018 B1
9904717 Anglin et al. Feb 2018 B2
9952809 Shah Feb 2018 B2
9910748 Pan Mar 2018 B2
9910904 Anglin et al. Mar 2018 B2
9934237 Shilane et al. Apr 2018 B1
9940065 Kalos et al. Apr 2018 B2
9946604 Glass Apr 2018 B1
9959167 Donlan et al. May 2018 B1
9965539 D'halluin et al. May 2018 B2
9998539 Brock et al. Jun 2018 B1
10007457 Hayes et al. Jun 2018 B2
10013177 Liu et al. Jul 2018 B2
10013311 Sundaram et al. Jul 2018 B2
10019314 Litsyn et al. Jul 2018 B2
10019317 Usvyatsky et al. Jul 2018 B2
10031703 Natanzon et al. Jul 2018 B1
10061512 Chu et al. Aug 2018 B2
10073626 Karamcheti et al. Sep 2018 B2
10082985 Hayes et al. Sep 2018 B2
10089012 Chen et al. Oct 2018 B1
10089174 Lin Oct 2018 B2
10089176 Donlan et al. Oct 2018 B1
10108819 Donlan et al. Oct 2018 B1
10146787 Bashyam et al. Dec 2018 B2
10152268 Chakraborty et al. Dec 2018 B1
10157098 Chung et al. Dec 2018 B2
10162704 Kirschner et al. Dec 2018 B1
10180875 Northcott Jan 2019 B2
10185730 Bestler et al. Jan 2019 B2
10235065 Miller et al. Mar 2019 B1
20020144059 Kendall Oct 2002 A1
20020156613 Geng Oct 2002 A1
20030105984 Masuyama et al. Jun 2003 A1
20030110205 Johnson Jun 2003 A1
20040161086 Buntin et al. Aug 2004 A1
20050001652 Malik et al. Jan 2005 A1
20050076228 Davis et al. Apr 2005 A1
20050235132 Karr et al. Oct 2005 A1
20050278460 Shin et al. Dec 2005 A1
20050283649 Turner et al. Dec 2005 A1
20060015683 Ashmore et al. Jan 2006 A1
20060114930 Lucas et al. Jun 2006 A1
20060174157 Barrail et al. Aug 2006 A1
20060248294 Nedved et al. Nov 2006 A1
20070079068 Draggon Apr 2007 A1
20070214194 Reuter Sep 2007 A1
20070214314 Reuter Sep 2007 A1
20070234016 Davis et al. Oct 2007 A1
20070268905 Baker et al. Nov 2007 A1
20080080709 Michtchenko et al. Apr 2008 A1
20080107274 Worthy May 2008 A1
20080155191 Anderson et al. Jun 2008 A1
20080295118 Liao Nov 2008 A1
20090077208 Nguyen et al. Mar 2009 A1
20090138654 Sutardja May 2009 A1
20090216910 Duchesneau Aug 2009 A1
20090216920 Lauterbach et al. Aug 2009 A1
20090327462 Adams Dec 2009 A1
20100017444 Chatterjee et al. Jan 2010 A1
20100042636 Lu Feb 2010 A1
20100094806 Apostolides et al. Apr 2010 A1
20100115070 Missimilly May 2010 A1
20100125695 Wu et al. May 2010 A1
20100162076 Sim-Tang et al. Jun 2010 A1
20100169707 Mathew et al. Jul 2010 A1
20100174576 Naylor Jul 2010 A1
20100268908 Ouyang et al. Oct 2010 A1
20110040925 Frost et al. Feb 2011 A1
20110060927 Fillingim et al. Mar 2011 A1
20110119462 Leach et al. May 2011 A1
20110219170 Frost et al. Sep 2011 A1
20110238625 Hamaguchi et al. Sep 2011 A1
20110264843 Haines et al. Oct 2011 A1
20110302369 Goto et al. Dec 2011 A1
20120011398 Eckhardt Jan 2012 A1
20120079318 Colgrove et al. Mar 2012 A1
20120089567 Takahashi et al. Apr 2012 A1
20120110249 Jeong et al. May 2012 A1
20120131253 McKnight May 2012 A1
20120158923 Mohamed et al. Jun 2012 A1
20120191900 Kunimatsu et al. Jul 2012 A1
20120198152 Terry et al. Aug 2012 A1
20120198261 Brown et al. Aug 2012 A1
20120209943 Jung Aug 2012 A1
20120226934 Rao Sep 2012 A1
20120246435 Meir et al. Sep 2012 A1
20120260055 Murase Oct 2012 A1
20120311557 Resch Dec 2012 A1
20130022201 Glew et al. Jan 2013 A1
20130036314 Glew et al. Feb 2013 A1
20130042056 Shats Feb 2013 A1
20130060884 Bernbo et al. Mar 2013 A1
20130067188 Mehra et al. Mar 2013 A1
20130073894 Xavier et al. Mar 2013 A1
20130124776 Hallak et al. May 2013 A1
20130132800 Healy et al. May 2013 A1
20130151653 Sawiki Jun 2013 A1
20130151771 Tsukahara et al. Jun 2013 A1
20130173853 Ungureanu et al. Jul 2013 A1
20130238554 Yucel et al. Sep 2013 A1
20130339314 Carpenter et al. Dec 2013 A1
20130339635 Amit et al. Dec 2013 A1
20130339818 Baker et al. Dec 2013 A1
20140040535 Lee Feb 2014 A1
20140040702 He et al. Feb 2014 A1
20140047263 Coatney et al. Feb 2014 A1
20140047269 Kim Feb 2014 A1
20140063721 Herman et al. Mar 2014 A1
20140064048 Cohen et al. Mar 2014 A1
20140068224 Fan et al. Mar 2014 A1
20140075252 Luo et al. Mar 2014 A1
20140122510 Namkoong et al. May 2014 A1
20140136880 Shankar et al. May 2014 A1
20140181402 White Jun 2014 A1
20140237164 Le et al. Aug 2014 A1
20140279936 Bernbo et al. Sep 2014 A1
20140280025 Eidson et al. Sep 2014 A1
20140289588 Nagadomi et al. Sep 2014 A1
20140330785 Isherwood et al. Nov 2014 A1
20140372838 Lou et al. Dec 2014 A1
20140380125 Calder et al. Dec 2014 A1
20140380126 Yekhanin et al. Dec 2014 A1
20150032720 James Jan 2015 A1
20150039645 Lewis Feb 2015 A1
20150039849 Lewis Feb 2015 A1
20150089283 Kermarrec et al. Mar 2015 A1
20150100746 Rychlik Apr 2015 A1
20150134824 Mickens May 2015 A1
20150153800 Lucas et al. Jun 2015 A1
20150180714 Chunn Jun 2015 A1
20150280959 Vincent Oct 2015 A1
20160246537 Kim Feb 2016 A1
20160191508 Bestler et al. Jun 2016 A1
20160378612 Hipsh et al. Dec 2016 A1
20170091236 Hayes et al. Mar 2017 A1
20170103092 Hu et al. Apr 2017 A1
20170103094 Hu et al. Apr 2017 A1
20170103098 Hu et al. Apr 2017 A1
20170103116 Hu et al. Apr 2017 A1
20170177236 Haratsch et al. Jun 2017 A1
20180039442 Shadrin et al. Feb 2018 A1
20180081958 Akirav et al. Mar 2018 A1
20180101441 Hyun et al. Apr 2018 A1
20180101587 Anglin et al. Apr 2018 A1
20180101588 Anglin et al. Apr 2018 A1
20180217756 Liu et al. Aug 2018 A1
20180307560 Vishnumolakala et al. Oct 2018 A1
20180321874 Li et al. Nov 2018 A1
20190036703 Bestler Jan 2019 A1
Foreign Referenced Citations (6)
Number Date Country
2164006 Mar 2010 EP
2256621 Dec 2010 EP
WO 02-13033 Feb 2002 WO
WO 2008103569 Aug 2008 WO
WO 2008157081 Dec 2008 WO
WO 2013032825 Jul 2013 WO
Non-Patent Literature Citations (25)
Entry
Hwang, Kai, et al. “RAID-x: A New Distributed Disk Array for I/O-Centric Cluster Computing,” HPDC '00 Proceedings of the 9th IEEE International Symposium on High Performance Distributed Computing, IEEE, 2000, pp. 279-286.
Schmid, Patrick: “RAID Scaling Charts, Part 3:4-128 kB Stripes Compared”, Tom's Hardware, Nov. 27, 2007 (http://www.tomshardware.com/reviews/RAID-SCALING-CHARTS.1735-4.html), See pp. 1-2.
Storer, Mark W. et al., “Pergamum: Replacing Tape with Energy Efficient, Reliable, Disk-Based Archival Storage,” Fast '08: 6th USENIX Conference on File and Storage Technologies, San Jose, CA, Feb. 26-29, 2008 pp. 1-16.
Ju-Kyeong Kim et al., “Data Access Frequency based Data Replication Method using Erasure Codes in Cloud Storage System”, Journal of the Institute of Electronics and Information Engineers, Feb. 2014, vol. 51, No. 2, pp. 85-91.
International Search Report and the Written Opinion of the International Searching Authority, PCT/US2015/018169, dated May 15, 2015.
International Search Report and the Written Opinion of the International Searching Authority, PCT/US2015/034302, dated Sep. 11, 2015.
International Search Report and the Written Opinion of the International Searching Authority, PCT/US2015/039135, dated Sep. 18, 2015.
International Search Report and the Written Opinion of the International Searching Authority, PCT/US2015/039136, dated Sep. 23, 2015.
International Search Report, PCT/US2015/039142, dated Sep. 24, 2015.
International Search Report, PCT/US2015/034291, dated Sep. 30, 2015.
International Search Report and the Written Opinion of the International Searching Authority, PCT/US2015/039137, dated Oct. 1, 2015.
International Search Report, PCT/US2015/044370, dated Dec. 15, 2015.
International Search Report amd the Written Opinion of the International Searching Authority, PCT/US2016/031039, dated May 5, 2016.
International Search Report, PCT/US2016/014604, dated May 19, 2016.
International Search Report, PCT/US2016/014361, dated May 30, 2016.
International Search Report, PCT/US2016/014356, dated Jun. 28, 2016.
International Search Report, PCT/US2016/014357, dated Jun. 29, 2016.
International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/016504, dated Jul. 6, 2016.
International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/024391, dated Jul. 12, 2016.
International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/026529, dated Jul. 19, 2016.
International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/023485, dated Jul. 21, 2016.
International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/033306, dated Aug. 19, 2016.
International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/047808, dated Nov. 25, 2016.
Stalzer, Mark A., “FlashBlades: System Architecture and Applications,” Proceedings of the 2nd Workshop on Architectures and Systems for Big Data, Association for Computing Machinery, New York, NY, 2012, pp. 10-14.
International Seach Report and the Written Opinion of the International Searching Authority, PCT/US2016/042147, dated Nov. 30, 2016.
Continuations (2)
Number Date Country
Parent 16050464 Jul 2018 US
Child 16700927 US
Parent 14464552 Aug 2014 US
Child 16050464 US